Processor performance tuning method and electronic device using the same

Abstract

A processor performance evaluation method and an electronic device using the same are provided. The method includes the following steps. A training dataset is established. The training dataset includes device design parameters, an actual performance test score, and an actual target design parameter for multiple tested electronic devices. A machine learning model is trained based on the training dataset. Device design parameters of an electronic device to be tested are received. Based on the device design parameters of the electronic device to be tested, the trained machine learning model is used to predict a predicted target design parameter of the electronic device to be tested. An operation is performed based on the predicted target design parameter.

Description

[Technical Field]

[0001] This disclosure relates to the analysis of the processing performance of a computer device, and more particularly to a processor performance tuning method and an electronic device using the method. [Previous Technology]

[0002] In today's computing systems, processor performance is considered one of the core indicators for evaluating computer system performance. From the perspective of computer system design, processor performance is closely related to factors such as hardware specifications, mechanical design, heat dissipation modules, and circuit implementation. In the current technological environment, effectively configuring and optimizing various device design parameters to enable the processor to achieve optimal performance under specific conditions remains a complex and difficult task. This is because the system design of each computer device involves numerous interrelated factors, including hardware architecture, mechanical design, heat dissipation solutions, and circuit implementation, which are closely linked to actual usage scenarios. Currently, finding the optimal settings for device design parameters is not simple and often relies on past practical experience or repeated, time-consuming testing. Traditionally, developers need to conduct extensive experiments and performance tests under different settings, which not only consumes a lot of time and resources but may also lead to uncertainty in the trial-and-error process. [Summary of the Invention]

[0003] In view of this, the present disclosure proposes a method for tuning the performance of electronic devices and processors, which can solve the above-mentioned technical problems.

[0004] This disclosure provides a processor performance tuning method, the method comprising the following steps: Establishing a training dataset. This training dataset includes device design parameters, actual performance test scores, and actual target design parameters for each of a plurality of tested electronic devices. Training a machine learning model based on the training dataset. Receiving device design parameters of an electronic device under test. Predicting a predicted target design parameter of the electronic device under test using the trained machine learning model based on the device design parameters of the electronic device under test. Performing an operation based on the predicted target design parameter.

[0005] This disclosure provides an electronic device including a storage device and a processor. The processor is coupled to the storage device and configured to perform the following operations: Establishing a training dataset. This training dataset includes device design parameters, actual performance test scores, and actual target design parameters for each of a plurality of tested electronic devices. Training a machine learning model based on the training dataset. Receiving device design parameters of an electronic device under test. Predicting a predicted target design parameter of the electronic device under test using the trained machine learning model based on the device design parameters of the electronic device under test. Performing an operation based on the predicted target design parameter.

[0006] Based on the above, in the embodiments disclosed herein, a training dataset including device design parameters of multiple tested electronic devices, actual performance test scores, and actual target design parameters can be used to train a machine learning model. Subsequently, the trained machine learning model can predict a predicted target design parameter of the electronic device under test based on the device design parameters, and perform an operation based on the predicted target design parameter. Therefore, the optimal parameter settings to ensure processor performance meets requirements can be determined more efficiently, thereby shortening product development and testing timelines.

Implementation Method

[0007] Some embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. Component symbols used in the following description are considered the same or similar components when they appear in different drawings. These embodiments are only a part of this disclosure and do not reveal all possible implementations of this disclosure. More precisely, these embodiments are merely examples of the methods and apparatus within the scope of this patent application.

[0008] FIG1 is a block diagram of an electronic device according to an embodiment of the present disclosure. Referring to FIG1, the electronic device 100 includes an input device 110, a display device 120, a storage device 130, a transceiver 140, and a processor 150. The electronic device 100 may be, for example, a tablet computer, a laptop computer, a desktop computer, an all-in-one computer, or a server, etc., a computer device with computing capabilities, and the present disclosure is not limited thereto.

[0009] Input device 110 is used to receive user input. Input device 110 may be, for example, a mouse, keyboard, touch input device, or microphone, etc.

[0010] The display device 120 is, for example, a liquid crystal display (LCD), a light-emitting diode (LED) display, an organic light-emitting diode (OLED) display, or other types of displays, and this disclosure is not limited thereto. In the embodiments disclosed herein, the display device 120 may be used to display a user interface.

[0011] Storage device 130 is used to temporarily or permanently store data, such as files, documents, images, instructions, code, software modules (e.g., operating systems, applications, drivers), etc. Specifically, storage device 130 may include volatile storage circuitry. Volatile storage circuitry is used to store data in a volatile manner. For example, volatile storage circuitry may include random access memory (RAM) or similar volatile storage media. Furthermore, storage device 130 may also include non-volatile storage circuitry. Non-volatile storage circuitry is used to store data in a non-volatile manner. For example, non-volatile storage circuitry may include read-only memory (ROM), solid-state drive (SSD), and / or traditional hard disk drive (HDD) or similar non-volatile storage media. The number of storage devices 130 may be one or more, and this disclosure does not limit this.

[0012] Transceiver 140 can transmit and receive signals wirelessly or via a wired connection. The transceiver can also perform operations such as low-noise amplification, impedance matching, mixing, up- or down-frequency conversion, filtering, amplification, and similar operations. Electronic device 100 can receive and transmit data via transceiver 140, such as via the Internet. In some embodiments, electronic device 100 may also include an antenna (not shown) for receiving radio frequency signals.

[0013] The processor 150 is coupled to the input device 110, the display device 120, the storage device 130, and the transceiver 140, and may be a general purpose processor, a special purpose processor, a conventional processor, a central processing unit (CPU), a graphics processing unit (GPU), a vision processing unit (VPU), a neural network processing unit (NPU) and / or a tensor processing unit (TPU), a digital signal processor, multiple microprocessors, one or more microprocessors incorporating a digital signal processor core, a controller, a microcontroller, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), any other type of integrated circuit, a state machine, a processor based on an advanced reduced instruction set machine (ARM), and the like. The processor 150 can access and execute instructions or program code recorded in the storage device 130 to implement the processor performance tuning method in this disclosed embodiment.

[0014] In the embodiments disclosed herein, the design data accumulated over the years can be used to find the complex relationship between various design parameters and processor performance using machine learning. This allows for more efficient identification of design parameter settings that enable the processor performance to meet requirements when developing new devices, thereby significantly shortening the design and verification time.

[0015] FIG2 is a flowchart of a processor performance tuning method according to an embodiment of the present disclosure, and the method flow of FIG2 can be implemented by the various components of the electronic device 100 of FIG1. ​​Please refer to FIG1 and FIG2 at the same time. The steps of the processor performance tuning method of this embodiment will be described below with reference to the various components of the electronic device 100 in FIG1.

[0016] In step S210, the processor 150 establishes a training dataset. This training dataset includes device design parameters, actual performance test scores, and actual target design parameters for each of the tested electronic devices. Here, each tested electronic device is a computer device including a processor, and each tested electronic device can execute a performance test program to obtain the actual performance test score of the processor. The processor of each tested electronic device can be a central processing unit (CPU), a graphics processing unit (GPU), or a neural network unit (NPU), etc.

[0017] In different embodiments, all tested electronic devices may be laptops, servers, desktop computers, all-in-one computers, or tablet computers, etc. Furthermore, in some embodiments, the plurality of tested electronic devices may be multiple laptops with different device specifications. In some embodiments, the plurality of tested electronic devices may be multiple servers with different device specifications. In some embodiments, the plurality of tested electronic devices may be multiple tablet computers with different device specifications, etc.

[0018] Furthermore, the training dataset may include multiple feature variables and at least one target variable for training a machine learning model. The multiple feature variables are the primary basis for the machine learning model's learning. The relationship between the feature variables and the target variable is the focus of model learning during training. In some embodiments, the processor 150 may use multiple device design parameters and actual performance test scores of multiple tested electronic devices as multiple feature variables, and use the actual target design parameters of the multiple tested electronic devices as a target variable. Alternatively, in some embodiments, the processor 150 may use multiple device design parameters of multiple tested electronic devices as multiple feature variables, and use the actual target design parameters and actual performance test scores of the multiple tested electronic devices as multiple target variables.

[0019] In some embodiments, the device design parameters include at least one of a hardware specification parameter and a processor performance management parameter. The device design parameters may include design features, specification parameters, and configurable parameter settings of the electronic device, etc.

[0020] In some embodiments, the hardware specifications include at least one of a processor specification and a thermal specification. The processor specification is the specifications of the processor, such as cache memory capacity, number of performance cores (P-cores), number of efficiency cores (E-cores), number of threads, base clock frequency, boost clock frequency, thermal design power (TDP), or processor manufacturing process (e.g., 10 nanometers), etc. The thermal specification is the specifications of the heat dissipation module, such as fan size, fan speed, number of heat pipes, heatsink size, or heatsink material, etc. Furthermore, the hardware specifications may also include motherboard material or number of motherboard layers, etc.

[0021] In some embodiments, the processor performance management parameters include at least one of a power consumption control parameter and a thermal management parameter. The processor performance management parameters relate to the control of processor power consumption and heat to ensure that the system operates in a high-performance and stable state. The power consumption control parameter may include a maximum power limit (PL) and a turbo time parameter (Tau), etc. The maximum power limit (PL) may further include a long-term maximum power limit (Power Limit 1, PL 1), a short-term maximum power limit (Power Limit 2, PL 2), or an overclocking maximum power limit (Power Limit 3, PL 3). The thermal management parameter may include a temperature limit parameter. This temperature limit parameter may be, for example, a Thermal Control Circuit (TCC) threshold or a TCC configurable offset, etc. Furthermore, the thermal management parameter may also include device thickness (Z-height), etc.

[0022] In some embodiments, a performance test program is executed by each tested electronic device to obtain an actual performance test score for each tested electronic device based on the device design parameters and actual target design parameters of each tested electronic device. The performance test program is used to measure the performance of a processor (e.g., CPU) under different load conditions. Each tested electronic device can execute the performance test program by running a performance benchmark tool. The aforementioned performance benchmark tools are, for example, Cinebench R23 (CR23), GeekBench, SiSoftware Sandra, or PassMark, etc., and this disclosure is not limited thereto. When the processor in each tested electronic device executes the performance test program, the performance benchmark tool can output the actual performance test score of the processor in each tested electronic device. For example, the actual performance test score can be the CR23 Multi-Threaded (MT) score. That is, given that the various hardware configurations and parameter configurations of each tested electronic device are determined, the corresponding actual performance test score can be obtained by actually executing a performance test program using a performance benchmark tool on these tested electronic devices. The actual performance test scores of these tested electronic devices can be collected and recorded. Processor 150 can obtain these actual performance test scores by reading files or receiving user input. Processor 150 can then match these actual performance test scores with corresponding device design parameters to generate a training dataset.

[0023] In some embodiments, the actual target design parameters are the device design parameters that the developer wants to find, that is, the target variables of the machine learning model. In some embodiments, the actual target design parameters may include a short-term maximum power consumption limit (Power Limit 2, PL2).

[0024] In step S220, the processor 150 trains a machine learning model based on the training dataset. In some embodiments, the machine learning model includes a supervised machine learning model applying a supervised machine learning algorithm. The aforementioned supervised machine learning algorithm may be a regression analysis algorithm, an extreme gradient boosting (XGboost) algorithm, a bootstrap aggregating (Bagged) algorithm, a neural network algorithm, a random forest algorithm, an elastic net algorithm, a least absolute shrinkage and selection operator (LASSO) algorithm, a k-nearest neighbor classification (KNN) algorithm, a support vector regression algorithm, or an ensemble learning algorithm, etc., and the present invention is not limited thereto.

[0025] In the embodiments disclosed herein, the processor 150 can utilize a training dataset to perform machine learning, analyze, and establish a correlation model between device design parameters and processor performance. Specifically, the processor 150 can establish a machine learning model based on device design information accumulated from numerous tested electronic devices in the past, and the trained machine learning model can be recorded in the storage device 130. That is, the machine learning model is a predictive model created by the processor 150 after performing machine learning based on the training dataset, used to predict the optimal settings of one or more target design parameters, which enable the processor performance to exceed test standards.

[0026] In some embodiments, the processor 150 may select multiple important feature variables based on feature selection algorithms in feature engineering. The processor 150 may train a machine learning model based on these important feature variables and the target variable in the training dataset.

[0027] In step S230, the processor 150 receives device design parameters of an electronic device under test. In some embodiments, the processor 150 may receive the device design parameters of the electronic device under test through the input device 110. That is, when a developer is developing the electronic device under test, the developer can provide the device design parameters of the electronic device under test to the trained machine learning model.

[0028] In step S240, the processor 150 predicts a target design parameter for the electronic device under test using a trained machine learning model based on the device design parameters of the electronic device under test. In some embodiments, the target design parameter includes a short-term maximum power consumption limit (PL2). Specifically, the processor 150 can use the trained machine learning model to perform model inference. Through the inference of the machine learning model, the processor 150 maps these device design parameters of the electronic device under test to the expected target design parameter (e.g., short-term maximum power consumption limit), thereby helping developers quickly make appropriate design adjustments to achieve the required performance requirements.

[0029] In step S250, processor 150 performs an operation based on the predicted target design parameters. In some embodiments, processor 150 may display and record the predicted target design parameters of the electronic device under test. In this way, developers can learn the set values ​​of the predicted target design parameters of the electronic device under test by viewing the user interface displayed on display device 120. Furthermore, in some embodiments, processor 150 may also record multiple target set values ​​of the predicted target design parameters under different design schemes. For example, a device design parameter has a first set value in a first design scheme, and a device design parameter has a second set value in a second design scheme. Processor 150 can determine which design scheme to use by analyzing these target set values ​​of the predicted target design parameters.

[0030] For example, please refer to FIG3, which is a schematic diagram of a user interface for tuning processor performance according to an embodiment of the present disclosure. The processor 150 can display the user interface U31 through the display device 120. Developers can input device design parameters and expected performance test scores of the electronic device under test using the user interface U31, and view the user interface U31 to know the predicted target design parameters predicted by the machine learning model.

[0031] In this example, the developer can select the processor model in input field 311, and the processor 150 can obtain the processor specification parameters based on the selected processor model. The developer can enter the expected performance test score in input field 312. The developer can enter the power consumption control parameters in input field 313. After completing the setting and input of these device design parameters, the developer can click on user interface option 316 to start the machine learning model for inference. Subsequently, the predicted target design parameters 314 predicted by the machine learning model can be displayed in the user interface U31, and the developer can click on user interface option 315 to save the predicted target design parameters 314.

[0032] As can be seen from the foregoing, in the embodiments disclosed herein, the target variable of the machine learning model may or may not include the performance test score. Examples will be provided below for each.

[0033] FIG4 is a flowchart of a processor performance tuning method according to an embodiment of the present disclosure, and the method flow of FIG4 can be implemented by the various components of the electronic device 100 in FIG1. ​​Please refer to FIG1 and FIG4 at the same time. The steps of the processor performance tuning method of this embodiment will be described below with reference to the various components of the electronic device 100 in FIG1.

[0034] In step S410, the processor 150 establishes a training dataset. This training dataset includes a device design parameter, an actual performance test score, and an actual target design parameter for each of the multiple tested electronic devices. For example, Table 1 shows a portion of the training data in the training dataset for a particular tested electronic device. Core count Number of threads cache capacity Accelerate clock frequency PL1 (max) PL1 (min) Tcc CR23 score PL2 6 twenty two twenty four 5.1 65 30 110 15710 48 6 twenty two twenty four 5.1 65 30 110 16840 56 6 twenty two twenty four 5.1 65 30 110 18192 72 Table 1. In addition, Table 2 contains some training data from the same training dataset for another tested electronic device. Core count Number of threads cache capacity Accelerate clock frequency PL1 (max) PL1 (min) Tcc CR23 score PL2 6 twenty two twenty four 4.8 65 45 110 15331 52 6 twenty two twenty four 4.8 65 45 110 14908 60 6 twenty two twenty four 4.8 65 45 110 14818 76 In the examples in Tables 1 and 2, the actual target design parameters for each tested electronic device can be PL2.

[0035] In step S420, the processor 150 trains a machine learning model based on the training dataset. In step S430, the processor 150 receives device design parameters of an electronic device under test. Detailed implementation details can be found in the foregoing embodiments and will not be repeated here.

[0036] In step S440, processor 150 receives the expected performance test score of the electronic device under test. It should be noted that the expected performance test score can be a value set by the developer. In step S460, processor 150 inputs the device design parameters of the electronic device under test and the expected performance test score into a trained machine learning model to predict the predicted target design parameters of the electronic device under test. In step S470, processor 150 performs an operation based on the predicted target design parameters.

[0037] Please refer to Figure 5, which is a schematic diagram of a processor performance tuning method according to an embodiment of the present disclosure. The processor 150 can collect hardware specification parameters 511, processor performance management parameters 512, actual performance test scores 513, and actual target design parameters 514 from multiple tested electronic devices, and establish a training dataset TD51 accordingly. This training dataset TD51 includes feature variables FV5 and target variables TV5. In this example, feature variables FV5 may include hardware specification parameters 511, processor performance management parameters 512, and actual performance test scores 513, while target variables TV5 may include actual target design parameters 514. The processor 150 can train a machine learning model based on the training dataset TD51 to establish a machine learning model M51. Then, the processor 150 can input the hardware specification parameters 521 and processor performance management parameters 522 of the electronic device to be tested provided by the developer, as well as the expected performance test score 513, into the machine learning model M51. The machine learning model M51 can output the predicted target design parameter 524.

[0038] For example, a trained machine learning model can map the hardware specifications, processor performance management parameters, and expected performance test scores input by the developer to a short-term maximum power limit (PL2), which allows the processor performance of the electronic device under test to reach the expected performance test score. In other words, when the developer provides hardware specifications, processor performance management parameters, and the expected performance test score to be achieved, the machine learning model can deduce the ideal setting value for the short-term maximum power limit.

[0039] FIG6 is a flowchart of a processor performance tuning method according to an embodiment of the present disclosure, and the method flow of FIG6 can be implemented by the various components of the electronic device 100 in FIG1. ​​Please refer to FIG1 and FIG6 at the same time. The steps of the processor performance tuning method of this embodiment will be described below with reference to the various components of the electronic device 100 in FIG1.

[0040] In step S610, processor 150 establishes a training dataset. This training dataset includes device design parameters, actual performance test scores, and actual target design parameters for each of the multiple tested electronic devices. In step S620, processor 150 trains a machine learning model based on the training dataset. In step S630, processor 150 receives device design parameters for an electronic device under test.

[0041] In step S640, the processor 150 inputs the device design parameters of the electronic device under test into a trained machine learning model to predict the target design parameters and a predicted performance test score of the electronic device under test. In step S650, the processor 150 performs an operation based on the predicted target design parameters.

[0042] Please refer to Figure 7, which is a schematic diagram of a processor performance tuning method according to an embodiment of the present disclosure. The processor 150 can collect hardware specification parameters 711, processor performance management parameters 712, actual performance test scores 713, and actual target design parameters 714 from multiple tested electronic devices, and establish a training dataset TD71 accordingly. This training dataset TD71 includes feature variables FV7 and target variables TV7. In this example, feature variables FV7 may include hardware specification parameters 711 and processor performance management parameters 712, while target variables TV7 may include actual performance test scores 713 and actual target design parameters 714. The processor 150 can train a machine learning model based on the training dataset TD71 to establish a machine learning model M71. Then, the processor 150 can input the hardware specification parameters 721 and processor performance management parameters 722 of the electronic device under test provided by the developer into the machine learning model M71. The machine learning model M71 can output the predicted target design parameter 724 set value and the expected performance test score 723.

[0043] For example, a trained machine learning model can map the hardware specifications and processor performance management parameters input by the developer to a short-term maximum power consumption limit and an expected performance test score. This short-term maximum power consumption limit enables the processor performance of the electronic device under test to reach the expected performance test score. In other words, when the developer provides hardware specifications and processor performance management parameters, the machine learning model can infer the expected performance test score and the corresponding short-term maximum power consumption limit (PL2) achievable under this design scheme.

[0044] In summary, in the embodiments disclosed herein, a training dataset including device design parameters of multiple tested electronic devices, actual performance test scores, and actual target design parameters can be used to train a machine learning model. Subsequently, the trained machine learning model can predict a predicted target design parameter of the electronic device under test based on its device design parameters, and perform an operation based on the predicted target design parameter. Therefore, the optimal parameter settings to ensure processor performance meets requirements can be determined more efficiently, thereby shortening product development and testing timelines.

[0045] In addition, when specifications change during the device design phase, trained machine learning models can be used to predict target design parameters that conform to the existing design scheme. This avoids the need for repeated parameter adjustments and performance testing, thus shortening the device development time. Since machine learning models can infer parameter settings for various design schemes based on past design data, developers can easily evaluate the merits and rationality of various design schemes.

[0046] Although this disclosure has been disclosed above with reference to embodiments, it is not intended to limit this disclosure. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0047] FIG1 is a block diagram of an electronic device according to an embodiment of the present disclosure. FIG2 is a flowchart of a processor performance tuning method according to an embodiment of the present disclosure. FIG3 is a schematic diagram of an operation interface for tuning processor performance according to an embodiment of the present disclosure. FIG4 is a flowchart of a processor performance tuning method according to an embodiment of the present disclosure. FIG5 is a schematic diagram of a processor performance tuning method according to an embodiment of the present disclosure. FIG6 is a flowchart of a processor performance tuning method according to an embodiment of the present disclosure. FIG7 is a schematic diagram of a processor performance tuning method according to an embodiment of the present disclosure.

Claims

1. A processor performance tuning method, the method comprising: Establish a training dataset, wherein the training dataset includes a device design parameter, an actual performance test score, and an actual target design parameter for each of a plurality of tested electronic devices; train a machine learning model based on the training dataset; receive the device design parameter of an electronic device under test; predict a predicted target design parameter of the electronic device under test using the trained machine learning model based on the device design parameter of the electronic device under test, wherein the predicted target design parameter includes an optimal setting value for at least one target design parameter used by the electronic device under test inferred by the machine learning model based on the device design parameter; and perform an operation based on the predicted target design parameter.

2. The processor performance tuning method as described in claim 1 further includes: A performance test procedure is performed on each of the plurality of tested electronic devices to obtain the actual performance test score of each of the plurality of tested electronic devices based on the device design parameters and the actual target design parameters.

3. The processor performance tuning method as described in claim 1, wherein the device design parameters include at least one of a hardware specification parameter and a processor performance management parameter.

4. The processor performance tuning method as described in claim 3, wherein the hardware specifications include at least one of a processor specification and a thermal specification.

5. The processor performance tuning method as described in claim 3, wherein the processor performance management parameters include at least one of a power consumption control parameter and a thermal management parameter.

6. The processor performance tuning method as described in claim 1, wherein the step of performing the operation according to the predicted target design parameters includes: Display and record the predicted target design parameters of the electronic device under test.

7. The processor performance tuning method as described in claim 1, wherein the actual target design parameters include a first short-time maximum power limit (Power Limit 2, PL2), and the predicted target design parameters include a second short-time maximum power limit.

8. The processor performance tuning method as described in claim 1 further includes: Receive a desired performance test score for the electronic device under test; The step of predicting the target design parameters of the electronic device under test using the trained machine learning model based on the device design parameters of the electronic device under test includes: inputting the device design parameters of the electronic device under test and the expected performance test score into the trained machine learning model to predict the target design parameters of the electronic device under test.

9. The processor performance tuning method as described in claim 1, wherein the step of predicting the target design parameters of the electronic device under test using the trained machine learning model based on the device design parameters of the electronic device under test includes: The device design parameters of the electronic device under test are input into the trained machine learning model to predict the predicted target design parameters and a predicted performance test score of the electronic device under test.

10. An electronic device comprising: A storage device; and at least one processor, coupled to the storage device, configured to: establish a training dataset, wherein the training dataset includes a device design parameter, an actual performance test score, and an actual target design parameter for each of a plurality of tested electronic devices; train a machine learning model based on the training dataset; receive the device design parameter of an electronic device under test; predict a predicted target design parameter of the electronic device under test using the trained machine learning model based on the device design parameter of the electronic device under test, wherein the predicted target design parameter includes an optimal setting of at least one target design parameter for use by the electronic device under test inferred by the machine learning model based on the device design parameter; and perform an operation based on the predicted target design parameter.

Images