Memory management method, memory storage device and memory control circuit unit

Abstract

The present invention provides a memory management method, a memory storage device, and a memory control circuit unit. The method includes: setting a timer corresponding to a first physical unit after powering on; performing a read operation on the first physical unit and determining whether a data error condition is met; and marking the first physical unit as a bad physical unit if the data error condition is met and elapsed time indicated by the timer is less than a time threshold.

Description

Technical Field

[0001] This disclosure relates to a memory management method for marking bad physical units, a memory storage device, and a memory control circuit unit. Prior Technology

[0002] The rapid growth of portable electronic devices such as mobile phones and laptops in recent years has led to a surge in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memory) are ideally suited for integration into the aforementioned portable electronic devices due to their non-volatile data, low power consumption, small size, and lack of mechanical structure.

[0003] During long-term use of rewritable non-volatile memory modules, the reliability of data stored in blocks gradually decreases, especially as the number of erases on certain blocks increases. These blocks become more susceptible to interference, leading to an increase in the number of faulty bits. When the number of faulty bits in a block exceeds its fault tolerance capacity, the block is marked as a bad block and taken out of service. Besides bad blocks resulting from deterioration in lifespan, some blocks may also have inherent defects from the manufacturing process due to variations or other production issues, making them prone to errors even under normal use. Early marking and management of these defective blocks are crucial for the reliability of rewritable non-volatile memory modules. Summary of the Invention

[0004] This disclosure proposes a memory management method, a memory storage device, and a memory control circuit unit that can mark physical units that are defective during production, and can also avoid incorrectly marking physical units due to endurance failure.

[0005] This disclosure proposes a memory management method for a rewritable non-volatile memory module, which includes multiple physical units. The memory management method includes: after power-on, setting a timer corresponding to a first physical unit; executing a read procedure on the first physical unit and determining whether a data error condition is met; and when the data error condition is met and the elapsed time indicated by the timer is less than a time threshold, marking the first physical unit as a bad physical unit.

[0006] In one embodiment of this disclosure, the memory management method further includes resetting a timer upon power-on.

[0007] In one embodiment of this disclosure, the memory management method further includes resetting a timer when the first physical unit is programmed.

[0008] In one embodiment of this disclosure, the above-described reading procedure includes a hardware decoding procedure for detecting multiple error bits in the first entity unit. The step of determining whether the data error condition is met includes: if the number of error bits is greater than a certain threshold, increasing the error count; and if the error count is greater than a certain threshold, determining that the data error condition is met.

[0009] In one embodiment of this disclosure, the step of determining whether the data error condition is met includes: when the hardware decoding program fails, executing the software decoding program and increasing the error count; if the error count is greater than the critical value for one error, determining that the data error condition is met.

[0010] In one embodiment of this disclosure, the aforementioned error count threshold is greater than or equal to 2. The memory management method further includes resetting the error count upon power-on.

[0011] In one embodiment of this disclosure, the memory management method includes: executing a software decoding program when the hardware decoding program fails; and executing cross-frame decoding if the software decoding program fails. The step of determining whether the data error condition is met is based on non-cross-frame error correction information.

[0012] From another perspective, embodiments of the present invention provide a memory storage device, comprising: a connection interface unit for coupling to a host system; a rewritable non-volatile memory module including a plurality of physical units; and a memory control circuit unit coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit performs multiple steps: after power-on, setting a timer corresponding to a first physical unit; executing a read procedure on the first physical unit and determining whether a data error condition is met; and when the data error condition is met and the elapsed time indicated by the timer is less than a time threshold, marking the first physical unit as a bad physical unit.

[0013] From another perspective, embodiments of the present invention provide a memory control circuit unit for controlling a rewritable non-volatile memory module. The memory control circuit unit includes: a host interface for coupling to a host system; a memory interface for coupling to the rewritable non-volatile memory module; and a memory management circuit coupled to both the host interface and the memory interface. The memory management circuit performs multiple steps: setting a timer after power-on, this timer corresponding to a first physical unit; executing a read procedure on the first physical unit and determining whether a data error condition is met; and when the data error condition is met and the elapsed time indicated by the timer is less than a time threshold, marking the first physical unit as a bad physical unit.

[0014] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings for detailed explanation. Simple Explanation of the Diagram

[0015] Figure 1 is a schematic diagram of a host system, memory storage device and input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 is a schematic diagram of a host system, memory storage device and I / O device according to an exemplary embodiment of the present invention. Figure 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention. Figure 4 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention. Figure 5 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Figure 6 is a schematic diagram illustrating the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. Figure 7 is a flowchart illustrating a memory management method according to an embodiment. Figure 8 is a schematic diagram illustrating the operation of a timer based on a scenario. Figure 9 is a schematic diagram illustrating the operation of the timer based on another scenario. Figure 10 is a flowchart illustrating a memory management method according to an embodiment. Figure 11 is a flowchart illustrating a memory management method according to another embodiment. Implementation

[0016] Some embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Component symbols used in the following description are considered identical or similar when they appear in different drawings. These embodiments are only a part of the present invention and do not disclose all possible implementations of the invention. More precisely, these embodiments are merely examples of systems and methods within the scope of the present invention's patent application.

[0017] The terms "first," "second," etc., used in this article do not specifically refer to order or sequence; they are merely used to distinguish elements or operations described using the same technical terms.

[0018] Generally, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as a control circuit). The memory storage device can be used with a host system to allow the host system to write data to or read data from the memory storage device.

[0019] Figure 1 is a schematic diagram of a host system, memory storage device, and input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 is a schematic diagram of a host system, memory storage device, and I / O device according to an exemplary embodiment of the present invention.

[0020] Referring to Figures 1 and 2, the host system 11 may include a processor 111, random access memory (RAM) 112, read-only memory (ROM) 113, and a data transfer interface 114. The processor 111, RAM 112, ROM 113, and ROM 114 may be coupled to a system bus 110.

[0021] In one exemplary embodiment, the host system 11 may be coupled to the memory storage device 10 via a data transfer interface 114. For example, the host system 11 may store data in or read data from the memory storage device 10 via the data transfer interface 114. Furthermore, the host system 11 may be coupled to the I / O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to or receive input signals from the I / O device 12 via the system bus 110.

[0022] In one exemplary embodiment, the processor 111, random access memory 112, read-only memory 113, and data transfer interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. Through the data transfer interface 114, the motherboard 20 may be coupled to the memory storage device 10 via wired or wireless means.

[0023] In one exemplary embodiment, the memory storage device 10 may be, for example, a USB flash drive 201, a memory card 202, a solid-state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a Near Field Communication (NFC) memory storage device, a WiFi wireless fax memory storage device, a Bluetooth memory storage device, or a Bluetooth Low Energy (BLE) memory storage device (e.g., iBeacon), or other memory storage devices based on various wireless communication technologies. Furthermore, the motherboard 20 may also be coupled to various I / O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 via the system bus 110. For example, in one exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

[0024] In one exemplary embodiment, the host system 11 is a computer system. In one exemplary embodiment, the host system 11 may be any system that can substantially cooperate with a memory storage device to store data. In one exemplary embodiment, the memory storage device 10 and the host system 11 may respectively include the memory storage device 30 and the host system 31 of FIG3.

[0025] Figure 3 is a schematic diagram illustrating a host system and a memory storage device according to an exemplary embodiment of the present invention. Referring to Figure 3, the memory storage device 30 can be used in conjunction with the host system 31 to store data. For example, the host system 31 can be a system such as a digital camera, camcorder, communication device, audio player, video player, or tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly couple memory modules to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0026] Figure 4 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention. Referring to Figure 4, the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable non-volatile memory module 43.

[0027] The interface unit 41 is used to couple to the host system 11. The memory storage device 10 can communicate with the host system 11 via the interface unit 41. In an exemplary embodiment, the interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In one exemplary embodiment, the connection interface unit 41 may also conform to the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The interface unit 41 may be packaged in the same chip as the memory control circuit unit 42, or the interface unit 41 may be disposed outside the chip containing the memory control circuit unit 42.

[0028] The memory control circuit unit 42 is coupled to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to execute multiple logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 43 according to the instructions of the host system 11.

[0029] The rewritable non-volatile memory module 43 is used to store the data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory cell), other flash memory modules, or other memory modules with the same characteristics.

[0030] Each memory cell in the rewritable non-volatile memory module 43 stores one or more bits by changing a voltage (hereinafter also referred to as the threshold voltage). Specifically, each memory cell has a charge trapping layer between its control gate and channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell". With the change of the threshold voltage, each memory cell in the rewritable non-volatile memory module 43 has multiple storage states. By applying a read voltage, it is possible to determine which storage state a memory cell belongs to, thereby retrieving the one or more bits stored in that memory cell.

[0031] In one exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 43 can constitute multiple physical programming units, and these physical programming units can constitute multiple physical erase units. Specifically, memory cells on the same word line can form one or more physical programming units. If each memory cell can store more than two bits, then physical programming units on the same word line can be classified into at least lower physical programming units and upper physical programming units. For example, the least significant bit (LSB) of a memory cell belongs to a lower physical programming unit, and the most significant bit (MSB) of a memory cell belongs to an upper physical programming unit. Generally, in MLC NAND flash memory, the write speed of lower physical programming units is greater than that of upper physical programming units, and / or the reliability of lower physical programming units is higher than that of upper physical programming units.

[0032] In one exemplary embodiment, a physical programming unit is the smallest unit of programming. That is, a physical programming unit is the smallest unit for writing data. For example, a physical programming unit can be a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units may include a data bit area and a redundancy bit area. The data bit area contains multiple physical sectors for storing user data, while the redundancy bit area is used to store system data (e.g., management data such as error correction codes). In one exemplary embodiment, the data bit area contains 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other exemplary embodiments, the data bit area may also contain 8, 16, or more or fewer physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, a physical erase unit is the smallest unit of erasure. That is, each physical erase unit contains one of the minimum number of memory cells to be erased. For example, the entity erasure unit is an entity block.

[0033] Figure 5 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Referring to Figure 5, the memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, and a memory interface 53.

[0034] The memory management circuit 51 controls the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has multiple control instructions, and these control instructions are executed when the memory storage device 10 is operating to perform operations such as writing, reading, and erasing data. The following description of the operation of the memory management circuit 51 is equivalent to the description of the operation of the memory control circuit unit 42 and the memory storage device 10.

[0035] In one exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 10 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

[0036] In one exemplary embodiment, the control instructions of the memory management circuit 51 can also be stored in program code format in a specific area of ​​the rewritable non-volatile memory module 43 (e.g., a system area in the memory module dedicated to storing system data). Furthermore, the memory management circuit 51 includes a microprocessor unit (not shown), read-only memory (not shown), and random access memory (not shown). Specifically, this read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit first executes this boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. Subsequently, the microprocessor unit executes these control instructions to perform operations such as writing, reading, and erasing data.

[0037] In one exemplary embodiment, the control instructions for the memory management circuit 51 can also be implemented in hardware. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, memory write circuit, memory read circuit, memory erase circuit, and data processing circuit are coupled to the microcontroller. The memory cell management circuit is used to manage the memory cells or groups of memory cells in the rewritable non-volatile memory module 43. The memory write circuit is used to issue a sequence of write instructions to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit is used to issue a sequence of read instructions to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erasure circuit is used to issue an erasure command sequence to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit is used to process data to be written to the rewritable non-volatile memory module 43 and data to be read from the rewritable non-volatile memory module 43. The write command sequence, read command sequence, and erase command sequence may each include one or more program codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read, and erase operations. In an exemplary embodiment, the memory management circuit 51 may also issue other types of command sequences to the rewritable non-volatile memory module 43 to instruct it to perform corresponding operations.

[0038] The host interface 52 is coupled to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to obtain and identify instructions and data transmitted by the host system 11. For example, instructions and data transmitted by the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited thereto, and the host interface 52 may also be compatible with the SATA standard, PATA standard, IEEE 1394 standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard, or other suitable data transmission standards.

[0039] The memory interface 53 is coupled to the memory management circuit 51 and is used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, data to be written to the rewritable non-volatile memory module 43 is converted into a format acceptable to the rewritable non-volatile memory module 43 via the memory interface 53. Specifically, if the memory management circuit 51 needs to access the rewritable non-volatile memory module 43, the memory interface 53 will transmit a corresponding instruction sequence. For example, these instruction sequences may include a write instruction sequence indicating the writing of data, a read instruction sequence indicating the reading of data, an erase instruction sequence indicating the erasure of data, and corresponding instruction sequences for indicating various memory operations (e.g., changing the read voltage level or performing garbage collection (GC) operations, etc.). These instruction sequences are generated, for example, by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 via the memory interface 53. These instruction sequences may include one or more signals, or data on a bus. These signals or data may include instruction codes or program code. For example, a read instruction sequence may include information such as the read identifier and memory address.

[0040] In one exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54, a buffer memory 55, and a power management circuit 56.

[0041] Error checking and correction circuit 54 is coupled to memory management circuit 51 and is used to perform error checking and correction operations to ensure data integrity. Specifically, when memory management circuit 51 obtains a write command from host system 11, error checking and correction circuit 54 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to the write command, and memory management circuit 51 writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code to rewritable non-volatile memory module 43. Subsequently, when memory management circuit 51 reads data from rewritable non-volatile memory module 43, it simultaneously reads the corresponding error correcting code and / or error detecting code for this data, and error checking and correction circuit 54 performs error checking and correction operations on the read data based on the error correcting code and / or error detecting code. For example, the error checking and correction circuit 54 can use various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), and Exclusive OR (XOR) code to encode and decode data.

[0042] The basic unit of encoding / decoding performed by the error checking and correction circuit 54 is a frame (also called a data frame). A frame may include multiple data bits. In one exemplary embodiment, a frame includes 256 bits. However, in another exemplary embodiment, a frame may also include more (e.g., 4K bytes) or fewer bits. The error checking and correction circuit 54 can perform single-frame encoding and decoding of data within a single frame, and it can also perform cross-frame encoding and decoding of data across multiple frames. When performing cross-frame encoding and decoding, one or more data bits are obtained from each frame, and encoding and decoding are performed after obtaining the data bits from multiple frames.

[0043] Buffer memory 55 is coupled to memory management circuit 51 and is used to temporarily store data. Power management circuit 56 is coupled to memory management circuit 51 and is used to control the power supply of memory storage device 10.

[0044] In one exemplary embodiment, the rewritable nonvolatile memory module 43 of FIG4 may include a flash memory module. In one exemplary embodiment, the memory control circuit unit 42 of FIG4 may include a flash memory controller. In one exemplary embodiment, the memory management circuit 51 of FIG5 may include a flash memory management circuit.

[0045] Figure 6 is a schematic diagram illustrating the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. Referring to Figure 6, the memory management circuit 51 can logically group the physical units 610(0) to 610(C) in the rewritable non-volatile memory module 43 into the storage area 601, the spare area 602, and the system area 603.

[0046] In one exemplary embodiment, an entity unit refers to an entity address or an entity programmable unit. In one exemplary embodiment, an entity unit may also consist of multiple consecutive or non-consecutive entity addresses. In one exemplary embodiment, an entity unit may also refer to a virtual block (VB). A virtual block may include multiple entity addresses or multiple entity programmable units. In one exemplary embodiment, a virtual block may include one or more entity erase units.

[0047] In one exemplary embodiment, entity units 610(0) to 610(A) in storage area 601 are used to store user data (e.g., user data from host system 11 of FIG1). For example, entity units 610(0) to 610(A) in storage area 601 may store valid data and invalid data. Entity units 610(A+1) to 610(B) in free area 602 do not store data (e.g., valid data). For example, if an entity unit does not store valid data, this entity unit may be associated (or added) to free area 602. In addition, entity units in free area 602 (or entity units that do not store valid data) may be erased. When new data is written, one or more entity units may be retrieved from free area 602 to store this new data. In one exemplary embodiment, free area 602 is also referred to as a free pool.

[0048] In one exemplary embodiment, memory management circuitry 51 may configure logic units 612(0) to 612(D) to map physical units 610(0) to 610(A) in storage area 601. In one exemplary embodiment, each logic unit corresponds to a logic address. For example, a logic address may include one or more logical block addresses (LBAs) or other logic management units. In one exemplary embodiment, a logic unit may also correspond to a logical programming unit or consist of multiple consecutive or non-consecutive logic addresses.

[0049] It should be noted that a logical unit can be mapped to one or more entity units. If an entity unit is currently mapped to a logical unit, it means that the data currently stored in this entity unit includes valid data. Conversely, if an entity unit is not currently mapped to any logical unit, it means that the data currently stored in this entity unit is invalid data.

[0050] In one exemplary embodiment, the memory management circuit 51 may record management data (also known as logic-to-entity mapping information) describing the mapping relationship between logic units and physical units in at least one logic-to-entity mapping table (L2P table). When the host system 11 wants to read data from or write data to the memory storage device 10, the memory management circuit 51 may access the rewritable non-volatile memory module 43 according to the information in this logic-to-entity mapping table.

[0051] In one exemplary embodiment, the memory management circuit 51 can store specific types of data in the system area 603. For example, physical units 610(B+1) to 610(C) in the system area 603 can be dedicated to storing high-importance data and / or data that is not intended to be accessed or modified by the host system 11. For example, the high-importance data and / or data that is not intended to be accessed or modified by the host system 11 may include a logic-to-entity mapping table, a bad block management table, a wear leveling table, a valid data management table, and / or other types of management data, which are not limited by this invention. The logic-to-entity mapping table is used to record mapping information. This mapping information can reflect the mapping relationship between logic units and physical units. The bad block management table is used to record information related to at least one bad block in the rewritable non-volatile memory module 43. The wear leveling table can be used to record information related to the wear status of at least one physical unit in the rewritable non-volatile memory module 43 (e.g., read count, write count, and / or erase count). The valid data management table can be used to record information related to the valid count of at least one physical cell in the rewritable non-volatile memory module 43.

[0052] In one exemplary embodiment, the memory management circuitry 51 may not map any logic units to physical units in the system area 603. This prevents data stored in the system area 603 from being accessed or modified by the host system 11.

[0053] Due to process variations or other factors, some physical cells are defective during manufacturing, making the data stored within them prone to errors. For example, QLC NAND flash memory modules are more likely to have such physical cells than TLC flash memory modules. If a physical cell experiences a serious data error shortly after being programmed, it is likely a defective physical cell from the manufacturing process and should be marked as a bad physical cell. In contrast, if a serious data error occurs long after programming (e.g., after a year), it may be due to durability failure, which can be resolved by reflashing the data in the physical cell. Generally, if a physical cell is found to have many error bits when reading it (which can be corrected using error correction codes), the physical cell is reflashed first. However, this approach leads to frequent reflashes when dealing with physical cells that are defective from the manufacturing process, which can degrade the performance of the entire memory storage device 10 or even render it unusable. Therefore, the following method is proposed to mark these bad physical cells earlier.

[0054] Figure 7 is a flowchart illustrating a memory management method according to one embodiment. The steps in Figure 7 are executed by the memory management circuit 51, and will not be described in detail below. Referring to Figure 7, in step 701, a timer is set after power-on. This timer corresponds to a first physical unit. In this embodiment, each physical unit has a corresponding timer. Taking the first physical unit as an example, the first physical unit may be a physical unit in storage area 601 or system area 603. For example, the timer includes a timestamp, and the memory management circuit 51 manages a clock. Subtracting the current clock from the timestamp calculates the elapsed time. In other embodiments, the timer includes a counter value, which the memory management circuit 51 increments periodically, thus representing the elapsed time.

[0055] In step 702, a reading procedure is executed on the first physical unit. In some embodiments, the reading procedure may include a hardware decoding procedure, in which a reading voltage is set, and the read bits are obtained based on whether the corresponding memory cell is turned on under this reading voltage. Next, an error correction code decoding procedure is applied to these read bits to correct the erroneous bits. If the number of erroneous bits exceeds the correction capability of the error correction code, the hardware decoding procedure fails. In some embodiments, the reading procedure may also include a software decoding procedure, in which multiple reading voltages are set, and a probability value is calculated based on whether the corresponding memory cell is turned on under these reading voltages. Next, an error correction code (e.g., LDPC) decoding procedure is applied to these probability values ​​to obtain the final read bits. If these read bits fail the error correction code check, the software decoding procedure fails. In some embodiments, the reading procedure includes both a hardware decoding procedure and a software decoding procedure; the software decoding procedure is performed when the hardware decoding procedure fails.

[0056] In step 703, it is determined whether a data error condition is met. This data error condition can have multiple states. In one state, the data error condition is met if the aforementioned hardware decoding procedure fails. In another state, the data error condition is met if the number of erroneous bits during the hardware decoding procedure exceeds a certain threshold. In yet another state, the data error condition is met if the aforementioned software decoding procedure fails. In some embodiments, when the above states occur, an error count can be accumulated, and the data error condition is only determined to be met when the error count exceeds a certain threshold. In other words, when the data error condition is met, it indicates that a serious data error has occurred in the first entity unit. If the result of step 703 is yes, then step 704 is performed; otherwise, this process ends.

[0057] In step 704, it is determined whether the elapsed time represented by the timer corresponding to the first entity unit is less than a time threshold (e.g., 5 minutes). If the result of step 704 is yes, in step 705, the first entity unit is marked as a bad entity unit, and this bad entity unit will no longer be used. If the result of step 704 is no, other procedures are performed in step 706, such as refreshing the first entity unit or not performing any processing on the first entity unit. In step 706, the first entity unit is not marked as a bad entity unit, and the first entity unit will continue to be used.

[0058] Figure 8 is a schematic diagram illustrating the operation of a timer based on a scenario. Referring to Figure 8, the horizontal axis represents time. At time point T1, when the first entity unit 810 is programmed, the timer 820 corresponding to the first entity unit 810 is reset, for example, by setting the timestamp to the current time or resetting the count value to 0. At time point T2, the first entity unit 810 executes the read procedure and meets the data error condition. The dashed line 830 represents the aforementioned time threshold, therefore the elapsed time (T2-T1) represented by timer 820 is less than the time threshold. In this example, the first entity unit 810 meets the data error condition shortly after being programmed, therefore the first entity unit 810 is marked as a bad entity unit.

[0059] Figure 9 is a schematic diagram illustrating the operation of the timer according to another scenario. Please refer to Figure 9. At time point T1, when the first physical unit 810 is programmed, the timer 820 corresponding to the first physical unit 810 is reset. However, the memory storage device 10 is then powered off, the timer 820 is not continuously updated, and the system clock stops. At time point T2, the system is powered on. At this time, the timer 820 can no longer represent how much time has passed since the first physical unit 810 was programmed. Therefore, in one embodiment, the timer 820 is also reset at power-on. At time point T3, the first physical unit 810 executes a read program and meets the data error condition. Similarly, the dashed line 830 represents the time threshold. In this example, the elapsed time (T3-T2) represented by the timer 820 is less than the time threshold, so the first physical unit 810 is also marked as a bad physical unit.

[0060] Figure 10 is a flowchart illustrating a memory management method according to an embodiment. Referring to Figure 10, in step 1001, a timer is set after power-on. In step 1002, a hardware decoding procedure is executed on the first physical unit. In step 1003, it is determined whether the hardware decoding procedure passes; if it passes, the process ends. If the hardware decoding procedure fails, a software decoding procedure is executed on the first physical unit in step 1004, and the first physical unit is refreshed. In step 1005, it is determined whether the software decoding procedure passes. If the software decoding procedure fails, cross-frame decoding is performed in step 1006. For example, single-frame decoding is used in both the hardware and software decoding procedures, meaning that the data bits used for decoding come from the same frame. However, when performing cross-frame decoding, the data bits used come from multiple different frames. In some embodiments, the data bits required for single-frame decoding are stored in the same physical unit, while the data bits required for cross-frame decoding are stored in multiple physical units, which may be distributed in the same (or different) memory planes, the same (or different) memory dies, and / or the same (or different) Chip Enabled (CE) regions. If the software decoding process is used, in step 1007, it is determined whether the elapsed time represented by the timer is less than a time threshold. If the result of step 1007 is no, the process ends. If the result of step 1007 is yes, the error count is incremented in step 1008 (e.g., by 1). In step 1009, it is determined whether the error count is greater than a count threshold. If the result of step 1009 is yes, the first physical unit is marked as a bad physical unit in step 1010. If the result of step 1009 is no, the process ends. In the example of Figure 10, the data error conditions include hardware decoding failure, successful software decoding, and the error count being greater than the count threshold.

[0061] In a variation of Figure 10, step 1007 can also be performed after step 1006. Therefore, the first entity unit may also be marked as a bad entity unit after the software decoding program fails. In such a variation, the data error condition includes the hardware decoding program failing and the number of errors exceeding a threshold.

[0062] Figure 11 is a flowchart illustrating a memory management method according to another embodiment. Referring to Figure 11, in step 1101, a timer is set after power-on. In step 1102, a hardware decoding procedure is executed on the first physical unit. Steps 1103 and 1108 are then executed in parallel. The hardware decoding procedure can detect the number of error bits. If the number of error bits is less than or equal to the upper limit of the error correction code, these error bits can be corrected. If the number of error bits is greater than the upper limit of the error correction code, for example, if verification fails in LDPC, these error bits cannot be corrected. In step 1103, it is determined whether the number of error bits is too large (greater than a number threshold). This number threshold can be greater than, equal to, or less than the upper limit of the error correction code. If the result of step 1103 is yes, in step 1104 it is determined whether the elapsed time represented by the timer is less than a time threshold. If the result of step 1104 is yes, the error count is increased in step 1105. Next, in step 1106, it is determined whether the error count is greater than a count threshold. If the result of step 1106 is yes, then in step 1107, the first entity unit is marked as a bad entity unit. On the other hand, in step 1108, it is determined whether the hardware decoding program has passed. If it has not passed, then step 1109 is performed to execute the software decoding program. In step 1110, it is determined whether the software decoding program has passed. If it has not passed, then in step 1111, cross-frame decoding is performed. In the embodiment of FIG11, the data error conditions include the number of error bits being greater than the number threshold and the number of errors being greater than the number threshold.

[0063] In some embodiments, the number of attempts thresholds used in steps 1009 and 1106 is greater than or equal to 2. This is to avoid erroneously marking available physical units as bad physical units. Referring to Figure 9, since timer 820 is reset at power-on, if a hardware decoding process fails within the time threshold, it will be marked as a bad physical unit. However, such physical units can still be used after a refresh. Therefore, the number of attempts thresholds is set to greater than or equal to 2, so that even if the hardware decoding process fails due to durability failure, there is still an additional opportunity to continue using it. Through the above means, the occurrence of erroneous marking can be reduced.

[0064] In some embodiments, the error count used in steps 1009 and 1106 is also reset (e.g., set to 0) during power-on (time point T2 in FIG9), and the error count is recalculated after power-on.

[0065] Referring to Figure 7, in some embodiments, step 703, which determines whether the data error condition is met, is based on non-RAID ECC parity information. In this embodiment, the aforementioned non-RAID ECC parity information includes information such as the hardware decoding program, the number of erroneous bits, the number of errors, and the time elapsed since programming or since power-on.

[0066] Through the aforementioned technical means, defective physical cells that exist during production can be detected and marked as bad physical cells in real time, preventing these physical cells from constantly refreshing and affecting system performance. This approach also avoids marking physical cells with durability defects as bad physical cells, thus extending the lifespan of the memory.

[0067] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0068] 10, 30: Memory storage devices 11, 31: Host System 110: System Bus 111: Processor 112: Random Access Memory 113: Read-only memory 114: Data Transfer Interface 12: Input / Output (I / O) Devices 20: Motherboard 201: USB flash drive 202: Memory Card 203: Solid State Drive 204: Wireless memory storage device 205: Global Positioning System Module 206: Network Interface Card 207: Wireless transmission device 208: Keyboard 209: Screen 210: Loudspeaker 32: SD card 33: CF card 34: Embedded storage device 341: Embedded Multimedia Card 342: Embedded multi-chip packaged storage device 41: Connection Interface Unit 42: Memory control circuit unit 43: Rewritable non-volatile memory modules 51: Memory Management Circuit 52: Host Interface 53: Memory Interface 54: Error checking and correction circuit 55: Buffer memory 56: Power Management Circuit 601: Storage Area 602: Idle Area 603: System area 610(0)~610(C): Solid unit 612(0)~612(D): Logic Unit 701~706, 1001~1010, 1101~1111: Steps 810: First Entity Unit 820: Timer 830: Dashed line T1, T2, T3: Time points

Claims

1. A memory management method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical units, and the memory management method includes: After power-on, a timer is set, wherein the timer corresponds to a first entity unit among the entity units; A read procedure is executed on the first entity unit, wherein the read procedure includes a hardware decoding procedure; when the hardware decoding procedure fails, a software decoding procedure is executed; when the software decoding procedure passes and an elapsed time represented by the timer is less than a time threshold, an error count is increased; and if the error count is greater than a one-count threshold, the first entity unit is marked as a bad entity unit.

2. The memory management method as described in claim 1 further includes: Reset the timer upon power-on.

3. The memory management method as described in claim 1 further includes: The timer is reset when the first entity unit is programmed.

4. The memory management method as described in claim 1, wherein the threshold value for the number of occurrences is greater than or equal to 2, the memory management method further includes: Reset the error count during startup.

5. A memory storage device, comprising: A connection interface unit for coupling to a host system; a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes multiple physical units; The system also includes a memory control circuit unit coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit performs multiple steps: after power-on, setting a timer corresponding to a first physical unit among the physical units; executing a read procedure on the first physical unit, wherein the read procedure includes a hardware decoding procedure; executing a software decoding procedure when the hardware decoding procedure fails; if the software decoding procedure passes and the elapsed time indicated by the timer is less than a time threshold, increasing the error count; and if the error count is greater than a one-time threshold, marking the first physical unit as a bad physical unit.

6. The memory storage device as claimed in claim 5, wherein the steps further include: Reset the timer upon power-on.

7. The memory storage device as claimed in claim 5, wherein the steps further include: The timer is reset when the first entity unit is programmed.

8. The memory storage device as claimed in claim 5, wherein the number of steps is greater than or equal to 2, and the steps further include: Reset the error count during startup.

9. A memory control circuit unit for controlling a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical units, and the memory control circuit unit includes: Host interface, used to couple to the host system; A memory interface for coupling to the rewritable non-volatile memory module; A memory management circuit, coupled to the host interface and the memory interface, performs multiple steps: after power-on, setting a timer, wherein the timer corresponds to a first physical unit among the physical units; executing a read program on the first physical unit, wherein the read program includes a hardware decoding program; executing a software decoding program when the hardware decoding program fails; when the software decoding program passes and an elapsed time indicated by the timer is less than a time threshold, increasing the error count; and if the error count is greater than a one-time threshold, marking the first physical unit as a bad physical unit.

10. The memory control circuit unit as claimed in claim 9, wherein the steps further include: Reset the timer upon power-on.

11. The memory control circuit unit as claimed in claim 9, wherein the steps further include: The timer is reset when the first entity unit is programmed.

12. The memory control circuit unit as claimed in claim 9, wherein the threshold value for the number of steps is greater than or equal to 2, further comprising: Reset the error count during startup.

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