Computing method based on a storage device, memory storage device and memory control circuit unit

Abstract

A computing method based on a storage device, a memory storage device and a memory control circuit unit are disclosed. The method includes: receiving an operation command from a host system, wherein the operation command includes header data, and the header data carries setting information related to a target logical computing; retrieving the header data from the operation command; and instructing a computing circuit inside the memory storage device to perform the target logical computing according to the header data.

Description

Technical Field

[0001] This invention relates to a memory control technology, and more particularly to a computational method based on a storage device, a memory storage device, and a memory control circuit unit. Prior Technology

[0002] The rapid growth of portable electronic devices such as mobile phones and laptops in recent years has led to a surge in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memory) are ideally suited for integration into the aforementioned portable electronic devices due to their non-volatile data, low power consumption, small size, and lack of mechanical structure.

[0003] On the other hand, with the development of computer technology, more and more data processing involves various logical operations (such as matrix operations), such as image convolution, modulo, binarization, and / or data compression. Generally, these operations are handled by the Graphics Processing Unit (GPU) or a dedicated chip in the host system, while the storage device is simply responsible for data storage. However, as the amount of data requiring logical operations becomes increasingly massive, how to effectively utilize the host system and memory storage devices to jointly complete computational tasks is one of the research topics that those skilled in the art are dedicated to studying. Summary of the Invention

[0004] This invention provides a computation method based on a storage device, a memory storage device, and a memory control circuit unit, which can improve the working efficiency between the host system and the memory storage device.

[0005] An exemplary embodiment of the present invention provides a computation method based on a storage device for use in a memory storage device. The computation method includes: receiving an operation instruction from a host system, wherein the operation instruction includes header data and the header data carries setting information related to a target logical operation; obtaining the header data from the operation instruction; and instructing the computation circuitry inside the memory storage device to perform the target logical operation based on the header data.

[0006] In an exemplary embodiment of the present invention, the setting information includes at least one of the following: enable information related to the target logical operation, type information related to the target logical operation, parameter setting information related to the target logical operation, and logical address information related to the target logical operation. The enable information is used to indicate the enablement of the target logical operation, the type information is used to indicate the type of the target logical operation, the parameter setting information is used to indicate at least one parameter used by the target logical operation, and the logical address information is used to indicate the logical address corresponding to at least a portion of the data participating in the target logical operation.

[0007] In an exemplary embodiment of the present invention, the operation instruction further includes first target data, and the step of instructing the arithmetic circuit inside the memory storage device to perform the target logical operation according to the header data includes: instructing the arithmetic circuit to perform the target logical operation on the first target data according to the header data.

[0008] In an exemplary embodiment of the present invention, the step of instructing the arithmetic circuit to perform the target logic operation on the first target data according to the header data includes: reading the second target data from the rewritable non-volatile memory module inside the memory storage device according to the header data; and instructing the arithmetic circuit to perform the target logic operation on the first target data and the second target data.

[0009] In an exemplary embodiment of the present invention, the step of instructing the arithmetic circuit inside the memory storage device to perform the target logic operation according to the header data includes: reading third target data from the rewritable non-volatile memory module inside the memory storage device according to the header data; and instructing the arithmetic circuit to perform the target logic operation on the third target data.

[0010] In an exemplary embodiment of the present invention, the calculation method further includes: in response to the operation instruction including a write instruction, storing the calculation result of the target logical operation into a rewritable non-volatile memory module inside the memory storage device; and in response to the operation instruction including a read instruction, transmitting the calculation result back to the host system.

[0011] An exemplary embodiment of the present invention provides a memory storage device, comprising a connection interface unit, a rewritable non-volatile memory module, an arithmetic circuit, and a memory control circuit unit. The connection interface unit is configured to connect to a host system. The memory control circuit unit is connected to the connection interface unit, the rewritable non-volatile memory module, and the arithmetic circuit. The memory control circuit unit is configured to: receive an operation instruction from the host system, wherein the operation instruction includes header data, and the header data carries setting information related to a target logical operation; obtain the header data from the operation instruction; and instruct the arithmetic circuit to perform the target logical operation based on the header data.

[0012] In an exemplary embodiment of the present invention, the operation instruction further includes first target data, and the operation of instructing the arithmetic circuit inside the memory storage device to perform the target logical operation according to the header data includes: instructing the arithmetic circuit to perform the target logical operation on the first target data according to the header data.

[0013] In an exemplary embodiment of the present invention, the operation of instructing the arithmetic circuit to perform the target logic operation on the first target data according to the header data includes: reading the second target data from the rewritable non-volatile memory module according to the header data; and instructing the arithmetic circuit to perform the target logic operation on the first target data and the second target data.

[0014] In an exemplary embodiment of the present invention, the operation of instructing the arithmetic circuit inside the memory storage device to perform the target logic operation according to the header data includes: reading third target data from the rewritable non-volatile memory module according to the header data; and instructing the arithmetic circuit to perform the target logic operation on the third target data.

[0015] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to: in response to the operation instruction including a write instruction, store the result of the target logic operation into a rewritable non-volatile memory module inside the memory storage device; and in response to the operation instruction including a read instruction, transmit the operation result back to the host system.

[0016] An exemplary embodiment of the present invention provides a memory control circuit unit for controlling a memory storage device, wherein the memory storage device includes a rewritable non-volatile memory module, and the memory control circuit unit includes a host interface, a memory interface, and a memory management circuit. The host interface is used to connect to a host system. The memory interface is used to connect to the rewritable non-volatile memory module. The memory management circuit is connected to both the host interface and the memory interface. The memory management circuit is used to: receive an operation instruction from the host system, wherein the operation instruction includes header data, and the header data carries setting information related to a target logical operation; obtain the header data from the operation instruction; and, based on the header data, instruct the arithmetic circuitry inside the memory storage device to perform the target logical operation.

[0017] Based on the above, after configuring the arithmetic circuitry supporting the target logic operation in the memory storage device, the host system can send operation instructions containing specially designed header data to the memory storage device to instruct it to perform the target logic operation. This improves the efficiency of cooperation between the host system and the memory storage device. Simple Explanation of the Diagram

[0018] Figure 1 is a schematic diagram of a host system, memory storage device and input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 is a schematic diagram of a host system, memory storage device and I / O device according to an exemplary embodiment of the present invention. Figure 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention. Figure 4 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention. Figure 5 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Figure 6 is a schematic diagram illustrating the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. Figure 7 is a schematic diagram illustrating the operation instructions according to an exemplary embodiment of the present invention. Figure 8 is a schematic diagram illustrating a memory storage device assisting a host system in performing target logical operations according to an exemplary embodiment of the present invention. Figure 9 is a schematic diagram illustrating a memory storage device assisting a host system in performing target logical operations according to an exemplary embodiment of the present invention. Figure 10 is a flowchart illustrating a storage device-based computation method according to an exemplary embodiment of the present invention. Implementation

[0019] Figure 1 is a schematic diagram of a host system, memory storage device, and input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 is a schematic diagram of a host system, memory storage device, and I / O device according to an exemplary embodiment of the present invention.

[0020] Referring to Figures 1 and 2, the host system 11 may include a processor 111, random access memory (RAM) 112, read-only memory (ROM) 113, and a data transfer interface 114. The processor 111, RAM 112, ROM 113, and ROM 114 may be connected to a system bus 110.

[0021] The host system 11 can be connected to the memory storage device 10 via the data transfer interface 114. For example, the host system 11 can store data in or read data from the memory storage device 10 via the data transfer interface 114. Furthermore, the host system 11 can be connected to the I / O device 12 via the system bus 110. For example, the host system 11 can transmit output signals to or receive input signals from the I / O device 12 via the system bus 110.

[0022] In one exemplary embodiment, the processor 111, random access memory 112, read-only memory 113, and data transfer interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. Through the data transfer interface 114, the motherboard 20 may be connected to the memory storage device 10 via wired or wireless means.

[0023] In one exemplary embodiment, the memory storage device 10 may be, for example, a USB flash drive 201, a memory card 202, a solid-state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a Near Field Communication (NFC) memory storage device, a WiFi wireless fax memory storage device, a Bluetooth memory storage device, or a Bluetooth Low Energy (BLE) memory storage device (e.g., iBeacon), or other memory storage devices based on various wireless communication technologies. Furthermore, the motherboard 20 may also be connected to various I / O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 via the system bus 110. For example, in one exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

[0024] In one exemplary embodiment, the host system 11 is a computer system. In one exemplary embodiment, the host system 11 may be any system that can substantially cooperate with a memory storage device to store data. In one exemplary embodiment, the memory storage device 10 and the host system 11 may respectively include the memory storage device 30 and the host system 31 of FIG3.

[0025] Figure 3 is a schematic diagram illustrating a host system and a memory storage device according to an exemplary embodiment of the present invention. Referring to Figure 3, the memory storage device 30 can be used in conjunction with the host system 31 to store data. For example, the host system 31 can be a system such as a digital camera, camcorder, communication device, audio player, video player, or tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly connect the memory module to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0026] Figure 4 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention. Referring to Figure 4, the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, a rewritable non-volatile memory module 43, and an arithmetic circuit 44.

[0027] The connection interface unit 41 is used to connect to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. For example, the interface unit 41 may be compatible with the Peripheral Component Interconnect Express (PCI Express) standard, the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards.

[0028] The memory control circuit unit 42 is connected to the connection interface unit 41, the rewritable non-volatile memory module 43, and the arithmetic circuit 44. The memory control circuit unit 42 controls the rewritable non-volatile memory module 43. For example, the memory control circuit unit 42 can instruct the rewritable non-volatile memory module 43 to perform operations such as writing, reading, and erasing data according to instructions from the host system 11. For example, the memory control circuit unit 42 may include a flash memory controller.

[0029] The rewritable non-volatile memory module 43 is used to store the data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory cell), other flash memory modules, or other memory modules with the same or similar characteristics.

[0030] The arithmetic circuit 44 is used to perform at least one logical operation. For example, the arithmetic circuit 44 can be used to perform logical operations such as image convolution, modulo, binarization, and / or data compression, and the types of logical operations that the arithmetic circuit 44 can perform are not limited to these. In addition, the arithmetic circuit 44 may include a Graphic Processing Unit (GPU), a Vision Processing Unit (VPU), a Neural Network Processing Unit (NPU), or other types of hardware circuits specifically used to perform the aforementioned logical operations.

[0031] Figure 5 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Referring to Figure 5, the memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, and a memory interface 53.

[0032] The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. For example, the memory management circuit 51 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or other similar devices or combinations thereof.

[0033] The host interface 52 is connected to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. For example, the host interface 52 may be compatible with PCI Express, SATA, PATA, IEEE 1394, USB, SD, UHS-I, UHS-II, MS, MMC, eMMC, UFS, CF, IDE, or other suitable data transfer standards. The memory interface 53 is connected to the memory management circuit 51. The memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53.

[0034] In one exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54, a buffer memory 55, and a power management circuit 56.

[0035] Error checking and correction circuit 54 is connected to memory management circuit 51 and is used to perform error checking and correction operations to ensure data integrity. Specifically, when memory management circuit 51 receives a write command from host system 11, error checking and correction circuit 54 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to the write command, and memory management circuit 51 writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code to rewritable non-volatile memory module 43. Subsequently, when memory management circuit 51 reads data from rewritable non-volatile memory module 43, it simultaneously reads the corresponding error correcting code and / or error detecting code for this data, and error checking and correction circuit 54 performs error checking and correction operations on the read data based on the error correcting code and / or error detecting code.

[0036] The buffer memory 55 is connected to the memory management circuit 51 and is used to temporarily store data. The power management circuit 56 is connected to the memory management circuit 51 and is used to control the power supply of the memory storage device 10.

[0037] Figure 6 is a schematic diagram illustrating the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. Referring to Figure 6, the memory management circuit 51 can logically group the physical units 610(0) to 610(B) in the rewritable non-volatile memory module 43 into the storage area 601 and the spare area 602.

[0038] In one exemplary embodiment, an entity unit refers to an entity address or an entity programmable unit. In one exemplary embodiment, an entity unit may also consist of multiple consecutive or non-consecutive entity addresses. In one exemplary embodiment, an entity unit may also refer to a virtual block (VB). A virtual block may include multiple entity addresses or multiple entity programmable units. In one exemplary embodiment, a virtual block may include one or more entity erase units.

[0039] In one exemplary embodiment, entity units 610(0) to 610(A) in storage area 601 are used to store user data (e.g., user data from host system 11 of FIG1). For example, entity units 610(0) to 610(A) in storage area 601 may store valid data and invalid data. Entity units 610(A+1) to 610(B) in free area 602 do not store data (e.g., valid data). For example, if an entity unit does not store valid data, this entity unit may be associated (or added) to free area 602. In addition, entity units in free area 602 (or entity units that do not store valid data) may be erased. When new data is written, one or more entity units may be retrieved from free area 602 to store this new data. In one exemplary embodiment, free area 602 is also referred to as a free pool.

[0040] In one exemplary embodiment, memory management circuitry 51 may configure logic units 612(0) to 612(C) to map physical units 610(0) to 610(A) in storage area 601. In one exemplary embodiment, each logic unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (LBAs) or other logical management units. In one exemplary embodiment, a logic unit may also correspond to a logical programming unit or consist of multiple consecutive or non-consecutive logical addresses.

[0041] In one exemplary embodiment, the memory management circuit 51 may record management data (also known as logic-to-entity mapping information) describing the mapping relationship between logic units and physical units in at least one logic-to-entity mapping table. When the host system 11 wants to read data from or write data to the memory storage device 10, the memory management circuit 51 may access the rewritable non-volatile memory module 43 according to the information in this logic-to-entity mapping table.

[0042] In one exemplary embodiment, the host system 11 may send at least one instruction (also referred to as an operation instruction) to the memory storage device 10. The memory management circuitry 51 may receive this operation instruction from the host system 11. In particular, this operation instruction may include specially designed header data. This header data may contain setting information related to a specific logical operation (also referred to as a target logical operation). For example, the target logical operation may be a logical operation supported by the arithmetic circuitry 44, such as convolution, modulo, binarization, and / or data compression, and the type of target logical operation is not limited to this.

[0043] Upon receiving this operation instruction, the memory management circuit 51 can obtain the header data from it. Then, the memory management circuit 51 can instruct the arithmetic circuit 44 to perform the target logic operation based on the header data. For example, the memory management circuit 51 can configure the arithmetic circuit 44 and instruct it to perform the target logic operation based on the configuration information carried in the header data.

[0044] Figure 7 is a schematic diagram illustrating operation instructions according to an exemplary embodiment of the present invention. Referring to Figure 7, in an exemplary embodiment, the memory management circuit 51 can receive operation instructions 710 from the host system 11. The operation instructions 710 may include header data 711 and user data 712. The header data 711 may carry setting information related to the target logical operation. For example, the header data 711 may include header description data 713 and header parameter data 714. The header description data 713 may carry data length information related to the header parameter data 714. This data length information may reflect the data length of the header parameter data 714. The header parameter data 714 is used to carry setting information related to the target logical operation. In addition, the user data 712 includes at least a portion of the data to be involved in the target logical operation (also referred to as first target data).

[0045] In one exemplary embodiment, the configuration information may include at least one of the following: enable information related to the target logical operation, type information related to the target logical operation, parameter setting information related to the target logical operation, and logical address information related to the target logical operation. The enable information indicates the enabling of the target logical operation. For example, memory management circuit 51 may enable (e.g., enable) the arithmetic circuit 44 based on this enable information. The type information indicates the type of the target logical operation. For example, memory management circuit 51 may configure the arithmetic circuit 44 based on this type information to control the arithmetic circuit 44 to perform a specific type of target logical operation. The parameter setting information indicates at least one parameter used in the target logical operation. For example, memory management circuit 51 may configure the arithmetic circuit 44 to use at least one parameter when performing the target logical operation based on this parameter setting information. The logical address information indicates the logical address corresponding to at least a portion of the data participating in the target logical operation. For example, memory management circuit 51 may read at least a portion of the data to participate in the target logical operation from the rewritable non-volatile memory module 43 based on this logical address information. For example, this logical address information may reflect at least one logical address. The memory management circuit 51 may, based on this logical address information, instruct the rewritable nonvolatile memory module 43 to read at least a portion of the data (also referred to as second target data or third target data) to participate in the target logical operation from the physical address mapped by the at least one logical address.

[0046] In one exemplary embodiment, the data size (or data length) of user data 712 is greater than zero. For example, when the data size (or data length) of user data 712 is greater than zero, the operation instruction 710 can be considered to include user data 712. In one exemplary embodiment, the data size (or data length) of user data 712 may be zero. For example, when the data size (or data length) of user data 712 is zero, the operation instruction 710 can be considered to not include user data 712. Furthermore, the operation instruction 710 may also include a write instruction or a read instruction. A write instruction is used to instruct the memory storage device 10 to perform a data write operation. A read instruction is used to instruct the memory storage device 10 to perform a data read operation.

[0047] In one exemplary embodiment, assume that operation instruction 710 includes user data 712. According to operation instruction 710, memory management circuit 51 can instruct arithmetic circuit 44 to perform a target logic operation on the first target data carried by user data 712. For example, after receiving operation instruction 710, memory management circuit 51 can configure arithmetic circuit 44 according to header data 711. Then, memory management circuit 51 can input the first target data carried by user data 712 into arithmetic circuit 44. Arithmetic circuit 44 can then perform a target logic operation based on the first target data.

[0048] In one exemplary embodiment, according to operation instruction 710, memory management circuit 51 can also read second target data from rewritable non-volatile memory module 43. Then, memory management circuit 51 can instruct arithmetic circuit 44 to perform target logic operations on the first target data and the second target data read from rewritable non-volatile memory module 43. For example, memory management circuit 51 can instruct rewritable non-volatile memory module 43 to read the second target data from a specific physical address based on logical address information in header data 711 (or header parameter data 714). After completing the setup of arithmetic circuit 44, memory management circuit 51 can input the first target data carried by user data 712 and the second target data read from rewritable non-volatile memory module 43 to arithmetic circuit 44. Arithmetic circuit 44 can then perform target logic operations based on the first target data and the second target data.

[0049] In one exemplary embodiment, it is assumed that operation instruction 710 does not contain user data 712. According to operation instruction 710, memory management circuit 51 can read third target data from rewritable non-volatile memory module 43. Then, memory management circuit 51 can instruct arithmetic circuit 44 to perform target logical operations on this third target data. For example, memory management circuit 51 can instruct rewritable non-volatile memory module 43 to read third target data from a specific physical address based on logical address information in header data 711 (or header parameter data 714). After completing the setup of arithmetic circuit 44, memory management circuit 51 can input the third target data read from rewritable non-volatile memory module 43 to arithmetic circuit 44. Arithmetic circuit 44 can then perform target logical operations based on the third target data.

[0050] In one exemplary embodiment, the memory management circuit 51 can determine whether the operation instruction (e.g., operation instruction 710 in FIG. 7) includes a write instruction or a read instruction. In response to the operation instruction including a write instruction, the memory management circuit 51 can store the result of the target logic operation into the rewritable non-volatile memory module 43. Subsequently, the memory management circuit 51 can read this operation result from the rewritable non-volatile memory module 43. Alternatively, in response to the operation instruction including a read instruction, the memory management circuit 51 can send this operation result back to the host system 11.

[0051] Figure 8 is a schematic diagram illustrating a memory storage device assisting a host system in performing target logical operations according to an exemplary embodiment of the present invention. Referring to Figure 8, in an exemplary embodiment, the memory management circuit 51 can receive an operation instruction 810 from the host system 11. The operation instruction 810 includes header data 811 and data 812 (i.e., user data or first target data). In addition, the operation instruction 810 includes a write instruction instructing the execution of a data write operation.

[0052] According to operation instruction 810, memory management circuit 51 can activate and configure arithmetic circuit 44. For example, according to the enable information in operation instruction 810, memory management circuit 51 can activate arithmetic circuit 44. According to the type information in operation instruction 810, memory management circuit 51 can configure arithmetic circuit 44 to perform matrix modular arithmetic (i.e., target logic operation). Furthermore, according to the logical address information in operation instruction 810, memory management circuit 51 can read data 820 (i.e., second target data) from rewritable non-volatile memory module 43. Then, memory management circuit 51 can input data 812 and 820 to arithmetic circuit 44. Arithmetic circuit 44 can perform matrix modular arithmetic (i.e., target logic operation) on data 812 and 820 and generate data 830. Data 830 reflects the result of the target logic operation. After generating data 830, in response to the write instruction in operation instruction 810, memory management circuit 51 can store data 830 into rewritable non-volatile memory module 43 for later use.

[0053] Figure 9 is a schematic diagram illustrating a memory storage device assisting a host system in performing a target logical operation according to an exemplary embodiment of the present invention. Referring to Figure 9, in an exemplary embodiment, the memory management circuit 51 can receive an operation instruction 910 from the host system 11. The operation instruction 910 includes header data 911. In addition, the operation instruction 910 includes a write instruction instructing the execution of a data write operation and a read instruction following the write instruction.

[0054] According to operation instruction 910, memory management circuit 51 can activate and configure arithmetic circuit 44. For example, according to the activation information in operation instruction 910, memory management circuit 51 can activate arithmetic circuit 44. According to the type information in operation instruction 910, memory management circuit 51 can configure arithmetic circuit 44 to perform matrix binarization operations (i.e., target logic operations). According to the parameter setting information in operation instruction 910, memory management circuit 51 can set the maximum, minimum, and critical values ​​used in this binarization operation to "10", "0", and "5", respectively. That is, in this binarization operation, if a parameter value is greater than the critical value (i.e., "5"), the parameter value will be adjusted to the set maximum value (i.e., "10"); however, if a parameter value is less than the critical value (i.e., "5"), the parameter value will be adjusted to the set minimum value (i.e., "0"). Furthermore, based on the logical address information in the operation instruction 910, the memory management circuit 51 can read data 920 (i.e., the third target data) from the rewritable non-volatile memory module 43. Then, the memory management circuit 51 can input the data 920 to the arithmetic circuit 44. The arithmetic circuit 44 can perform a binarization operation (i.e., a target logical operation) on the data 920 and generate data 930. Data 930 reflects the result of the target logical operation.

[0055] After data 930 is generated, in response to the read instruction in operation instruction 910, memory management circuit 51 can send data 930 back to host system 11. It should be noted that in the foregoing exemplary embodiments, the header data in the operation instruction may also include other useful information, depending on practical needs, and the present invention does not impose any limitations.

[0056] In one exemplary embodiment, the aforementioned operation mode, which further incorporates additional computational operations performed by the memory storage device 10 during data reading and / or writing, is also known as Compute-Intensive Read / Write (CIRW) mode. This mode is typically used in scenarios where complex computational tasks need to be performed in computer systems and / or storage systems, such as data analysis, machine learning, and image processing. This mode has the following advantages: during data reading or writing, not only is data transmitted, but complex computational processing is also performed; data processing is integrated into the storage system, reducing data transmission overhead; real-time processing can be performed simultaneously with data reading or writing, improving processing efficiency; and by performing computation in the storage system, the dependence on the central processing unit (CPU) and network bandwidth is reduced. Furthermore, in the following exemplary embodiments, operations performed by the host system 11 can be considered as operations performed by the processor 111 of FIG. 1.

[0057] In one exemplary embodiment, the host system 11 may perform preprocessing operations on an image (also referred to as a target image) to generate feature data corresponding to the target image. This feature data may reflect image features related to the target image.

[0058] In one exemplary embodiment, the host system 11 may send the operation instruction to the memory storage device 10 based on the feature data. The operation instruction may instruct the memory storage device 10 to store the feature data in a rewritable non-volatile memory module 43, read the feature data from the rewritable non-volatile memory module 43, and / or perform logical operations (i.e., target logical operations) on the feature data.

[0059] In one exemplary embodiment, the host system 11 may use this image feature to train an artificial intelligence model. For example, the artificial intelligence model may include a Convolutional Neural Network (CNN) model, an autoencoder model, a Feature Pyramid Networks (FPNs) model, a Transformer model, or a Capsule Networks model. A Convolutional Neural Network is a deep learning model specifically designed to process data with a grid structure, such as images.

[0060] Autoencoder models can be used for dimensionality reduction and feature extraction. After training an autoencoder model to encode key features of an image, the decoder part can be discarded, retaining only the encoder as a feature extractor. This is an unsupervised learning method, primarily used in feature learning, data dimensionality reduction, and generative models. An autoencoder consists of an input layer, hidden layers, and an output layer, and its goal is to learn the intrinsic representation of the data by reconstructing the input data.

[0061] Feature pyramid network models can capture features at different scales, making them very useful for tasks such as object detection. Pre-extracting multi-scale features can accelerate the training speed of subsequent models. Transformer models were originally designed for natural language processing, but they also perform well in visual tasks. They can learn global contextual information from key regions of an image. Therefore, they have been widely used in computer vision and other fields. Capsule network models attempt to capture the part-whole hierarchical structure of objects, which is very useful for recognizing objects and their poses in images.

[0062] Capsule networks are an architecture designed to improve the performance of traditional convolutional neural networks (CNNs) in image recognition tasks, particularly excelling in addressing problems such as object pose estimation and translation invariance. The main characteristic of capsule networks is their use of so-called capsule units instead of traditional neurons. These capsule units capture not only the basic features of an object but also its pose information (such as orientation and size). Each capsule is actually a vector that can represent multiple attributes of the feature, not just a single scalar activation value. Through dynamic routing algorithms, capsule networks can better handle changes in the position and shape of objects in an image. It should be noted that the artificial intelligence model described may also include other types of models, and this invention is not limited thereto.

[0063] In one exemplary embodiment, the host system 11 may employ a metadata indexing strategy to store key features (i.e., the feature data) of the target image along with the complete target image. In one exemplary embodiment, the host system 11 may create an index file. This index file may record information such as the storage location and size of each key feature of the target image. Subsequently, the host system 11 may query this index file to retrieve each key feature (i.e., the feature data) of the target image.

[0064] In one exemplary embodiment, during the preprocessing operation, the host system 11 can segment the target image into multiple parts (such as a grid) and create a separate file for each part. Subsequently, the file corresponding to each part can be loaded and used independently, thereby improving operational flexibility.

[0065] In one exemplary embodiment, the host system 11 may create corresponding metadata for the target image and each segmented portion. The metadata includes identification information of the target image, location information of each portion of the target image (e.g., grid position), file names or storage locations corresponding to each portion of the target image, or category labels, and other information (also known as attribute data) that helps to identify and / or classify the segments from the target image.

[0066] In one exemplary embodiment, the host system 11 may record the metadata in the index file. Furthermore, the host system 11 may store the target image and its segments in the memory storage device 10.

[0067] In one exemplary embodiment, the target image may be stored in the memory storage device 10 based on a certain storage mode (also referred to as the first storage mode), while the segments segmented from the target image may be stored in the memory storage device 10 based on another storage mode (also referred to as the second storage mode). For example, the first storage mode may include a three-level memory cell (TLC) or a four-level memory cell (QLC) mode, while the second storage mode may include a single-level memory cell (SLC) mode. Furthermore, the first and second storage modes may be adjusted according to practical needs, and the present invention is not limited thereto.

[0068] In one exemplary embodiment, the host system 11 may query the index file to obtain metadata corresponding to a specific portion segmented from the target image. Then, the host system 11 may generate an operation instruction with specific header data based on the obtained metadata. Subsequently, in the aforementioned Read-Write Attached Computation (CIRW) mode, the host system 11 may access the memory storage device 10 via this operation instruction. Specifically, during access to the memory storage device 10 via this operation instruction, the host system 11 may instruct the memory storage device 10 to perform target logical operations on the specific portion segmented from the target image using the header data carried by the operation instruction. Related operational details can be found in the descriptions of the foregoing exemplary embodiments (e.g., Figures 8 and 9), and will not be repeated here.

[0069] In one exemplary embodiment, the artificial intelligence model does not need to access the complete image data for training. Instead, it can be trained by extracting key information from the image (i.e., segmenting specific parts from the target image), thereby improving training efficiency. In other words, by pre-processing (e.g., segmenting) the image data during the storage phase, the time required to load the entire image during training can be reduced. This approach not only simplifies the data preparation process for model training but also significantly reduces the demand for computational resources.

[0070] In one exemplary embodiment, in the metadata indexing strategy, the host system 11 can select a suitable database to store metadata based on data access patterns and data volume. For example, the host system 11 can select a suitable database from relational databases, NoSQL databases, or other types of databases based on the content of the metadata to be stored, the complexity of the created index, and / or the type of artificial intelligence model used, and use the selected database to store the metadata. In particular, a reasonable metadata storage and retrieval design can greatly improve the efficiency of model training and make the storage system more flexible and powerful.

[0071] Figure 10 is a flowchart illustrating a storage device-based computation method according to an exemplary embodiment of the present invention. Referring to Figure 10, in step S1001, an operation instruction is received from the host system, wherein the operation instruction includes header data, and the header data carries setting information related to the target logical operation. In step S1002, the header data is obtained from the operation instruction. In step S1003, based on the header data, the computation circuitry inside the memory storage device is instructed to perform the target logical operation.

[0072] However, since each step in Figure 10 has been described in detail above, it will not be repeated here. It is worth noting that each step in Figure 10 can be implemented as multiple pieces of code or circuits, and this invention is not limited thereto. Furthermore, the method in Figure 10 can be used in conjunction with the above exemplary embodiments, or it can be used alone, and this invention is not limited thereto.

[0073] In summary, the storage-based computation method, memory storage device, and memory control circuit unit proposed in this invention can configure the computation circuit supporting the target logic operation within the memory storage device. Subsequently, the host system can send operation instructions containing specially designed header data to the memory storage device to instruct it to perform the target logic operation. This improves the collaborative efficiency between the host system and the memory storage device.

[0074] On the other hand, the storage device-based computation method, memory storage device, and memory control circuit unit proposed in this invention can simultaneously complete logical operations on data during the process of the host system writing or reading data from the storage device. Therefore, the storage device-based computation method, memory storage device, and memory control circuit unit proposed in this invention can provide at least one of the following advantages:

[0075] 1. Reduce the hardware specifications and / or setup costs of host systems (such as computer terminal systems). For example, the host system may not require additional and / or specialized chips.

[0076] 2. The computational task is offloaded by the storage device. Whether using a dedicated chip or a central processing unit (CPU) for matrix calculations, some data always needs to be retrieved from the storage device before computation. However, with this invention, the calculated result is retrieved directly, reducing the computational burden on other computing units.

[0077] 3. Improve overall system efficiency. Traditionally, host systems often calculate and store data, or retrieve data, perform calculations, and then use it. This process wastes time in two places: first, waiting for data to be read or written; and second, processing and calculating data in memory. While waiting for data, processes can be suspended, and the CPU can handle other tasks, but data calculation still occupies the CPU. However, with this invention, the time for data calculation can be incorporated into the time spent waiting for data transmission.

[0078] 4. Reduce system complexity. For some small systems, such as dashcams and recording devices, there is a need for data compression and simple calculations. Using this invention, the integration of these small systems can be further improved, thereby simplifying the system, reducing costs, and improving stability.

[0079] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0080] 10, 30: Memory storage devices 11, 31: Host System 110: System Bus 111: Processor 112: Random Access Memory 113: Read-only memory 114: Data Transfer Interface 12: Input / Output (I / O) Devices 20: Motherboard 201: USB flash drive 202: Memory Card 203: Solid State Drive 204: Wireless memory storage device 205: Global Positioning System Module 206: Network Interface Card 207: Wireless transmission device 208: Keyboard 209: Screen 210: Loudspeaker 32: SD card 33: CF card 34: Embedded storage device 341: Embedded Multimedia Card 342: Embedded multi-chip packaged storage device 41: Connection Interface Unit 42: Memory control circuit unit 43: Rewritable non-volatile memory modules 44: Operational Circuit 51: Memory Management Circuit 52: Host Interface 53: Memory Interface 54: Error checking and correction circuit 55: Buffer memory 56: Power Management Circuit 601: Storage Area 602: Idle Area 610(0)~610(B): Solid unit 612(0)~612(C): Logic Unit 710, 810, 910: Operation instructions 711, 811, 911: Header data 712: User Data 713: Header Description 714: Header Parameter Data 812, 820, 813, 920, 930: Data S1001~S1003: Steps

Claims

1. A computation method based on a storage device, used in a memory storage device, the computation method comprising: The system receives an operation instruction, wherein the operation instruction includes header data and the header data contains setting information related to a target logical operation, wherein the setting information includes at least one of the following: enable information related to the target logical operation, type information related to the target logical operation, parameter setting information related to the target logical operation, and logical address information related to the target logical operation. The enable information is used to indicate the enable of the target logical operation, the type information is used to indicate the type of the target logical operation, the parameter setting information is used to indicate at least one parameter used by the target logical operation, and the logical address information is used to indicate the logical address corresponding to at least a portion of the data participating in the target logical operation. The system retrieves the header data from the operation instruction and, based on the header data, instructs the arithmetic circuitry inside the memory storage device to execute the target logical operation.

2. The operation method as described in claim 1, wherein the operation instruction further includes first target data, and the step of instructing the arithmetic circuit inside the memory storage device to perform the target logical operation according to the header data includes: Based on the header data, the arithmetic circuit is instructed to perform the target logic operation on the first target data.

3. The operation method as described in claim 2, wherein the step of instructing the operation circuit to perform the target logic operation on the first target data according to the header data includes: Based on the header data, the second target data is read from the rewritable non-volatile memory module inside the memory storage device; And instruct the computing circuit to perform the target logic operation on the first target data and the second target data.

4. The operation method as described in claim 1, wherein the step of instructing the arithmetic circuitry inside the memory storage device to perform the target logical operation based on the header data includes: Based on the header data, third target data is read from the rewritable non-volatile memory module inside the memory storage device; And instruct the computing circuit to perform the target logic operation on the third target data.

5. The calculation method as described in claim 1 further includes: In response to the operation instruction including a write instruction, the result of the target logical operation is stored in a rewritable non-volatile memory module inside the memory storage device; and in response to the operation instruction including a read instruction, the result is sent back to the host system.

6. A memory storage device, comprising: A connection interface unit for connecting to the host system; Rewritable non-volatile memory modules; Operational circuits; The system also includes a memory control circuit unit connected to the connection interface unit, the rewritable non-volatile memory module, and the arithmetic circuit. The memory control circuit unit is configured to: receive an operation instruction from the host system, wherein the operation instruction includes header data and the header data contains setting information related to a target logical operation. The setting information includes at least one of the following: enable information related to the target logical operation, type information related to the target logical operation, parameter setting information related to the target logical operation, and logical address information related to the target logical operation. The enable information indicates the enable of the target logical operation, the type information indicates the type of the target logical operation, the parameter setting information indicates at least one parameter used by the target logical operation, and the logical address information indicates the logical address corresponding to at least a portion of the data participating in the target logical operation; obtain the header data from the operation instruction; and instruct the arithmetic circuit to execute the target logical operation based on the header data.

7. The memory storage device as claimed in claim 6, wherein the operation instructions further include first target data, and the operation of instructing the arithmetic circuitry within the memory storage device to perform the target logical operation based on the header data includes: Based on the header data, the arithmetic circuit is instructed to perform the target logic operation on the first target data.

8. The memory storage device as claimed in claim 7, wherein instructing the arithmetic circuit to perform the target logic operation on the first target data according to the header data includes: Based on the header data, read the second target data from the rewritable non-volatile memory module; And instruct the computing circuit to perform the target logic operation on the first target data and the second target data.

9. The memory storage device as claimed in claim 6, wherein instructing the arithmetic circuitry within the memory storage device to perform the target logical operation based on the header data includes: Based on the header data, third target data is read from the rewritable non-volatile memory module; And instruct the computing circuit to perform the target logic operation on the third target data.

10. The memory storage device as claimed in claim 6, wherein the memory control circuit unit is further configured to: store the result of the target logic operation into a rewritable non-volatile memory module inside the memory storage device in response to the operation instruction including a write instruction; and transmit the operation result back to the host system in response to the operation instruction including a read instruction.

11. A memory control circuit unit for controlling a memory storage device, wherein the memory storage device includes a rewritable non-volatile memory module, and the memory control circuit unit includes: The host interface is used to connect to the host system; A memory interface for connecting to the rewritable non-volatile memory module; The system also includes a memory management circuit connected to the host interface and the memory interface. The memory management circuit is configured to: receive an operation instruction from the host system, wherein the operation instruction includes header data and the header data contains setting information related to a target logical operation. The setting information includes at least one of the following: enable information related to the target logical operation, type information related to the target logical operation, parameter setting information related to the target logical operation, and logical address information related to the target logical operation. The enable information indicates the enable of the target logical operation, the type information indicates the type of the target logical operation, the parameter setting information indicates at least one parameter used by the target logical operation, and the logical address information indicates the logical address corresponding to at least a portion of the data participating in the target logical operation; obtain the header data from the operation instruction; and, based on the header data, instruct the arithmetic circuitry within the memory storage device to execute the target logical operation.

12. The memory control circuit unit as claimed in claim 11, wherein the operation instruction further includes first target data, and the operation of instructing the arithmetic circuit inside the memory storage device to perform the target logical operation according to the header data includes: Based on the header data, the arithmetic circuit is instructed to perform the target logic operation on the first target data.

13. The memory control circuit unit as claimed in claim 12, wherein instructing the arithmetic circuit to perform the target logic operation on the first target data according to the header data includes: Based on the header data, read the second target data from the rewritable non-volatile memory module; And instruct the computing circuit to perform the target logic operation on the first target data and the second target data.

14. The memory control circuit unit as claimed in claim 11, wherein instructing the arithmetic circuitry within the memory storage device to perform the target logical operation based on the header data includes: Based on the header data, third target data is read from the rewritable non-volatile memory module; And instruct the computing circuit to perform the target logic operation on the third target data.

15. The memory control circuit unit of claim 11, wherein the memory management circuit is further configured to: in response to the operation instruction including a write instruction, store the result of the target logic operation into a rewritable non-volatile memory module inside the memory storage device; and in response to the operation instruction including a read instruction, transmit the result of the operation back to the host system.

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