Dynamic addressing system for data transmission
Patent Information
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- ANPEC ELECTRONICS CORPORATION
- Filing Date
- 2025-01-08
- Publication Date
- 2026-07-16
AI Technical Summary
Traditional SPI addressing methods require significant time and computational resources due to the need for high-performance computing, especially when addressing a large number of interconnected devices, leading to inefficient and costly data transmission.
A dynamic addressing system where slave devices modulate clock signals and set individual addresses based on clock and data signal levels, reducing the data processing load on both slave and master devices.
The system efficiently addresses multiple slave devices with reduced data processing, lowering the need for high-performance computing capabilities and reducing circuit costs.
Smart Images
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Abstract
Description
Technical Field
[0001] This invention relates to data transmission, and in particular to a dynamic addressing system for data transmission. Prior Technology
[0002] SPI (Serial Peripheral Interface) is a synchronous serial communication interface consisting of 4 pins. Its features include high-speed, full-duplex data transmission. This architecture consists of multiple devices, one of which acts as the master device and the others as slave devices.
[0003] However, the traditional addressing method for multiple devices using SPI involves the master device sending instructions containing multiple data points, with multiple slave devices sequentially receiving specific data as the basis for judgment, and using the results of internal counters to determine their own position. This traditional addressing method requires the number of bits sent and transmitted to be determined based on the number of devices connected in series, thus the transmission time is directly proportional to the number of devices. When using the traditional addressing method to address a large number of interconnected devices, the amount of data that the master device and multiple slave devices need to process and compute is too large, resulting in a significant time consumption to complete the addressing of all slave devices. This leads to poor addressing efficiency and requires multiple devices with high-performance computing capabilities, significantly increasing circuit costs. Summary of the Invention
[0004] To address the shortcomings of traditional technologies, this invention provides a dynamic addressing system for data transmission. The dynamic addressing system of this invention includes multiple slave devices and a master control device. The multiple slave devices are sequentially connected in series. The master control device is connected to a first of the multiple slave devices. The master control device is configured to send a clock signal and a data signal to the first of the multiple slave devices. The first of the multiple slave devices is configured to modulate multiple levels of the clock signal received from the master control device, and output the data signal and the modulated clock signal to the next slave device. Each of the multiple slave devices, except for the first and last ones, is configured to modulate multiple levels of the clock signal received from the previous slave device, and output the modulated clock signal and the data signal received from the previous slave device to the next slave device. Each of the slave devices is configured to set its own individual device address based on the multiple levels of the received clock signal and the multiple bit values of the data signal.
[0005] As described above, this invention provides a dynamic addressing system for data transmission. Compared to traditional addressing methods, the addressing method employed in this invention's dynamic addressing system effectively reduces the amount of data processed by multiple slave devices and the master control device. Even without employing multiple slave devices and the master control device with high-performance computing capabilities to reduce costs, this invention's dynamic addressing system can still accurately and quickly address multiple slave devices.
[0006] To further understand the features and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are for reference and illustration only and are not intended to limit the present invention. Simple Explanation of the Diagram
[0007] Figure 1 is a block diagram of the data transmission dynamic addressing system according to the first embodiment of the present invention.
[0008] Figure 2 is a waveform diagram of the signal of the first of a plurality of slave devices in the data transmission dynamic addressing system of the first embodiment of the present invention.
[0009] Figure 3 is a waveform diagram of the signals of multiple slave devices in the data transmission dynamic addressing system of the first embodiment of the present invention.
[0010] Figure 4 is a block diagram of the data transmission dynamic addressing system according to the second embodiment of the present invention.
[0011] Figure 5 is a waveform diagram of the signals of multiple slave devices in the data transmission dynamic addressing system of the second embodiment of the present invention. Implementation
[0012] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of the present invention. In addition, the accompanying drawings of the present invention are only simple illustrations and are not depictions of actual dimensions, as stated in advance. The following embodiments will further describe the relevant technical content of the present invention in detail, and the disclosed content is not intended to limit the scope of protection of the present invention. In addition, the term "or" used herein should be interpreted to include any or more combinations of the associated listed items, depending on the actual situation.
[0013] Please refer to Figure 1, which is a block diagram of the data transmission dynamic addressing system according to the first embodiment of the present invention.
[0014] The data transmission dynamic addressing system of the present invention includes multiple slave devices SL1 and a master control device MA1 as shown in FIG1.
[0015] Multiple slave devices SL1~SLn are connected in series in sequence. The master control device MA1 is connected to the input terminal of the slave device SL1, which is the first in the sequence. The master control device MA1 can also be connected to the output terminal of the slave device SLn, which is the last in the sequence. The input terminal of each of the slave devices SL1~SLn except the first one is connected to the output terminal of the previous one.
[0016] For example, the master control device MA1 has a data output terminal MOSI, a clock output terminal SCLO, a clock input terminal SCLI, and a data output terminal MISO, and each of the multiple slave devices SL1~SLn has a data input terminal SDI, a clock input terminal SCLI, a data output terminal SDO, and a clock output terminal SCLO.
[0017] The data output terminal MOSI of the master control device MA1 is connected to the data input terminal SDI of the slave device SL1, which is the first slave device in the sequence of multiple slave devices SL1~SLn.
[0018] Among multiple slave devices SL1~SLn, except for the slave device SLn which is the first in the sequence, the data output terminal SDO of each of the others is connected to the data input terminal SDI of the next slave device. That is, the data output terminal SDO of the slave device SL1 which is the first in the sequence is connected to the data input terminal SDI of the slave device SL2 which is the next / second in the sequence.
[0019] The data output terminal SDO of the slave device SLn, which is the most senior among the multiple slave devices SL1~SLn, can be connected to the data output terminal MISO of the master device MA1.
[0020] The clock output terminal SCLO of the master control device MA1 is connected to the clock input terminal SCLI of the slave device SL1, which is the first in the sequence of multiple slave devices SL1~SLn.
[0021] Among multiple slave devices SL1~SLn, except for the slave device SLn which is the first in the sequence, the clock output terminal SCLO of each of the others is connected to the clock input terminal SCLI of the next slave device SL2. That is, the clock output terminal SCLO of the first slave device SL1~SLn is connected to the clock input terminal SCLI of the slave device SL2 which is the next / second slave device SL1~SLn.
[0022] The clock output terminal SCLO of the slave device SLn, which is the most senior among the multiple slave devices SL1~SLn, can be connected to the clock input terminal SCLI of the master control device MA1.
[0023] The master control device MA1 generates a data signal SDA1, which has multiple bit values, including multiple bit values "0" and "1". The master control device MA1 sends the data signal SDA1, which is transmitted through a data output terminal MOSI of the master control device MA1 to a data input terminal SDI of the slave device SL1, which is the first slave device in the sequence of the slave devices SL1~SLn.
[0024] The master control device MA1 generates a clock signal CLK1. This clock signal CLK1 has multiple levels, including multiple low (logic) levels "0" and multiple high (logic) levels "1". The master control device MA1 sends the clock signal CLK1, which is transmitted through its clock output terminal SCLO to the clock input terminal SCLI of the first-ordered slave device SL1~SLn.
[0025] It is worth noting that among the multiple slave devices SL1~SLn, the first slave device SL1 modulates multiple levels of the clock signal CLK1 received from the master control device MA1, and then uses the modulated clock signal CLK1 as the clock signal CLK2, and outputs it through a clock output terminal SCLO of the slave device SL1 to a clock input terminal SCLI of the next slave device SL2.
[0026] Among the multiple slave devices SL1~SLn, except for the first and last ones, the multiple slave devices SL2~SLn-1 modulate multiple levels of the clock signals CLK2~CLKn-1 received from the previous one, so as to output the modulated clock signals CLK3~CLKn to the next slave device SL3~SLn respectively.
[0027] Among multiple slave devices SL1~SLn, the last slave device SLn can modulate the clock signal CLKn received from the previous slave device SLn-1 and output the modulated clock signal CLKn+1 to the master control device MA1. Alternatively, in practice, the slave device SLn does not modulate the clock signal CLKn and directly outputs the clock signal CLKn to the master control device MA1.
[0028] For example, multiple slave devices SL1~SLn respectively invert multiple levels of the received clock signals CLK1~CLKn, such as inverting from a low level to a high level or from a high level to a low level, to modulate the clock signals CLK1~CLKn respectively.
[0029] On the other hand, among the multiple slave devices SL1~SLn, the slave device SL1, which is ranked first, can output a data signal SDA2 to the slave device SL2, which is ranked next, based on a data signal SDA1 received from the master control device MA1.
[0030] Among the multiple slave devices SL1~SLn, except for the first and last ones, the slave devices SL2~SLn-1 can output multiple data signals SDA3~SDAn to the next slave device SL3~SLn according to the data signals SDA2~SDAn-1 received from the previous one.
[0031] Multiple bit values of data signal SDA2 can be the same as multiple bit values of data signal SDA1. However, each of the multiple slave devices SL1~SLn receives multiple data signals SDA1~SDAn, and it takes time to extract multiple bit values from each of the multiple data signals SDA1~SDAn, which may result in a delay in the output of multiple data signals SDA2~SDAn+1. As a result, as shown in Figure 3, each of the multiple data signals SDA1~SDA1n has a phase difference / time difference with the previous one.
[0032] For example, as shown in Figures 2 and 3, each of the multiple data signals SDA1 to SDA1n may contain multiple waveforms. These multiple waveforms at multiple time points may each have multiple (logic or voltage) levels that represent multiple bit values. For example, each high logic level of the multiple waveforms represents a bit value "1", while each low logic level of the multiple waveforms represents a bit value "0".
[0033] Multiple slave devices SL1~SLn set their own individual device addresses based on multiple levels of the received clock signals CLK1~CLKn and multiple bit values of the data signals SDA1~SDAn. That is, slave device SL1 sets its own individual device address based on multiple levels of the clock signal CLK1 and multiple bit values of the data signal SDA1n. Slave device SL2 sets its own individual device address based on multiple levels of the clock signal CLK2 and multiple bit values of the data signal SDA2n.
[0034] If needed, in addition to multiple clock signals CLK1~CLKn and multiple data signals SDA1~SDAn, multiple slave devices SL1~SLn can generate or store multiple read signals READY1~READYn respectively.
[0035] Multiple slave devices SL1~SLn set their own individual device address based on multiple levels of the received clock signals CLK1~CLKn, multiple bit values of the data signals SDA1~SDAn, and multiple levels of the read signals READY1~READYn generated or stored by themselves. That is, slave device SL1 sets its own individual device address based on multiple levels of the clock signal CLK1, multiple bit values of the data signal SDA1n, and multiple levels of the read signal READY1. Slave device SL2 sets its own individual device address based on multiple levels of the clock signal CLK2, multiple bit values of the data signal SDA2n, and the read signal READY2.
[0036] Please refer to Figures 1 to 3, which are block diagrams of the data transmission dynamic addressing system of the first embodiment of the present invention. Figure 2 is a waveform diagram of the signal of the first among the multiple slave devices of the data transmission dynamic addressing system of the first embodiment of the present invention. Figure 3 is a waveform diagram of the signal of the multiple slave devices of the data transmission dynamic addressing system of the first embodiment of the present invention.
[0037] The number of slave devices SL1~SLn connected in series can be determined according to actual needs, and the present invention is not limited thereto. For ease of explanation, only slave devices SL1~SL4 are shown in Figure 3, and will be described in the following text as slave devices SL1~SL4. The other slave devices SL5~SLn are described in the same way.
[0038] Each of the multiple slave devices SL1~SLn aligns the multiple levels of the read signals READY1~READYn that it generates or stores with the multiple levels of the received clock signals CLK1~CLKn respectively, and aligns the multiple levels of the received clock signals CLK1~CLKn with the multiple bit values of the received data signals SDA1~SDAn respectively.
[0039] Multiple slave devices SL1~SLn address their own individual device address based on a combination of each of the multiple levels of the read signals READY1~READYn, the level of the clock signals CLK1~CLKn, and the bit values of the data signals SDA1~SDAn.
[0040] Specifically, as shown in Figures 3 and 4, the slave device SL1 aligns the multiple levels of the received read signal READY1 with the multiple levels of the received clock signal CLK1 according to the order of the multiple occurrence times of the multiple waveforms of the read signal READY1 and the sorting of the multiple levels.
[0041] The slave device SL1 aligns the multiple levels of the received clock signal CLK1 with the multiple bit values of the received data signal SDA1 based on the order of multiple occurrence times, multiple levels, and multiple bit values of multiple waveforms of the clock signal CLK1 and the data signal SDA1.
[0042] As shown in Figures 2 and 3, when the slave device SL1 determines that any one of the multiple levels of the read signal READY1 is the same as the first reference level (e.g., a high voltage level or a first logic level "1") and the level of the clock signal CLK1 it is aligned with is the same as an initial reference level (e.g., a low voltage level or an initial logic level "0"), the slave device SL1 adds an initial preset value, such as "0", to an address count value ID1 from an initial count value, such as "1", thus counting this address count value ID1. At this time, as indicated by the index arrow E1 pointing to the address count value ID1 in Figure 3, the counted address count value ID1 remains unchanged and is still "1".
[0043] Next, when slave device SL1 determines that any of the multiple levels of clock signal CLK1 is transitioning from an initial reference level (e.g., a low voltage level or an initial logic level "0") to a first reference level (e.g., a high voltage level or a first logic level "1") and the level of the data signal SDA1 it is aligned with is the same as the first reference level, slave device SL1 sets the current address count value "1" as its own device address. That is, among the multiple slave devices SL1~SLn, the slave device SL1 that is first in sequence sets its own device address to "1".
[0044] It should be understood that when the clock signal CLK1 transitions from a low level to a high level, a rising edge is generated in the waveform of the clock signal CLK1. In practice, the rising edge of the waveform of the clock signal CLK1 described in this article can be replaced with the falling edge of the waveform of the clock signal CLK1. When the clock signal CLK1 transitions from a high level to a low level, a falling edge is generated in the waveform of the clock signal CLK1.
[0045] After setting its own individual device address "1", slave device SL1 can change its latch signal LATCH1 from an initial latch signal to a preset latch signal. For example, the initial latch signal has a low voltage level or an initial logic level "0", while the preset latch signal has a high voltage level or a first logic level "1".
[0046] When the latch signal LATCH1 of slave device SL1 is the same as an initial latch signal, it means that slave device SL1 has not yet set its own device address. Conversely, when the latch signal LATCH1 of slave device SL1 is the same as a preset latch signal, it means that slave device SL1 has completed setting its own device address. At this time, as shown by the indicator arrow E4 in Figure 3, it points to the address count value ID1 at which slave device SL1 stops counting, and is aligned with the latch signal LATCH1 that transitions from the initial logic level "0" to the first logic level "1".
[0047] It is worth noting that the slave device SL1 inverts multiple levels of the received clock signal CLK1 to form a clock signal CLK2. As shown in Figure 3, each of the multiple levels of the clock signal CLK1 is opposite to the level aligned with in the multiple levels of the clock signal CLK2. That is, when any level of the clock signal CLK1 is the first logic level "1", the level aligned with in the clock signal CLK2 is an initial logic level "0". Conversely, when any level of the clock signal CLK1 is an initial logic level "0", the level aligned with in the clock signal CLK2 is the first logic level "1".
[0048] It should be understood that, as shown in Figure 3, the time difference / phase difference between clock signal CLK2 and clock signal CLK1 is the delay time caused by the slave device SL1 receiving clock signal CLK1, generating clock signal CLK2, and transmitting clock signal CLK2, etc., while performing other operations.
[0049] After slave device SL1 outputs clock signal CLK2 and data signal SDA2 to the next slave device SL2 in sequence, slave device SL2 begins addressing, as detailed below.
[0050] As shown in Figure 4, the slave device SL2 aligns the multiple levels of the received read signal READY2 with the multiple levels of the received clock signal CLK2 according to the order of the multiple occurrence times of the multiple waveforms of the read signal READY2 and the sorting of the multiple levels.
[0051] The slave device SL2 aligns the multiple levels of the received clock signal CLK2 with the multiple bit values of the received data signal SDA2 based on the sequence of multiple occurrence times, multiple levels, and multiple bit values of multiple waveforms of the clock signal CLK2 and the data signal SDA2.
[0052] When the slave device SL2 determines that any one of the multiple levels of the read signal READY2 is the same as the first reference level (e.g., a high voltage level or the first logic level "1") and the level of the clock signal CLK2 is the same as the first reference level, the slave device SL2 will add a first preset value, such as a high voltage level or the first logic level "1", to an initial count value, such as "1". As shown by the index arrow E2 pointing to the address count value ID2 in Figure 3, the currently counted address count value ID2 is "2".
[0053] Next, when slave device SL2 determines that any of the multiple levels of clock signal CLK2 is transitioning from an initial reference level (e.g., a low voltage level or an initial logic level "0") to a first reference level (e.g., a high voltage level or a first logic level "1") and the level of the data signal SDA2 it is aligned with is the same as the first reference level, slave device SL1 sets the current address count value "2" as its own device address. As indicated by the arrow E4 pointing to the address count value ID2 in Figure 3, slave device SL2, which is the second slave device in the sequence of multiple slave devices SL1~SLn, sets its own device address to "2".
[0054] After setting its own individual device address "2", slave device SL2 can change its latch signal LATCH2 from an initial latch signal to a preset latch signal. For example, as shown by the indicator arrow E4 in Figure 3, the latch signal LATCH2 can be changed from a low voltage level or an initial logic level "0" (the level of the initial latch signal) to a high voltage level or a first logic level "1" (the level of the preset latch signal).
[0055] When the latch signal LATCH2 of slave device SL2 is the same as an initial latch signal, it means that slave device SL2 has not yet set its own device address. Conversely, when the latch signal LATCH2 of slave device SL2 is the same as a preset latch signal, it means that slave device SL2 has completed setting its own device address, and therefore slave device SL2 will not count up by one address value.
[0056] It is worth noting that the slave device SL2 inverts multiple levels of the received clock signal CLK2 to form a clock signal CLK3. As shown in Figure 3, each of the multiple levels of the clock signal CLK2 is opposite to the corresponding level of the multiple levels of the clock signal CLK3. That is, when the level of the clock signal CLK2 is the first logic level "1", the level of the clock signal CLK3 is a low voltage level or an initial logic level "0". Conversely, when the level of the clock signal CLK2 is an initial logic level "0", the level of the clock signal CLK3 is the first logic level "1".
[0057] After slave device SL2 addresses its own device address or outputs clock signal CLK3 and data signal SDA3 to the next slave device SL3 in sequence, slave device SL3 begins addressing, as detailed below.
[0058] As shown in Figure 4, the slave device SL3 aligns the multiple levels of the received read signal READY3 with the multiple levels of the received clock signal CLK3 according to the order of the multiple occurrence times of the multiple waveforms of the read signal READY3 and the sorting of the multiple levels.
[0059] The slave device SL3 aligns the multiple levels of the received clock signal CLK3 with the multiple bit values of the received data signal SDA3 based on the sequence of multiple occurrence times, multiple levels, and multiple bit values of multiple waveforms of the clock signal CLK3 and the data signal SDA3.
[0060] When the slave device SL3 determines that any one of the multiple levels of the read signal READY3 is the same as the first reference level (e.g., a high voltage level or a first logic level "1") and the level of the clock signal CLK3 is the same as an initial reference level (e.g., a low voltage level or an initial logic level "0"), the slave device SL3 will add an initial preset value, such as "0", to an initial count value, such as "1" ID1, in order to count this address count value ID3. As indicated by the arrow E1 pointing to the address count value ID3 in Figure 3, the counted address count value ID3 remains unchanged at this time and is still "1".
[0061] Next, when any of the multiple levels of the pulse signal CLK3 is transitioning from an initial reference level (e.g., a low voltage level or an initial logic level "0") to a first reference level (e.g., a high voltage level or a first logic level "1"), and the level of the data signal SDA3 being aligned to is the same as the initial reference level, the slave device SL3 adds a second preset value, such as "2", to an address count value "1". As indicated by the arrow E3 pointing to the address count value ID3 in Figure 3, the address count value ID3 at this time is "3".
[0062] Next, when slave device SL3 determines that any of the multiple levels of clock signal CLK3 is transitioning from an initial reference level (e.g., a low voltage level or an initial logic level "0") to a first reference level (e.g., a high voltage level or a first logic level "1") and the level of the data signal SDA3 it is aligned with is the same as the first reference level, slave device SL3 sets the current address count value "3" as its own individual device address. As indicated by the arrow E4 pointing to the address count value ID3 in Figure 3, slave device SL3, which is the third among the multiple slave devices SL1~SLn, sets its own individual device address to "3".
[0063] After setting its own individual device address "3", slave device SL3 can change its latch signal LATCH3 from an initial latch signal to a preset latch signal. For example, the initial latch signal has a low voltage level or an initial logic level "0", while the preset latch signal has a high voltage level or a first logic level "1".
[0064] When the latch signal LATCH3 of slave device SL3 is the same as an initial latch signal, it means that slave device SL3 has not yet set its own device address. Conversely, when the latch signal LATCH3 of slave device SL3 is the same as a preset latch signal, it means that slave device SL3 has completed setting its own device address. At this time, as indicated by the arrow E4 pointing to the address count value ID3 in Figure 3, slave device SL3 stops counting one address count value.
[0065] It is worth noting that the slave device SL3 inverts multiple levels of the received clock signal CLK3 to form a clock signal CLK4.
[0066] After slave device SL3 addresses its own device address or outputs clock signal CLK4 and data signal SDA4 to the next slave device SL4 in sequence, slave device SL4 begins addressing, as detailed below.
[0067] As shown in Figure 4, the slave device SL4 aligns the multiple levels of the received read signal READY4 with the multiple levels of the received clock signal CLK4 according to the order of the multiple occurrence times of the multiple waveforms of the read signal READY4 and the sorting of the multiple levels.
[0068] The slave device SL4 aligns the multiple levels of the received clock signal CLK4 with the multiple bit values of the received data signal SDA4 based on the sequence of multiple occurrence times, multiple levels, and multiple bit values of multiple waveforms of the clock signal CLK4 and the data signal SDA4.
[0069] When the slave device SL4 determines that any one of the multiple levels of the read signal READY4 is the same as the first reference level (e.g., a high voltage level or the first logic level "1") and the level of the clock signal CLK4 is the same as the first reference level, the slave device SL4 will add a first preset value, such as a high voltage level or the first logic level "1", to an initial count value, such as "1", to count this address count value ID4. As indicated by the arrow E2 pointing to the address count value ID4 in Figure 3, the counted address count value ID4 is "2" at this time.
[0070] Next, when any of the multiple levels of the pulse signal CLK4 is transitioning from an initial reference level (e.g., a low voltage level or an initial logic level "0") to a first reference level (e.g., a high voltage level or a first logic level "1"), and the level of the data signal SDA4 being aligned to is the same as the initial reference level, the slave device SL4 adds a second preset value, such as "2", to an address count value "2". As indicated by the arrow E3 pointing to the address count value ID4 in Figure 3, the address count value ID3 being counted at this time is "4".
[0071] Next, when the slave device SL4 determines that any of the multiple levels of the clock signal CLK4 is transitioning from an initial reference level (e.g., a low voltage level or an initial logic level "0") to a first reference level (e.g., a high voltage level or a first logic level "1") and the level of the data signal SDA2 it is aligned with is the same as the first reference level, the slave device SL4 sets the current address count value "4" as its own individual device address. As indicated by the arrow E4 pointing to the address count value ID4 in Figure 3, the slave device SL4, which is the fourth among the multiple slave devices SL1~SLn, sets its own individual device address to "4".
[0072] The above description only applies to four of the multiple slave devices SL1 to SLn: SL1 to SL4. The other slave devices SL5 to SLn perform the same or similar operations.
[0073] It is worth noting that traditional data addressing systems, in order to sequentially address multiple serially connected slave devices, output a clock signal and transmit it sequentially to each slave device. Each device receives a clock signal with the same number of levels / pulses as the other devices. Due to the operating time of the multiple slave devices, there is a phase difference / phase delay between the clock signal received by each device and the clock signal received by the previous device. If a large number of slave devices are serially connected, the sequential addressing of these devices by a traditional data addressing system results in a significant phase delay between the clock signal received by the master device from the last slave device and the one sent from the first slave device. This phase delay requires padding with logic level "0" and bit value "0". Consequently, when the master device compares the sent and received clock signals to analyze the number of slave devices, the master device in a traditional data addressing system processes a large amount of data, leading to poor addressing efficiency.
[0074] In contrast, the data transmission dynamic addressing system of the present invention includes multiple slave devices SL1~SLn that invert the multiple clock signals CLK1~CLKn received respectively. As shown in FIG3, slave device SL1 inverts the level of the clock signal CLK1 from the master control device MA1 to output clock signal CLK2. The clock signal CLK2 received by slave device SL2, which is the next slave device SL1, has the opposite level to the clock signal CLK1. Next, slave device SL2 inverts the level of the clock signal CLK2 from slave device SL1 to output clock signal CLK3. The clock signal CLK3 received by slave device SL3, which is the next slave device SL2, has the opposite level to the clock signal CLK2. Next, slave device SL3 inverts the level of the clock signal CLK3 from slave device SL2 to output clock signal CLK4. The clock signal CLK4 received by slave device SL4, which is the next slave device in the sequence, is opposite to the level of clock signal CLK3.
[0075] As a result, the dynamic addressing system for data transmission of the present invention can effectively reduce the phase delay between the clock signal CLKn+1 (or in practice, the clock signal CLKn) received by the master control device MA1 from the last slave device SLn among the multiple slave devices SL1~SLn, and the clock signal CLKn sent by the master control device to the first slave device SL1 among the multiple slave devices SL1~SLn. Therefore, when the master control device MA1 of the dynamic addressing system for data transmission of the present invention compares the sent clock signal CLK1 with the received clock signal CLKn+1 (or in practice, the clock signal CLKn) to analyze the number of multiple slave devices SL1~SLn, the amount of data processed by the master control device MA1 of the dynamic addressing system for data transmission of the present invention is small. Therefore, even without high-performance computing capabilities, it can efficiently address based on this data.
[0076] Please refer to Figures 4 and 5, where Figure 4 is a block diagram of the data transmission dynamic addressing system of the second embodiment of the present invention, and Figure 5 is a waveform diagram of the signals of multiple slave devices of the data transmission dynamic addressing system of the second embodiment of the present invention.
[0077] The second embodiment of the present invention is the same as the first embodiment, and will not be repeated herein. The differences between the second embodiment and the first embodiment of the present invention are described in detail below.
[0078] As shown in Figure 1, in the first embodiment, multiple slave devices SL1~SLn generate or store multiple read signals READY1~READYn respectively. In contrast, in the second embodiment, as shown in Figure 4, the multiple slave devices SL1~SLn do not generate / store read signals READY1~READYn. Instead, the master control device MA1 sends a master control signal MAS1, and the multiple slave devices SL1~SLn sequentially transmit the master control signal MAS1~MASn.
[0079] As shown in Figure 4, in the second embodiment, the main control device MA1, in addition to having a data output terminal MOSI, a clock output terminal SCLO, a clock input terminal SCLI, and a data output terminal MISO, also has a main control output terminal xCS.
[0080] Each of the multiple slave devices SL1~SLn has a data input terminal SDI, a clock input terminal SCLI, a data output terminal SDO, and a clock output terminal SCLO, as well as a master control input terminal xCSI.
[0081] The master control device MA1 outputs a master control signal MAS1 to a master control input terminal xCSI of the slave device SL1. Based on the received master control signal MAS1, the slave device SL1 outputs a master control signal MAS2 to a master control input terminal xCSI of the next slave device SL2 in the sequence. Multiple slave devices SL3~SLn perform the same operation described above.
[0082] As shown in Figure 5, when each slave device SL1~SLn determines that any one of the multiple levels of the received master control signal MAS1~MASn is the same as an initial reference level (e.g., a low voltage level or an initial logic level "0") and the level of the clock signal CLK1 is the same as an initial reference level (e.g., a low voltage level or an initial logic level "0"), the multiple slave devices SL1~SLn add an initial preset value (e.g., "0") to an address count value from an initial count value (e.g., "1"). As indicated by the index arrow E1 pointing to the address count values ID1 and ID3 in Figure 5, adding an initial preset value (e.g., "0") to an address count value "1" yields a counted address count value "1".
[0083] Furthermore, when each slave device SL1~SLn determines that any of the multiple levels of the received master control signal MAS1~MASn is the same as an initial reference level (e.g., a low voltage level or an initial logic level "0") and the level of the clock signal CLK1 is the same as the first reference level, the multiple slave devices SL1~SLn add a first preset value, such as "1", to an address count value. As indicated by the index arrow E2 pointing to the address count values ID2 and ID4 in Figure 5, adding the first preset value, such as "1", to an address count value "2" after counting is obtained.
[0084] In summary, this invention provides a dynamic addressing system for data transmission. Compared to traditional addressing methods, the addressing method employed in this invention's dynamic addressing system effectively reduces the amount of data processed by multiple slave devices and the master control device. Even without employing multiple slave devices and the master control device with high-performance computing capabilities to reduce costs, this invention's dynamic addressing system can still accurately and quickly address multiple slave devices.
[0085] The content disclosed above is only a preferred and feasible embodiment of the present invention, and is not intended to limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made using the contents of the present invention specification and drawings are included in the scope of the patent application of the present invention.
[0086] MA1: Main control unit MOSI: Data Output Terminal SCLO: Clock Output Terminal SCLI: Clock Input MISO: Data Output Terminal SL1~SLn: Slave devices SDI: Data Input Terminal SCLI: Clock Input SDO: Data Output Terminal SCLO: Clock Output Terminal SDA1~SDAn+1: Data Signals CLK1~CLKn+1: Clock signal READY1~READYn: Read signals ID1~ID4: Address count values E1~E4: Indicator Arrows LATCH1~LATCH4: Latch signals MAS1~MASn: Master control signals xCS: Main control output terminal xCSI: Main control input terminal MAS1~MASn: Master control signals
Claims
1. A dynamic addressing system for data transmission, comprising: a plurality of slave devices sequentially connected in series; and a master control device connected to a first of the plurality of slave devices, configured to send a clock signal and a data signal to the first of the plurality of slave devices; wherein the first of the plurality of slave devices is configured to modulate a plurality of levels of the clock signal received from the master control device, and output the data signal and the modulated clock signal to the next slave device; wherein each of the plurality of slave devices, except for the first and last, is configured to modulate the plurality of levels of the clock signal received from the previous slave device, and output the modulated clock signal and the data signal received from the previous slave device to the next slave device; wherein each slave device is configured to set its own individual device address based on the plurality of levels of the received clock signal and a plurality of bit values of the data signal.
2. The data transmission dynamic addressing system as claimed in claim 1, wherein each of the plurality of slave devices, except for the last one, is configured to invert a plurality of the levels of the received clock signal to modulate the clock signal.
3. The data transmission dynamic addressing system as described in claim 1, wherein the last of the plurality of slave devices is connected to the master device and configured to directly output the received clock signal to the master device, or to invert the plurality of levels of the received clock signal and output the inverted clock signal to the master device.
4. The data transmission dynamic addressing system as claimed in claim 1, wherein each of the slave devices is configured to generate a read signal, aligning a plurality of levels of the read signal to a plurality of levels of the clock signal and to a plurality of bit values of the data signal; wherein each of the slave devices is configured to address its own individual device address based on a combination of each of the plurality of levels of the read signal, the aligned level of the clock signal, and the bit value of the data signal.
5. The data transmission dynamic addressing system as described in claim 4, wherein, When any one of the multiple levels of the read signal is the same as a first reference level and the level of the clock signal being aligned is the same as an initial reference level, each of the slave devices is configured to add an initial preset value to an address count value.
6. The data transmission dynamic addressing system as described in claim 5, wherein, When any one of the multiple levels of the read signal is the same as the first reference level and the level of the clock signal being aligned is the same as the first reference level, each of the slave devices is configured to add a first preset value to the address count value.
7. The data transmission dynamic addressing system as described in claim 6, wherein, When any of the multiple levels of the clock signal is transitioning from the initial reference level to the first reference level and the level of the data signal being aligned is the same as the initial reference level, each of the slave devices is configured to add a second preset value to the address count value.
8. The data transmission dynamic addressing system as described in claim 7, wherein, When any of the multiple levels of the clock signal is transitioning from the initial reference level to the first reference level and the level of the data signal being aligned to is the same as the first reference level, each slave device is configured to set the current address count value as its own individual device address.
9. The data transmission dynamic addressing system as claimed in claim 8, wherein each of the slave devices is configured to, after setting its own individual device address, change its own latch signal from an initial latch signal to a preset latch signal.
10. The data transmission dynamic addressing system of claim 1, wherein the master control device outputs a master control signal sequentially transmitted to a plurality of the slave devices; wherein each of the slave devices is configured to align a plurality of levels of the master control signal with a plurality of levels of the clock signal and with a plurality of bit values of the data signal; wherein each of the slave devices is configured to address its own individual device address based on a combination of each of the plurality of levels of the master control signal, the aligned level of the clock signal, and the bit value of the data signal.
11. The data transmission dynamic addressing system as described in claim 10, wherein, When any one of the multiple levels of the master control signal is the same as an initial reference level and the level of the clock signal being aligned is the same as the initial reference level, each slave device is configured to add an initial preset value to an address count value.
12. The data transmission dynamic addressing system as described in claim 11, wherein, When any one of the multiple levels of the master control signal is the same as the initial reference level and the level of the clock signal being aligned is the same as a first reference level, each of the slave devices is configured to add a first preset value to the address count value.
13. The data transmission dynamic addressing system as described in claim 12, wherein, When any of the multiple levels of the clock signal is transitioning from the initial reference level to the first reference level and the level of the data signal being aligned is the same as the initial reference level, each of the slave devices is configured to add a second preset value to the address count value.
14. The data transmission dynamic addressing system as described in claim 13, wherein, When any of the multiple levels of the clock signal is transitioning from the initial reference level to the first reference level and the level of the data signal being aligned to is the same as the first reference level, each slave device is configured to set the current address count value as its own individual device address.