Burst access memory and method of operating a burst access memory

Abstract

The present disclosure relates to a burst access memory comprising a memory array comprising a plurality of memory macros, each memory macro comprising an array of memory cells arranged in rows and columns, wherein the memory cells in each column are connected by at least one local bit line, said array of memory cells and the local bit lines defining the memory macro; a plurality of global bit lines and bit line switches, wherein each global bit line is connectable to several corresponding local bit lines of the memory macros; a controller configured to schedule a burst access of the burst access memory by generating a plurality of macro accesses to the memory macros, wherein the plurality of macro accesses are scheduled to start with a predefined delay in relation to each other, wherein each macro access is divided into a plurality of ordered sub-operations, and wherein consecutive macro accesses are directed to different memory macros and different columns, wherein data for consecutive macro accesses are arranged in the different memory macros and the different columns to match the consecutive macro accesses. The disclosure further relates to a method of operating a burst access memory.

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