System-on-a-chip and method of manufacturing the same
Segmented silicon interposers with single-chip support and strategic bonding reduce thermal warpage, enhancing assembly and yield in semiconductor manufacturing.
TW202630400APending Publication Date: 2026-07-16SAMSUNG ELECTRONICS CO LTD
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Patent Information
- Application Number
- TW114143823
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-05-21
- Filing Date
- 2025-11-11
- Publication Date
- 2026-07-16
AI Technical Summary
Technical Problem
Existing intermediates in semiconductor manufacturing suffer from significant warpage due to differing coefficients of thermal expansion (CTE) between grains, leading to assembly difficulties and lower manufacturing yields.
Method used
The use of segmented silicon interposers, where each interposer supports a single computer chip, connected via microbumps and C4 bumps, with optional epoxy molding compound removal, to reduce thermal warpage.
Benefits of technology
This configuration significantly reduces warpage at high temperatures, improving assembly and yield by maintaining chip integrity and eliminating the need for additional epoxy layers.
✦ Generated by Eureka AI based on patent content.
Abstract
A system-on-a-chip (SoC) includes segmented interposers and computer chips, such as high-bandwidth memory (HBM) devices. One computer chip is on each segmented interposer. The SoC also includes second interposers connecting the segmented interposers together. At least some of the second interposers extend across a gap between adjacent segmented interposers. The SoC also includes an organic substrate coupled to each of the segmented interposers.
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