Memory with serialized redundancy interface

TW202630407APending Publication Date: 2026-07-16QUALCOMM INC
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Patent Information

Authority / Receiving Office
TW · TW
Patent Type
Applications
Current Assignee / Owner
QUALCOMM INC
Filing Date
2025-11-26
Publication Date
2026-07-16

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Abstract

A memory is provided having a plurality of banks. A shared redundancy address decoder decodes a redundancy address for each of the banks to provide a decoded redundancy address to each bank. Should one of the banks have a defect, the bank repairs the defect by reconfiguring its resources responsive to its decoded redundancy address.
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