Repair system for system on a chip

Abstract

A system on a chip includes a plurality of tiles, a non-volatile memory, and a repair system. The repair system includes a cache and control logic. The control logic is configured to receive a repair data write request and a respective repair address and corresponding repair data for a respective tile of the plurality of tiles from a respective repair controller and store the corresponding repair data in the cache in a redundancy encoded and compressed format; write the contents of the cache to the non-volatile memory; and receive a repair data read request and the respective repair address for the respective tile from the respective repair controller, read the corresponding redundancy encoded and compressed repair data from the cache, decompress the repair data, decode the corresponding repair data with error detection and correction logic, and output the corresponding repair data to the respective repair controller.

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