Flip-flop

Abstract

A flip-flop is disclosed. The flip-flop includes a master latch and a slave latch, and the master latch may include a first circuit configured to generate, based on a data input, a first data signal complementary to the data input and a second circuit configured to generate, based on a clock input and the first data signal, a second data signal complementary to the first data signal and a clock signal complementary to the clock input, and the slave latch may be configured to receive the clock signal through a first node and to generate a data output by latching a third data signal complementary to the second data signal based on the clock input, the second data signal, and the clock signal, and the second circuit may be configured to float the first node based on the first data signal and the third data signal.

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