Memory device and manufacturing method thereof
TW202630730APending Publication Date: 2026-07-16NAN YA TECH
Patent Information
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- NAN YA TECH
- Filing Date
- 2025-07-04
- Publication Date
- 2026-07-16
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Figure TWG2TA001068362_001 
Figure TWG2TA001068362_002 
Figure TWG2TA001068362_003
Abstract
A manufacturing method of a capacitor includes forming a dielectric layer stack over a substrate, forming an opening through the dielectric layer stack, forming a bottom electrode layer lining the opening, forming a protective layer sealing the opening, in which forming the protective layer includes performing a first deposition process to form a first dielectric layer by using a nitrogen plasma, and performing a second deposition process to form a second dielectric layer by using an oxygen plasma, removing a portion of the protective layer until the top surface of the dielectric layer stack is exposed, and the other portion of the protective layer remains in place, forming a high-k dielectric layer along a sidewall of the bottom electrode layer and a sidewall of the protective layer, and forming a top electrode layer along a sidewall of the high-k dielectric layer.
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