Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes a substrate structure, a well region, an emitter contact region, a collector contact region, an isolation doped region, trenches and a gate structure. A top epitaxial layer of the substrate structure includes a first region and a second region having different doped concentrations. The well region and the isolation doped region are located outside the first region and have a first conductivity type. The top epitaxial layer has a second conductivity type. The emitter contact region is disposed on the well region. The collector contact region is disposed in the first region. The emitter contact region and the collector contact region have opposite conductivity types. The isolation doped region is located between the well region and the collector contact region. The trenches are disposed in the substrate structure and extend from the emitter contact region to the isolation doped region. The gate structure fills the trenches. The distance between the collector contact region and the gate structure is greater than the distance between the emitter contact region and the gate structure.

Description

Technical Field

[0001] This invention relates to semiconductor devices, and more particularly to semiconductor devices comprising trench gates and three-dimensional (3D) channel structures. Prior Technology

[0002] The semiconductor industry continues to improve the integration density of various electronic components by continuously reducing the minimum component size, allowing more components to be integrated within a given area. For example, complementary metal-oxide semiconductor (CMOS) field-effect transistors (FETs) are the most basic and widely used components in integrated circuit manufacturing, offering advantages such as low power consumption, ease of manufacturing, and small size. In high-voltage power integrated circuits, laterally diffused metal-oxide semiconductor (LDMOS) FETs are often used to meet requirements such as high voltage resistance and power control. Furthermore, LDMOS devices are easily compatible with the manufacturing processes of CMOS devices.

[0003] However, conventional laterally diffused metal-oxide-semiconductor (LMDS) and complementary metal-oxide-semiconductor (CMDS) devices typically employ a planar gate structure located on the top surface of the semiconductor substrate. This makes it impossible for conventional laterally diffused LMDS and CDS devices to fully meet requirements in terms of turn-on resistance, forward current, and channel mobility. Summary of the Invention

[0004] Some embodiments of the present invention provide a semiconductor device. The semiconductor device includes a substrate structure, a well region, an emitter contact region, a collector contact region, an isolation doped region, a plurality of trenches, and a gate. The substrate structure includes a top epitaxial layer. The top epitaxial layer includes a first region and a second region. The well region is located outside the first region of the top epitaxial layer. The well region has a first conductivity type, and the top epitaxial layer has a second conductivity type. The emitter contact region is disposed on the well region. The collector contact region is disposed in the first region of the top epitaxial layer. The emitter contact region and the collector contact region have opposite conductivity types. The isolation doped region is disposed outside the first region of the top epitaxial layer and between the well region and the collector contact region, and the isolation doped region has a first conductivity type. A plurality of trenches are disposed in the substrate structure. The trenches extend from the emitter contact region to the isolation doped region along a first direction, and a plurality of bottom surfaces of the trenches are higher than a bottom surface of the emitter contact region and a bottom surface of the isolation doped region. A gate is disposed on the substrate and fills the trenches. The distance between the collector contact region and the gate is greater than the distance between the emitter contact region and the gate. The first and second regions of the top epitaxial layer have different doping concentrations. Simple Explanation of the Diagram

[0005] The viewpoints of embodiments of the invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the elements may be arbitrarily enlarged or reduced to clearly demonstrate the features of embodiments of the invention. Figure 1 is a schematic cross-sectional view of a semiconductor device according to some embodiments disclosed herein. Figure 2 is a partial perspective view of the semiconductor device of some embodiments disclosed in Figure 1. Figure 3 is a cross-sectional view along tangent BB and tangent B'-B' in Figure 2. Figures 4, 5, 6, 7, 8A, 9A, and 10A are schematic cross-sectional views of intermediate stages forming some embodiments of the semiconductor device shown in Figure 1 of this disclosure. Figures 8B, 9B, and 10B are perspective views of intermediate stages forming the channel regions of the semiconductor devices of some embodiments of the present disclosure shown in Figure 1. Implementation

[0006] The present disclosure is described more fully below with reference to the accompanying drawings of embodiments of the invention. However, the present disclosure may be implemented in various different ways and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings may be enlarged for clarity, and the same or similar reference numerals in the drawings denote the same or similar elements. It is understood that additional steps may be provided before, during, and after the method, and some described steps may be replaced or omitted for other embodiments of the method.

[0007] Various embodiments or examples are provided below for implementing different elements of the provided semiconductor structure. When the description refers to a first component being formed on top of a second component, it may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components, so that the first and second components are not in direct contact. Furthermore, the embodiments of the invention may use repeated component symbols in many examples. These repetitions are for simplification and clarity only and do not represent a specific relationship between the various embodiments and / or configurations discussed.

[0008] Furthermore, spatially related terms such as "below," "under," "below," "above," "above," and other similar expressions may be used in the following description to simplify the statement of the relationship between an element or component and other elements or components as shown in the figure. These spatially related terms include not only the orientation depicted in the figure but also the different orientations of the device during use or operation. The device may be positioned in other orientations (rotated 90 degrees or in other orientations), and the spatially related descriptions used herein may be interpreted accordingly.

[0009] This disclosure relates to a semiconductor device including trench gates and a three-dimensional (3D) channel structure, and a method for manufacturing the same. Multiple trenches are formed within the substrate of the semiconductor device, and gates are located on the substrate and fill these trenches, thereby creating a three-dimensional channel structure between the trench gates to increase the channel width. Furthermore, the channel mobility can be increased by modifying the sidewall crystal planes of the three-dimensional channel structure, thereby improving the on-resistance and forward current of the semiconductor device. Moreover, the drift region of the semiconductor device can have multiple regions, and the drift region resistance can be further reduced by adjusting the doping concentration of these regions. The semiconductor device disclosed herein is applicable to lateral insulated-gate bipolar transistor (LIGBT) devices.

[0010] Figure 1 is a schematic cross-sectional view of a semiconductor device 500 according to some embodiments disclosed herein. In some embodiments, the semiconductor device 500 may be a lateral insulated gate bipolar transistor (LIGBT). In some embodiments, the semiconductor device 500 may include a substrate structure 210, a well region 207, an emitter contact region 209, a collector contact region 213, an isolation doped region 215, a plurality of trenches 232, and a gate 219.

[0011] In some embodiments, the substrate structure 210 may include a bottom layer 201, a first epitaxial layer 202, and a second epitaxial layer 203L stacked sequentially from bottom to top. In some embodiments, the bottom layer 201 may be doped with a dopant to have a second conductivity type. When the second conductivity type is N-type, the dopant having the second conductivity type may include phosphorus (P), arsenic (As), antimony (Sb), or other suitable dopant. Furthermore, the doping concentration of the bottom layer 201 is approximately 10¹⁹-10²¹ atoms / cm³, and can be considered as an N-type heavily doped semiconductor substrate.

[0012] A first epitaxial layer 202 is disposed on a base layer 201. In some embodiments, the first epitaxial layer 202 may be doped with a dopant to have a first conductivity type opposite to the second conductivity type. The dopant having the first conductivity type may include aluminum (Al), boron (B), boron difluoride (BF₂), or other suitable dopant. For example, when the base layer 201 is an N-type base layer 201, the first epitaxial layer 202 is a P-type epitaxial layer 202. Furthermore, the doping concentration of the first epitaxial layer 202 is approximately 10¹⁷-10¹⁸ atoms / cm³.

[0013] A second epitaxial layer 203L is disposed and stacked on the first epitaxial layer 202. In some embodiments, the second epitaxial layer 203L may be doped with a dopant to have a second conductivity type. For example, when the bottom layer 201 is an N-type bottom layer 201, the second epitaxial layer 203L is an N-type epitaxial layer 203L. Furthermore, the doping concentration of the second epitaxial layer 203L (e.g., about 10¹⁵-10¹⁶ atoms / cm³) is less than the doping concentration of the bottom layer 201 (e.g., about 10¹⁹-10²¹ atoms / cm³). For example, when the bottom layer 201 is an N-type heavily doped (N+) bottom layer 201, the second epitaxial layer 203L is an N-type lightly doped (N-) epitaxial layer 203L. In applications of lateral insulated-gate bipolar transistors, the second epitaxial layer 203L having a second conductivity type can serve as a drift region of the semiconductor device 500. In some embodiments, the second epitaxial layer 203L is located on the top layer of the substrate structure 210, and may also be referred to as the top epitaxial layer 203L. The first epitaxial layer 202 is located in the middle layer of the substrate structure 210, and may also be referred to as the middle epitaxial layer 202.

[0014] As shown in Figure 1, the second epitaxial layer 203L may include multiple regions 203-1, 203-2, and 203-3 arranged side-by-side along the X direction (channel length direction). In the Z direction (vertical direction), the depths of regions 203-1, 203-2, and 203-3 may all be the same as the thickness D1 of the second epitaxial layer 203L. In some embodiments, the top surface T1 of region 203-1, the top surface T2 of region 203-2, and the top surface T3 of region 203-3 may be coplanar and may each be a different portion of the top surface 203LT of the second epitaxial layer 203L. The bottom surface T1 of region 203-1, the bottom surface T2 of region 203-2, and the bottom surface T3 of region 203-3 may be coplanar and may each be a different portion of the bottom surface 203LB of the second epitaxial layer 203L. Furthermore, the interface F12 between region 203-2 and region 203-1, and the interface F23 between region 203-2 and region 203-3, both extend along the Z direction from the top surface 203LT of the top epitaxial layer 203L to the bottom surface 203LB of the top epitaxial layer 203L. Therefore, the first epitaxial layer 202 can simultaneously contact the first region 203-1, the second region 203-2, and the third region 203-3 of the second epitaxial layer 203L.

[0015] In some embodiments, adjacent regions in regions 203-1, 203-2, and 203-3 may have different doping concentrations depending on the component's electrical characteristics (e.g., on-resistance or breakdown voltage). For example, the doping concentrations of regions 203-1, 203-2, and 203-3 may increase gradually. In other words, the doping concentration of region 203-1 is less than that of region 203-2, and the doping concentration of region 203-2 is less than that of region 203-3. In this embodiment, the doping concentration of region 203-1 may be the same as the original doping concentration of the second epitaxial layer 203L.

[0016] In some embodiments, the doping concentration of region 203-2 may be greater than or less than the doping concentrations of regions 203-1 and 203-3. In this embodiment, regions 203-1 and 203-3 may also have the same doping concentration. The second epitaxial layer 203L may have any number of regions with different doping concentrations, and is not limited to the embodiments disclosed herein.

[0017] In some embodiments, the composition of the bottom layer 201, the first epitaxial layer 202, and the second epitaxial layer 203L may each be silicon carbide (SiC) or silicon (Si). In some embodiments, the first epitaxial layer 202 and the second epitaxial layer 203L may be formed using an epitaxial process, including metal-organic chemical vapor deposition (MOCVD), plasma-enhanced chemical vapor deposition (PECVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), chloride vapor phase epitaxy (Cl-VPE), other suitable epitaxial growth processes, or combinations thereof.

[0018] The well region 207 of the semiconductor device 500 is disposed in regions 203-3 of the second epitaxial layer 203L. In some embodiments, the well region 207 may be doped with a dopant to have a first conductivity type. For example, when the bottom layer 201 is an N-type bottom layer 201, the well region 207 is a P-type well region 207. Furthermore, the doping concentration of the well region 207 may be the same as the doping concentration of the first epitaxial layer 202, for example, approximately 10¹⁷-10¹⁸ atoms / cm³.

[0019] The emitter contact region 209 of the semiconductor device 500 is disposed on the well region 207. In some embodiments, the emitter contact region 209 may be doped with a dopant to have a second conductivity type. For example, when the bottom layer 201 is an N-type bottom layer 201, the emitter contact region 209 is an N-type contact region 209. Furthermore, the doping concentration of the emitter contact region 209 may be the same as the doping concentration of the bottom layer 201, for example, approximately 10¹⁹-10²¹ atoms / cm³.

[0020] The semiconductor device 500 also includes a bulk contact region 211. The bulk contact region 211 is disposed on the well region 207. In some embodiments, the bulk contact region 211 may be adjacent to the emitter contact region 209. In some embodiments, the bulk contact region 211 may be doped with a dopant to have the same conductivity type as the well region 207. For example, when the well region 207 has a first conductivity type (e.g., a P-type well region 207), the bulk contact region 211 may also have a first conductivity type (e.g., a P-type bulk contact region 211). Furthermore, the doping concentration of the bulk contact region 211 is greater than the doping concentration of the well region 207, for example, 10¹⁹-10²¹ atoms / cm³. For example, when the well region 207 is a P-type well region 207, the bulk contact region 211 is a heavily doped P-type (P+) region 211, serving as a connection doped region for the well region 207.

[0021] The collector contact region 213 of the semiconductor device 500 is disposed in region 203-1 of the second epitaxial layer 203L, such that region 203-2 is located between well region 207 and collector contact region 213. In embodiments using lateral insulated-gate bipolar transistors, the emitter contact region 209 of the semiconductor device 500 and the collector contact region 213 have opposite conductivity types. In some embodiments, the substrate contact region 211 may be doped to have a first conductivity type. For example, when the bottom layer 201 is an N-type bottom layer 201, the collector contact region 213 is a P-type collector contact region 213. Furthermore, the doping concentration of the collector contact region 213 may be the same as the doping concentration of the substrate contact region 211, for example, approximately 10¹⁹-10²¹ atoms / cm³. Therefore, the collector contact region 213 is a heavily doped P-type (P+) region 213.

[0022] The isolation doped region 215 of the semiconductor device 500 is disposed in regions 203-3 of the second epitaxial layer 203L, and is located between the well region 207 and the collector contact region 213. In some embodiments, the isolation doped region 215 may be doped with a dopant to have a first conductivity type. For example, when the bottom layer 201 is an N-type bottom layer 201, the isolation doped region 215 is a P-type isolation doped region 215. Furthermore, the doping concentration of the isolation doped region 215 may be the same as the doping concentration of the substrate contact region 211 and the collector contact region 213, for example, approximately 10¹⁹-10²¹ atoms / cm³. Therefore, the isolation doped region 215 is a heavily P-type doped (P+) region 215.

[0023] As shown in Figure 1, the isolation doped region 215 is located close to the edge of the subsequently formed gate 219 to reduce the surface electric field at the edge of the gate 219, thereby increasing the breakdown voltage of the semiconductor device 500.

[0024] As shown in Figure 1, the semiconductor device 500 also includes a plurality of trenches 232 disposed in the second epitaxial layer 203L of the substrate structure 210 (as shown in framed region A; see Figure 2 for detailed structure). In some embodiments, these trenches 232 are disposed in regions 203-3 of the second epitaxial layer 203L. These trenches 232 extend laterally from the emitter contact region 209 to the isolation doped region 215 along a first direction (e.g., the X-axis direction), for example, continuously extending from the right side adjacent to the emitter contact region 209 to the left side adjacent to the isolation doped region 215, and the bottom surface of these trenches 232 is higher than the bottom surface of the emitter contact region 209 and the bottom surface of the isolation doped region 215.

[0025] The gate 219 of the semiconductor device 500 is disposed on the substrate structure 210 and fills the trenches 232. A gate dielectric layer 217 is disposed below the gate 219 and is compliantly formed on the sidewalls and bottom surfaces of the trenches 232, as well as on the top surface of the substrate structure 210 (i.e., the top surface 203LT of the second epitaxial layer 203L and the top surface T3 of region 203-3) (see Figure 3 for detailed structure). In this embodiment, the distance between the collector contact region 213 and the gate 219 is greater than the distance between the emitter contact region 209 and the gate 219. In other embodiments, the distance between the collector contact region 213 and the gate 219 may be equal to the distance between the emitter contact region 209 and the gate 219.

[0026] Additionally, the semiconductor device 500 also includes a shallow trench isolation (STI) structure 205 disposed within the substrate structure 210, for example, within the second epitaxial layer 203L. According to some embodiments disclosed herein, the top surface of the emitter contact region 209, the top surface of the isolation doped region 215, the top surface of the collector contact region 213, and the top surface of the shallow trench isolation structure 205 are all on the same plane, for example, all on the top surface of the substrate structure 210 (i.e., the top surface 203LT of the second epitaxial layer 203L).

[0027] The semiconductor device 500 further includes an interlayer dielectric layer 220. The interlayer dielectric layer 220 may be disposed entirely on the substrate structure 210 and cover the gate 219. In some embodiments, the interlayer dielectric layer 220 may include silicon oxide, silicon nitride, silicon oxynitride, silicon phosphorus glass (PSG), silicon borosilicate glass (BPSG), or a combination thereof. In some embodiments, the interlayer dielectric layer 220 may be formed using conformably deposited processes, oxidation processes, other suitable formation processes, and subsequent patterning processes. In some embodiments, the oxidation process may be thermal oxidation or other suitable processes. In some embodiments, the deposition process may be physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-assisted chemical vapor deposition (PECVD), other suitable processes, or a combination thereof.

[0028] The semiconductor device 500 further includes an emitter contact 221 and a collector contact 223 disposed on the second epitaxial layer 203L. The emitter contact 221 extends from above the interlayer dielectric layer 220 in the Z direction, passing through the interlayer dielectric layer 220 to cover and electrically connect the emitter contact region 209 and the substrate contact region 211. The collector contact 223 extends from above the interlayer dielectric layer 220 in the Z direction, passing through the interlayer dielectric layer 220 to cover and electrically connect the collector contact region 213.

[0029] As shown in Figure 1, the semiconductor device 500 further includes an emitter electrode 222 and a collector electrode 224 disposed on the second epitaxial layer 203L. The emitter electrode 222 is electrically coupled to the emitter contact region 209 and the substrate contact region 211 via an emitter contact 221, and the collector electrode 224 is electrically coupled to the collector contact region 213 via a collector contact 223. In some embodiments, the emitter electrode 222 and the collector electrode 224 may comprise copper, silver, gold, aluminum, tungsten, other suitable metal materials, or combinations thereof. In some embodiments, the emitter electrode 222 and the collector electrode 224 may comprise the same material or different materials. In some embodiments, the emitter electrode 222 and the collector electrode 224 may be formed using a deposition process and a subsequent patterning process. In some embodiments, the deposition process may include a physical vapor deposition process, a chemical vapor deposition process, other suitable processes, or combinations thereof.

[0030] Figure 2 is a perspective view of the frame region A of the semiconductor device disclosed in some embodiments of Figure 1. Figure 3 is a cross-sectional view along tangent BB and tangent B'-B' in Figure 2, wherein tangent BB passes through well region 207 and tangent B'-B' passes through second epitaxial layer 203L. For clarity, the gate 219 and gate dielectric layer 217 are not shown in the perspective view of Figure 2. As shown in Figures 2 and 3, the substrate structure 210 of the semiconductor device 500 includes a plurality of strip structures 231 that extend laterally along a first direction (e.g., the X-axis direction) from the right side of the contact emitter contact region 209, across a portion of the well region 207 and the second epitaxial layer 203L, to the left side of the contact isolation doped region 215. These strip structures 231 and the aforementioned plurality of trenches 232 are arranged alternately along a second direction (e.g., the Y-axis direction), and the bottom surfaces of these strip structures 231 are all higher than the bottom surfaces of the emitter contact region 209 and the isolation doped region 215. Furthermore, the top surfaces of these strip structures 231, the top surfaces of the emitter contact region 209 and the top surfaces of the isolation doped region 215 are all on the same plane, and the top surfaces of these strip structures 231 and the top surfaces of the shallow trench isolation structure 205 are also on the same plane. As shown in the cross-sectional schematic diagram of Figure 3, the gate dielectric layer 217 is compliantly formed on the sidewalls and top surface of these strip structures 231, as well as on the bottom surface of the multiple trenches 232. The gate 219 is filled in the multiple trenches 232 and located on the top surface of these strip structures 231. The gate 219 may have a flat top surface.

[0031] In some embodiments, the substrate structure 210 or the second epitaxial layer 203L is composed of silicon carbide (SiC), the sidewall P2 of the strip structure 231 can be the (0, -3, 3, -8) crystal plane, (1, 1, -2, 0) crystal plane or other low interface state density crystal plane of silicon carbide, and the top surface P1 of the strip structure 231 is the (0, 0, 0, 1) crystal plane of silicon carbide. Compared to the (0, 0, 0, 1) crystal plane of silicon carbide, the (0, -3, 3, -8) and (1, 1, -2, 0) crystal planes of silicon carbide have lower interface state density and higher free electronization, resulting in a significant increase in electron channel mobility. The channel mobility of the (0, -3, 3, -8) crystal plane can be about 4 to 5 times that of the (0, 0, 0, 1) crystal plane, and the channel mobility of the (1, 1, -2, 0) crystal plane can be about 2 times that of the (0, 0, 0, 1) crystal plane. Furthermore, the multiple sidewalls P2 of the multiple strip structures 231 can increase the channel width (e.g., in the Y-axis direction) by several times, thus significantly improving the channel mobility of the semiconductor device 500, thereby reducing the characteristic on-resistance (R onsp) and increasing the forward current.

[0032] In another embodiment, the second epitaxial layer 203L is composed of silicon, for example. The sidewalls P2 and top surface P1 of the strip structure 231 are both silicon (1, 0, 0) crystal planes. Although the channel mobility cannot be improved by utilizing the sidewall crystal planes, the channel width (e.g. in the Y-axis direction) can still be increased several times by means of the multiple sidewalls P2 of the multiple strip structures 231, so as to improve the channel mobility of the semiconductor device 500, thereby reducing the characteristic on-resistance (R onsp) and increasing the forward current.

[0033] The following describes a method for forming a semiconductor device 500 according to some embodiments of the present invention. Figures 4, 5, 6, 7, 8A, 9A, and 10A are cross-sectional schematic diagrams of intermediate stages in forming the semiconductor device 500 of some embodiments of the present disclosure shown in Figure 1. Figures 8B, 9B, and 10B are perspective schematic diagrams of intermediate stages in forming the framed region A of the semiconductor device 500 of some embodiments of the present disclosure shown in Figure 1, wherein the same or similar element symbols as in Figure 1 represent the same or similar elements.

[0034] As shown in Figure 4, a substrate structure 210 is first provided, which includes a bottom layer 201, a first epitaxial layer 202, and a second epitaxial layer 203L stacked sequentially from bottom to top. A shallow trench isolation structure 205 is formed in the second epitaxial layer 203L using photolithography, etching, filling, and chemical mechanical planarization processes.

[0035] Next, as shown in Figure 5, a first conductivity type (P-type) dopant is implanted in the second epitaxial layer 203L using an ion implantation process and a mask to form well region 207.

[0036] Next, as shown in Figure 6, using a multi-pass ion implantation process and multiple masks, second conductivity type (N-type) dopants are implanted in different regions within the second epitaxial layer 203L to form regions 203-1, 203-2, and 203-3. For example, a mask can be used to cover region 203-3, and then an ion implantation process can be used to implant second conductivity type (N-type) dopants in regions 203-1 and 203-2; then another mask can be used to cover regions 203-2 and 203-3, and then an ion implantation process can be used to implant second conductivity type (N-type) dopants in region 203-1 to form regions 203-1, 203-2, and 203-3 with different doping concentrations. In this embodiment, the doping concentration of region 203-1 is greater than that of region 203-2, and the doping concentration of region 203-2 is greater than that of region 203-3. The doping concentrations of regions 203-1, 203-2, and 203-3 can be adjusted arbitrarily, and are not limited to the embodiments disclosed herein. In some embodiments, the doping concentration of region 203-3 is equal to the doping concentration of the second epitaxial layer 203L. Furthermore, well region 207 is located in region 203-3.

[0037] Next, as shown in Figure 7, using another ion implantation process and another mask, a first conductivity type (P-type) dopant is implanted in region 203-1 of the well region 207 and the second epitaxial layer 203L to form the substrate contact region 211 and the isolation doped region 215. Then, using another ion implantation process and another mask, a second conductivity type (N-type) dopant is implanted in region 203-3 of the well region 207 and the second epitaxial layer 203L to form the emitter contact region 209 and the collector contact region 213.

[0038] Next, as shown in Figures 8A and 8B, using photolithography and etching processes, alternating trenches 232 and strip structures 231 are etched in the well region 207 and the second epitaxial layer 203L, specifically in the frame region A between the emitter contact region 209 and the isolation doped region 215. By controlling the etching process parameters, the bottom surfaces of the trenches 232 are all higher than the bottom surfaces of the emitter contact region 209 and the isolation doped region 215. In some embodiments, the etching process includes dry etching. Dry etching may include plasma etching, plasmaless gas etching, sputter etching, ion milling, reactive ion etching (RIE), neutral beam etching (NBE), inductively coupled plasma etching, or other suitable processes.

[0039] Next, as shown in Figures 9A and 9B, a gate dielectric layer 217, for example a silicon oxide layer, is compliantly formed on the sidewalls and top surfaces of the multiple strip structures 231, the bottom surfaces of the multiple trenches 232, and the top surface of the substrate structure 210 using a thermal oxidation or deposition process.

[0040] Next, as shown in Figures 10A and 10B, a gate material layer is deposited on the surface of the substrate structure 210 using deposition and chemical mechanical planarization processes, and the gate material layer fills multiple trenches 232. In some embodiments, the gate material layer is, for example, a polycrystalline silicon layer. A second conductivity type (N-type) dopant is implanted into the gate material layer using an ion implantation process and a mask to form an N-type doped polycrystalline silicon layer. Then, the N-type doped polycrystalline silicon layer is patterned using photolithography and etching processes to form the gate 219.

[0041] In some embodiments, after the gate 219 is formed, a dielectric layer (not shown in the figures), such as a silicon oxide layer, can be compliantly formed on the sidewalls and top surface of the gate 219 and the top surface of the substrate structure 210 (i.e., the top surface 203LT of the second epitaxial layer 203L) using a thermal oxidation or deposition process. This dielectric layer can increase the adhesion between the surfaces of the substrate structure 210 and the gate 219 shown in Figures 10A and 10B and the subsequently formed interlayer dielectric layer 220.

[0042] Next, as shown in Figure 1, a backend process is performed to deposit an interlayer dielectric layer 220 on the substrate structure 210. Then, using photolithography, etching, and deposition processes, emitter contacts 221, collector contacts 223, and other contact plugs are formed within the interlayer dielectric layer 220. Next, emitter electrodes 222, collector electrodes 224, and other conductive lines are formed on the interlayer dielectric layer 220. After the above processes, the semiconductor device 500 of Figure 1 is completed.

[0043] This disclosure provides embodiments of semiconductor devices (e.g., laterally insulated-gate bipolar transistors) and methods for forming the same. According to some embodiments of this disclosure, a plurality of trenches (e.g., trenches 232) and a plurality of strip structures (e.g., strip structures 231) are alternately arranged within a substrate structure (e.g., substrate structure 210) of the semiconductor device. These trenches and strip structures are located between an emitter region (e.g., emitter contact region 209) and a collector region (e.g., collector contact region 213). A gate (e.g., gate 219) is disposed on the substrate structure and fills these trenches to enclose these strip structures, thereby creating a three-dimensional channel structure. Without increasing the wafer area, the channel width can be increased by the three-dimensional channel structure, and the channel mobility can be increased by utilizing the sidewall crystal faces of the strip structures, thereby reducing on-resistance and increasing forward current to improve the electrical performance of the semiconductor device. Furthermore, the drift region (second epitaxial layer 203L) of the semiconductor device may have multiple regions with different doping concentrations, so that the three-dimensional channel structure and the collector region (collector contact region 213) are respectively disposed in different regions. By adjusting the doping concentration of the above regions, the on-resistance of the semiconductor device can be further reduced (or the on-resistance can be further increased under the same breakdown voltage conditions).

[0044] This disclosure provides a semiconductor device. The semiconductor device includes a substrate structure, a well region, an emitter contact region, a collector contact region, an isolation doped region, a plurality of trenches, and a gate. The substrate structure includes a top epitaxial layer. The top epitaxial layer includes a first region and a second region. The well region is located outside the first region of the top epitaxial layer. The well region has a first conductivity type, and the top epitaxial layer has a second conductivity type. The emitter contact region is disposed on the well region. The collector contact region is disposed in the first region of the top epitaxial layer. The emitter contact region and the collector contact region have opposite conductivity types. The isolation doped region is disposed outside the first region of the top epitaxial layer and between the well region and the collector contact region, and the isolation doped region has a first conductivity type. A plurality of trenches are disposed in the substrate structure. The trenches extend from the emitter contact region to the isolation doped region along a first direction, and a plurality of bottom surfaces of the trenches are higher than the bottom surfaces of the emitter contact region and the isolation doped region. A gate is disposed on the substrate structure and fills the trenches. The distance between the collector contact region and the gate is greater than the distance between the emitter contact region and the gate. The first and second regions of the top epitaxial layer have different doping concentrations.

[0045] In some embodiments, the emitter contact region has a second conductivity type, and the collector contact region has a first conductivity type.

[0046] In some embodiments, the well region and the isolation doped region are disposed in the second region of the top epitaxial layer.

[0047] In some embodiments, the doping concentration of the first region is lower than that of the second region.

[0048] In some embodiments, the first top surface of the first region and the second top surface of the second region are different portions of the top surface of the top epitaxial layer, and the first bottom surface of the first region and the second bottom surface of the second region are different portions of the bottom surface of the top epitaxial layer.

[0049] In some embodiments, the trench is provided in the second region of the top epitaxial layer.

[0050] In some embodiments, the top epitaxial layer further includes a third region. The second region is located between the first region and the third region along a first direction, and the doping concentration of the second region is different from the doping concentration of the first region and the doping concentration of the third region.

[0051] In some embodiments, the well region and the isolation doped region are disposed in the third region of the top epitaxial layer.

[0052] In some embodiments, the doping concentration of the first region is the same as that of the third region.

[0053] In some embodiments, the first interface between the second region and the first region and the second interface between the second region and the third region both extend from the top surface of the top epitaxial layer to the bottom surface of the top epitaxial layer along the second direction.

[0054] In some embodiments, the substrate structure includes a bottom layer and an intermediate epitaxial layer. The bottom layer has a second conductivity type. The intermediate epitaxial layer is disposed between the bottom layer and the top epitaxial layer. The intermediate epitaxial layer has a first conductivity type.

[0055] In some embodiments, the substrate structure includes a plurality of strip structures that extend from the emitter contact region to the isolation doped region along a first direction, and the strip structures and trenches are alternately arranged along a third direction.

[0056] In some embodiments, the substrate structure comprises silicon carbide or silicon, and the plurality of sidewalls of the strip structure each comprise a (0, -3, 3, -8) crystal plane or a (1, 1, -2, 0) crystal plane of silicon carbide, or a (1, 0, 0) crystal plane of silicon.

[0057] In some embodiments, the semiconductor device further includes a shallow trench isolation structure. The shallow trench isolation structure is disposed in a substrate structure. Multiple top surfaces of the strip structure, the top surface of the emitter contact region, the top surface of the isolation doped region, the top surface of the collector contact region, and the top surface of the shallow trench isolation structure are all on the same plane.

[0058] While the present invention has been disclosed above with reference to the foregoing embodiments, it is not intended to limit the invention. Those skilled in the art can make modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of this invention shall be determined by the appended claims.

[0059] 201: Bottom Layer 202: First epitaxial layer 203L: Second epitaxial layer 203LT,T1,T2,T3,P1: Top surface 203LB, B1, B2, B3: Top surface 203-1, 203-2, 203-3: Area 205: Shallow trench isolation structure 207: Well Area 209: Emitter Contact Area 210: Base structure 211: Matrix contact area 213: Collector Contact Region 215: Isolation Doped Region 217: Gate dielectric layer 219: Gate 220: Interlayer dielectric layer 221: Emitter Contact 222: Emitter electrode 223: Collector Contact 224: Collector electrode 231: Strip-like structure 232: Trench 500: Semiconductor Devices A: Bordered area D1: Thickness F12, F23: Interface BB,B'-B': Tangent P2: Sidewall X, Y, Z: Direction

Claims

1. A semiconductor device, comprising: A substrate structure, wherein the substrate structure includes a top epitaxial layer, wherein the top epitaxial layer includes a first region and a second region; A well region is located outside the first region of the top epitaxial layer, wherein the well region has a first conductivity type and the top epitaxial layer has a second conductivity type; an emitter contact region is disposed on the well region; a collector contact region is disposed in the first region of the top epitaxial layer, wherein the emitter contact region and the collector contact region have opposite conductivity types; an isolation doped region is disposed outside the first region of the top epitaxial layer and located between the well region and the collector contact region, wherein the isolation doped region has the first conductivity type; Multiple trenches are disposed in the substrate structure, wherein the trenches extend from the emitter contact region to the isolation doped region along a first direction, and multiple bottom surfaces of the trenches are higher than a bottom surface of the emitter contact region and a bottom surface of the isolation doped region; and a gate is disposed on the substrate structure and fills the trenches, wherein the distance between the collector contact region and the gate is greater than the distance between the emitter contact region and the gate, and wherein the first region and the second region of the top epitaxial layer have different doping concentrations.

2. The semiconductor device as claimed in claim 1, wherein the emitter contact region has the second conductivity type and the collector contact region has the first conductivity type.

3. The semiconductor device as claimed in claim 1, wherein the well region and the isolation doped region are disposed in the second region of the top epitaxial layer.

4. The semiconductor device as claimed in claim 1, wherein the doping concentration of the first region is less than the doping concentration of the second region.

5. The semiconductor device as claimed in claim 1, wherein a first top surface of the first region and a second top surface of the second region are different portions of a top surface of the top epitaxial layer, and a first bottom surface of the first region and a second bottom surface of the second region are different portions of a bottom surface of the top epitaxial layer.

6. The semiconductor device as claimed in claim 1, wherein the trenches are disposed in the second region of the top epitaxial layer.

7. The semiconductor device as claimed in claim 1, wherein the top epitaxial layer further comprises: A third region, wherein the second region is located between the first region and the third region along the first direction, and the doping concentration of the second region is different from the doping concentration of the first region and the doping concentration of the third region.

8. The semiconductor device as claimed in claim 7, wherein the well region and the isolation doped region are disposed in the third region of the top epitaxial layer.

9. The semiconductor device as claimed in claim 7, wherein the doping concentration of the first region is the same as the doping concentration of the third region.

10. The semiconductor device as claimed in claim 7, wherein a first interface between the second region and the first region and a second interface between the second region and the third region both extend along a second direction from a top surface of the top epitaxial layer to a bottom surface of the top epitaxial layer.

11. The semiconductor device as claimed in claim 1, wherein the substrate structure comprises: A bottom layer having this second conductivity type; And an intermediate epitaxial layer disposed between the bottom layer and the top epitaxial layer, wherein the intermediate epitaxial layer has the first conductivity type.

12. The semiconductor device as claimed in claim 1, wherein the substrate structure includes a plurality of strip structures extending from the emitter contact region to the isolation doped region along the first direction, and the strip structures and the trenches are alternately arranged along a third direction.

13. The semiconductor device as claimed in claim 12, wherein the substrate structure comprises silicon carbide or silicon, and the plurality of sidewalls of the strip structures each comprise a (0, -3, 3, -8) crystal plane or a (1, 1, -2, 0) crystal plane of silicon carbide, or a (1, 0, 0) crystal plane of silicon.

14. The semiconductor device as described in claim 12, further comprising: A shallow trench isolation structure is disposed in the substrate structure, wherein multiple top surfaces of the strip structures, a top surface of the emitter contact region, a top surface of the isolation doped region, a top surface of the collector contact region, and a top surface of the shallow trench isolation structure are all on the same plane.

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