ESD protection device, ESD power clamp device, and method of manufacturing the same

Abstract

A device includes a substrate and a first PIN diode for ESD protection situated in the substrate. The first PIN diode has a first region, a second region, and a first intrinsic semiconductor region situated between the first region and the second region. The device further includes a first backside via connected to the first region and to a backside pad contact, a second backside via connected to the second region and to a first backside power contact, and a first frontside conductive layer resistor for thermal sensing having a first end connected to the first region and a second end connected to the second region, where at least a portion of the first frontside conductive layer resistor is situated within a first footprint of the first PIN diode.

Claims

1. An electrostatic discharge (ESD) protection device, comprising: Base; A first PIN diode for electrostatic discharge (ESD) protection is located in the substrate and has a first region, a second region, and a first intrinsic semiconductor region located between the first region and the second region; a first back-side via is connected to the first region and a back-side pad contact; a second back-side via is connected to the second region and a first back-side power contact; And a first front conductive layer resistor for thermal sensing, having a first end connected to the first region and a second end connected to the second region, wherein at least a portion of the first front conductive layer resistor is located within a first package pin of the first PIN diode.

2. The apparatus of claim 1, comprising a sensing pin connected to a first terminal of a first front conductive layer resistor via a front conductive layer, and a stress pin connected to a second terminal of the first front conductive layer resistor via the front conductive layer.

3. The apparatus of claim 1, wherein the first front conductive layer resistor is configured to apply and sense stress via the back pad contact and the first back power contact.

4. The apparatus as claimed in claim 1, comprising: The second PIN diode is located in the substrate and has a third region, a fourth region, and a second intrinsic semiconductor region located between the third region and the fourth region; A third back-side via is connected to the third region and the back-side pad contact; a fourth back-side via is connected to the fourth region and a second back-side power contact different from the first back-side power contact; and a second front-side conductive layer resistor has a third end connected to the third region and a fourth end connected to the fourth region, wherein at least a portion of the second front-side conductive layer resistor is located within the second package pin of the second PIN diode.

5. An electrostatic discharge (ESD) power clamping device, comprising: A power clamping voltage divider includes: a first front conductive layer resistor having a first end connected to a VDD power contact and a second end connected to a voltage divider node; and a second front conductive layer resistor having a third end connected to the voltage divider node and a fourth end connected to a VSS power contact; a first ESD detection circuit connected to the VDD power contact and the voltage divider node; a first active trigger circuit connected to the first ESD detection circuit and connected to the VDD power contact and the voltage divider node; and a field-effect transistor circuit connected to the first active trigger circuit, with one side connected to the VDD power contact and the other side connected to the VSS power contact, wherein the power clamping voltage divider is a thermal sensor having one of a sensing or stress pin at the VDD power contact and the other of a sensing or stress pin at the VSS power contact.

6. The apparatus as claimed in claim 5, comprising: The second ESD detection circuit is connected to the voltage divider node and the VSS power supply contact. A second active trigger circuit is connected to the second ESD detection circuit and to the voltage divider node and the VSS power supply contact, wherein the field-effect transistor circuit is connected to the second active trigger circuit.

7. The apparatus of claim 5, wherein the first ESD detection circuit comprises a resistor and a capacitor, one end of the resistor being connected to the VDD power contact, the other end being connected to one end of the capacitor and the first active trigger circuit, and the other end of the capacitor being connected to the voltage divider node.

8. The apparatus of claim 5, wherein the first active trigger circuit comprises a PMOS transistor and an NMOS transistor connected in series and connected between the VDD power contact and the voltage divider node.

9. The apparatus of claim 5, wherein the field-effect transistor circuit comprises a metal-oxide-semiconductor field-effect transistor having a first drain / source region connected to the VDD power contact via a first back-side via, and a second drain / source region connected to the VSS power contact via a second back-side via.

10. A method for manufacturing an ESD protection device, comprising: Forming a PIN diode matrix in a substrate includes forming PIN diodes by the following steps: forming a first doped region of the PIN diodes; An intrinsic semiconductor region of the PIN diode is formed adjacent to the first doped region; and a second doped region of the PIN diode is formed adjacent to the intrinsic semiconductor region of the PIN diode; a front conductive layer resistor is formed, with a first end connected to the first doped region and a second end connected to the second doped region, wherein the PIN diode matrix includes the PIN diode and the front conductive layer resistor, such that at least a portion of the front conductive layer resistor is located within the package pins of the PIN diode matrix; a first back via is formed, connected to the first doped region and a back pad contact; and a second back via is formed, connected to the second doped region and a back power contact.

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