Capacitance structure and manufacturing method thereof

Abstract

The invention provides a capacitor structure, which comprises a first capacitor structure located on a substrate, wherein the first capacitor structure comprises a plurality of lower electrode layers, wherein each lower electrode layer is arranged in the same direction and stacked with each other along a height direction (Z direction), and a second capacitor structure located on the first capacitor structure, wherein the second capacitor structure comprises a plurality of upper electrode layers, wherein some upper electrode layers are arranged in a first direction (X direction), and the other upper electrode layers are arranged in a second direction (Y direction), and the first direction and the second direction are perpendicular to each other.

Description

[Technical Field]

[0001] This invention relates to the semiconductor field, and more particularly to a composite capacitor composed of an alternating polarity MOM capacitor (APMOM capacitor) and a braided MOM capacitor. [Previous Technology]

[0002] In integrated circuit design, capacitors play an indispensable role. Among them, MOM (Metal-Oxide-Metal) capacitors and MIM (Metal-Insulator-Metal) capacitors are two common capacitor structures. Although they are both composed of metal and insulating layers, they differ significantly in structure, manufacturing process, and performance. These differences directly affect their selection in different application scenarios.

[0003] MOM capacitors primarily utilize the oxide layer between the same or adjacent metal layers as the dielectric, forming an interdigital electrode structure. The advantage of this structure lies in its simple fabrication process, eliminating the need for an additional masking layer and fully utilizing existing metal interconnect layers. However, due to the relatively low dielectric constant of the oxide layer and its large parasitic capacitance, MOM capacitors typically have small capacitance values ​​and relatively limited frequency characteristics. Nevertheless, MOM capacitors are still widely used in digital circuits as coupling capacitors, bypass capacitors, etc.

[0004] MIM capacitors use different layers of metal with a high-dielectric-constant insulating layer sandwiched in between. The advantages of this structure are a larger capacitance, excellent frequency characteristics, and relatively stable capacitance. However, the manufacturing process of MIM capacitors is relatively complex, requiring additional shielding layers and process steps. Furthermore, the high-dielectric-constant insulating layer may introduce significant leakage current, affecting the capacitor's performance. MIM capacitors are typically used in analog circuits, radio frequency circuits, and other applications where high capacitance accuracy is required. [Summary of the Invention]

[0005] The present invention provides a capacitor structure, comprising a first capacitor structure located on a substrate, wherein the first capacitor structure is a metal-oxide-metal (MOM) capacitor structure, comprising multiple lower electrode layers, wherein each lower electrode layer is arranged facing the same direction and stacked with each other along a height direction (Z direction), and a second capacitor structure located on the first capacitor structure, wherein the second capacitor structure is a metal-oxide-metal (MOM) capacitor structure, comprising multiple upper electrode layers, wherein a portion of the upper electrode layers are arranged facing a first direction (X direction), and another portion of the upper electrode layers are arranged facing a second direction (Y direction), the first direction and the second direction are perpendicular to each other, and the upper electrode layers arranged facing the first direction (X direction) and the upper electrode layers arranged facing the second direction (Y direction) are alternately stacked along the height direction (Z direction).

[0006] The present invention further provides a method for manufacturing a capacitor structure, comprising forming a first capacitor structure on a substrate, wherein the first capacitor structure is a metal-oxide-metal (MOM) capacitor structure, comprising multiple layers of lower electrode layers, wherein each lower electrode layer is arranged in the same direction and stacked with each other along a height direction (Z direction), and forming a second capacitor structure on the first capacitor structure, wherein the second capacitor structure is a metal-oxide-metal (MOM) capacitor structure, comprising multiple layers of upper electrode layers, wherein a portion of the upper electrode layers are arranged in a first direction (X direction), and another portion of the upper electrode layers are arranged in a second direction (Y direction), the first direction and the second direction are perpendicular to each other, and the upper electrode layers arranged in the first direction (X direction) and the upper electrode layers arranged in the second direction (Y direction) are alternately stacked along the height direction (Z direction).

[0007] The present invention is characterized by providing a composite capacitor structure, comprising a lower alternating polarity MOM capacitor (APMOM capacitor) and an upper braided MOM capacitor (Woven MOM capacitor). The APMOM capacitor has a higher overlap area and capacitance value, while the Woven MOM capacitor offers more flexible routing and simpler manufacturing processes. Therefore, the composite capacitor of the present invention combines these two types of MOM capacitors, thus obtaining the advantages of both. Specifically, the APMOM capacitor can be used in the lower layer structure of the semiconductor device to increase the capacitance value, while the Woven MOM capacitor in the upper layer structure offers advantages such as more flexible routing direction and reduced manufacturing difficulty. Therefore, the composite capacitor structure of the present invention has advantages such as higher capacitance value, lower manufacturing difficulty, and compatibility with existing technologies.

Implementation Method

[0008] Although specific configurations and arrangements are discussed herein, it should be understood that this is done for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this disclosure. It will be apparent to those skilled in the art that this disclosure can also be used in a variety of other applications.

[0009] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include specific features, structures, or characteristics. Furthermore, such terms do not necessarily refer to the same embodiments. In addition, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0010] Generally, terms can be understood at least in part according to their usage in context. For example, the term “one or more” (at least in part according to context) as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a plural combination of features, structures, or characteristics. Similarly, terms such as “a,” “an,” or “the” can again be understood to express a singular usage or convey a plural usage, at least in part according to context. Furthermore, the term “based on” can be understood to not necessarily convey an exclusive set of factors, and can conversely allow for the presence of additional factors that are not necessarily explicitly described, at least in part according to context.

[0011] It should be readily understood that the meanings of “on top of,” “above,” and “above” in the disclosure of this case should be interpreted in the broadest sense, such that “on top of” not only means “directly” on something, but also includes the meaning of being on something and having intermediate features or layers between them, and that “on top of” or “above” not only means being on or above something, but also includes the meaning of not having intermediate features or layers (i.e., being directly on something).

[0012] Furthermore, for ease of description, as indicated in the figures, spatial relative terms such as “below,” “under,” “lower,” “above,” and “higher” can be used to describe the relationship (one or more) of one element or feature to another. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the element in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptions used herein can be interpreted accordingly.

[0013] As used herein, the term "substrate" refers to the material on which a layer of material is subsequently added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0014] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entire lower or upper layer structure, or may have a extent smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes between the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a single layer, which may include one or more layers, and / or may have one or more layers on and / or below it. A single layer may contain multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where contacts, interconnects, and / or vias are formed) and one or more dielectric layers.

[0015] As mentioned above, capacitors are widely used in integrated circuit design. Among them, MOM (Metal-Oxide-Metal) capacitors are often used as the main capacitors in smaller electronic components because they can be fabricated together with the conductive layers of electronic components.

[0016] In one embodiment of the present invention, a composite MOM capacitor structure is provided, which mainly consists of two parts: an alternating polarity metal-oxide-metal (APMOM) capacitor located in the lower layer, and a braided MOM capacitor located in the upper layer, also known as a Woven MOM capacitor. In some embodiments, the APMOM capacitor is located in the first three layers of the semiconductor stack structure, while the fourth and subsequent layers use Woven MOM capacitors. However, the number of layers here is only an example and the present invention is not limited thereto. The structures and arrangements of the APMOM capacitor and the Woven MOM capacitor are slightly different, and these two MOM capacitor structures will be described separately below.

[0017] Figure 1 shows a top view of an alternating polarity MOM (APMOM) capacitor in the composite capacitor of the present invention, and Figure 2 shows a schematic diagram of the arrangement structure of the alternating polarity MOM (APMOM) capacitor in Figure 1. As shown in Figures 1 and 2, the APMOM capacitor 10 of the present invention includes multiple layers of stacked lower metal layers. Here, lower metal layers 11 and 12 are used as examples for explanation, wherein lower metal layers 11 and 12 are stacked and partially overlap. It is worth noting that although two lower metal layers (i.e., lower metal layers 11 and 12) are described here, the present invention is not limited to the number of lower metal layers. If the APMOM capacitor 10 includes two or more lower metal layers, it is within the scope of the present invention.

[0018] It is worth noting that the lower metal layer 11 and the lower metal layer 12 are stacked on top of each other and have a portion of their areas overlap. For example, the lower metal layer 12 can be stacked on top of the lower metal layer 11, that is, the lower metal layer 12 and the lower metal layer 11 partially overlap in the Z-axis direction. In Figure 1, to clearly illustrate the schematic features, the lower metal layer 11 is drawn in the middle area, the lower metal layer 12 is drawn in the right area, and the APMOM capacitor 10 on the left is a schematic diagram of the lower metal layer 11 and the lower metal layer 12 after being stacked.

[0019] The lower metal layer 11 includes two main shaft electrodes 11A and 11B and a plurality of parallel branch electrodes 11C and 11D. The main shaft electrodes 11A and 11B are arranged along a first direction (e.g., the X direction) and are located near the upper and lower positions, respectively, in Figure 1. The plurality of branch electrodes 11C and 11D are arranged along a second direction (e.g., the Y direction). Each branch electrode 11C is connected to the main shaft electrode 11A located near the upper position, and each branch electrode 11D is connected to the main shaft electrode 11B located near the lower position. Furthermore, viewed along the X direction, the branch electrodes 11C and 11D are arranged alternately, for example, in the order of branch electrode 11C, branch electrode 11D, branch electrode 11C, branch electrode 11D… The lengths of the branch electrodes 11C and 11D in the Y direction are preferably the same. The two main axis electrodes 11A and 11B, and the branch electrodes 11C and 11D are all formed by electrode patterns made of a highly conductive material (e.g., metal). Therefore, the lower metal layer 11 contains the two main axis electrodes 11A and 11B and the branch electrodes 11C and 11D made of conductive material, and forms an interdigital electrode pattern. The interdigital electrode pattern is located in a dielectric layer (not shown), which serves as the conductive layer of the MOM capacitor structure, while the dielectric layer serves as the oxide layer of the MOM capacitor structure.

[0020] In addition, the two main spindle electrodes 11A and 11B included in the lower metal layer 11 are connected to different polarities. For example, the main spindle electrode 11A is connected to a high polarity signal, while the main spindle electrode 11B is connected to a low polarity signal. Therefore, each branch electrode 11C connected to the main spindle electrode 11A will also maintain a high polarity, and on the other hand, each branch electrode 11D connected to the main spindle electrode 11B will also maintain a low polarity. From the X direction, each branch electrode 11C and each branch electrode 11D are arranged alternately, so each branch electrode is also arranged in the order of high polarity, low polarity, high polarity, low polarity...

[0021] The lower metal layer 12 has a structure similar to that of the lower metal layer 11. The lower metal layer 12 includes two main shaft electrodes 12A and 12B and multiple parallel branch electrodes 12C and 12D. The main shaft electrodes 12A and 12B are arranged along a first direction (e.g., the X direction) and are located near the top and bottom positions, respectively, in Figure 1. The multiple branch electrodes 12C and 12D are arranged along a second direction (e.g., the Y direction). Each branch electrode 12C is connected to the main shaft electrode 12A located near the top, and each branch electrode 12D is connected to the main shaft electrode 12D located near the bottom. Furthermore, viewed along the X direction, the branch electrodes 12C and 12D are arranged alternately, for example, from left to right in the order of branch electrode 12C, branch electrode 12D, branch electrode 12C, branch electrode 12D… The lengths of the branch electrodes 12C and 12D in the Y direction are preferably the same. The two main axis electrodes 12A and 12B, as well as the branch electrodes 12C and 12D, are all electrode patterns made of a highly conductive material (e.g., metal). Therefore, the lower metal layer 12 contains the two main axis electrodes 12A and 12B and the branch electrodes 12C and 12D made of conductive material, forming an interdigitated electrode pattern. The interdigitated electrode pattern is located in a dielectric layer (not shown), which serves as the conductive layer of the MOM capacitor structure, while the dielectric layer serves as the oxide layer of the MOM capacitor structure.

[0022] In addition, the two main spindle electrodes 12A and 12B included in the lower metal layer 12 are connected to different polarities. For example, the main spindle electrode 12A is connected to a low polarity signal, while the main spindle electrode 12B is connected to a high polarity signal. Therefore, each branch electrode 12C connected to the main spindle electrode 12A will also maintain a low polarity, and on the other hand, each branch electrode 12D connected to the main spindle electrode 12B will also maintain a high polarity. From the X direction, each branch electrode 12C and each branch electrode 12D are arranged alternately, so each branch electrode is also arranged in the order of low polarity, high polarity, low polarity, high polarity...

[0023] Referring also to Figure 2, for any branch electrode (11C, 11D or 12C, 12D) included in the lower metal layer 11 and the lower gold metal layer 12, the other branch electrodes adjacent to it in the X and Z directions have opposite polarities to itself. In other words, if a branch electrode 11C with high polarity is selected, then the branch electrodes 11D on both sides in the X direction are low polarity, and the branch electrode 12C above it also has low polarity. On the other hand, if a branch electrode 11D with low polarity is selected, then the branch electrodes 11C on both sides in the X direction are high polarity, and the branch electrode 12D above it also has high polarity. For clarity, different backgrounds are used in Figure 2 to represent high polarity and low polarity respectively. In addition, Figure 2 shows another lower metal layer 13 stacked on top of the lower metal layer 12, indicating that the APMOM capacitor 10 can include more lower electrode layers in addition to the lower metal layers 11 and 12. The pattern features of the lower metal layer 13 may be the same as or similar to those of the lower metal layer 11, so its detailed features will not be repeated here.

[0024] In addition, the APMOM capacitor 10 may also include multiple contact plugs V1, which are used to connect different metal electrode layers with the same polarity (e.g., both high polarity or both low polarity). Therefore, the signal output from the signal source can be transmitted to each metal electrode layer. In this embodiment, because the spindle electrode has a large linewidth, each contact plug V1 overlaps with each spindle electrode 11A / 11B / 12A / 12B. This makes it easy for the contact plugs V1 to align with each spindle electrode 11A / 11B / 12A / 12B without misalignment. However, the invention is not limited to this; in other embodiments of the invention, the position of the contact plugs V1 can be adjusted as needed.

[0025] In addition, the manufacturer can minimize the linewidth and spacing of the APMOM capacitor 10 formed in Figure 1 to increase the component density and reduce the overall component volume, thereby achieving miniaturization. In this embodiment, each lower metal layer in the APMOM capacitor 10 can be formed by two exposure and development steps (using two photomasks respectively). For example, the main axis electrode 11A and branch electrode 11C of the lower metal layer 11 can be formed by one exposure and development process, and then the main axis electrode 11B and branch electrode 11D of the lower metal layer 11 can be formed by another exposure and development process. By forming the pattern of the lower metal layer 11 by two exposure and development steps, the pattern density of the lower metal layer 11 can be increased. Similarly, the other lower metal layers 12, lower metal layers 13, etc. mentioned above are also preferably formed by two exposure and development steps. In this embodiment, taking a 14-nanometer process as an example, the minimum linewidth of the lower metal layer 11 and the minimum spacing between each branch electrode are approximately 36 nanometers, but the present invention is not limited to this. With technological advancements, the minimum line width and minimum spacing mentioned above may continue to decrease.

[0026] As shown in Figures 1 and 2, the APMOM capacitor 10 is characterized in that all its lower metal layers are arranged in the same direction. Specifically, the arrangement direction of the main axis electrodes 11A / 11B of the lower metal layer 11 is the same as that of the main axis electrodes 12A / 12B of the lower metal layer 12, and the arrangement direction of the branch electrodes 11C / 11D of the lower metal layer 11 is the same as that of the branch electrodes 12C / 12D of the lower metal layer 12. With this arrangement, the overlap area between different lower metal layers is large because each branch electrode has a large area of ​​overlap. Since the capacitance of the MOM capacitor is proportional to the overlap area between the electrodes, that is, the larger the overlap area between the electrodes, the larger the capacitance of the MOM capacitor, the larger the capacitance of the MOM capacitor. Therefore, the APMOM capacitor 10 has a large capacitance value, can store more charge in a limited area, and has higher efficiency.

[0027] Figure 3 illustrates a top view of an overlaid Woven MOM capacitor, one of the composite capacitors of the present invention, and Figure 4 illustrates a schematic diagram of the arrangement structure of the Woven MOM capacitor in Figure 3. As shown in Figures 3 and 4, the Woven MOM capacitor 20 of the present invention includes multiple stacked upper metal layers. Here, upper metal layer 21 and upper metal layer 22 are used as examples for explanation, wherein upper metal layer 21 and upper metal layer 22 are stacked and partially overlap. It is worth noting that although two upper metal layers (i.e., upper metal layer 21 and upper metal layer 22) are described here, the present invention is not limited to the number of upper metal layers. If the Woven MOM capacitor 20 includes two or more upper metal layers, it is within the scope of the present invention.

[0028] It is worth noting that the upper metal layer 21 and the upper metal layer 22 are stacked on top of each other and have a portion of their areas overlap. For example, the upper metal layer 22 can be stacked on top of the upper metal layer 21, that is, the upper metal layer 22 and the upper metal layer 21 partially overlap in the Z-axis direction. In Figure 3, to clearly illustrate the schematic features, the upper metal layer 21 is drawn in the middle area, the upper metal layer 22 is drawn in the right area, and the Woven MOM capacitor 20 on the left is a schematic diagram of the upper metal layer 21 and the upper metal layer 22 after being stacked.

[0029] The upper metal layer 21 includes an L-shaped main spindle electrode composed of main spindle electrodes 21A and 21E, and another L-shaped main spindle electrode composed of main spindle electrodes 21B and 21F. Multiple parallel branch electrodes 21C and 21D are connected to the main spindle electrodes 21E and 21F respectively. Main spindle electrodes 21A and 21B are arranged along a first direction (e.g., the X direction), main spindle electrodes 21E and 21F are arranged along a second direction (Y direction), and branch electrodes 21C and 21D are arranged along the first direction (e.g., the X direction). Furthermore, viewed along the Y direction, branch electrodes 21C and 21D are arranged alternately, for example, from top to bottom in the order of branch electrode 21C, branch electrode 21D, branch electrode 21C, branch electrode 21D… The lengths of branch electrodes 21C and 21D in the X direction are preferably the same. The main shaft electrodes 21A, 21B, 21E, 21F and the branch electrodes 21C, 21D are all electrode patterns made of a highly conductive material (e.g., metal). Therefore, the upper metal layer 21 includes the main shaft electrodes 21A, 21B, 21E, 21F and the branch electrodes 21C, 21D made of conductive material, forming an interdigitated electrode pattern. The interdigitated electrode pattern is located in a dielectric layer (not shown), which serves as the conductive layer of the MOM capacitor structure, while the dielectric layer serves as the oxide layer of the MOM capacitor structure.

[0030] In addition, the upper metal layer 21 includes two L-shaped main axis electrodes (i.e., main axis electrodes 21A and 21E constitute one L-shaped main axis electrode, and main axis electrodes 21B and 21F constitute the other L-shaped main axis electrode) which are connected to different polarities. For example, main axis electrode 21E is connected to a high polarity signal, while main axis electrode 21F is connected to a low polarity signal. Therefore, each branch electrode 21C connected to main axis electrode 21E will also maintain high polarity, and conversely, each branch electrode 21D connected to main axis electrode 21F will also maintain low polarity. From the Y direction, each branch electrode 21C and each branch electrode 21D are arranged alternately, so each branch electrode is also arranged in the order of high polarity, low polarity, high polarity, low polarity...

[0031] The upper metal layer 22 has a similar structure to the upper metal layer 21, but it is worth noting that the arrangement direction of the upper metal layer 22 is different from that of the upper metal layer 21. Specifically, the arrangement direction of each branch electrode in the upper metal layer 22 is perpendicular to the arrangement direction of each branch electrode in the upper metal layer 21 in the XY plane. Taking this embodiment as an example, the upper metal layer 22 includes an L-shaped main shaft electrode composed of main shaft electrode 22A and main shaft electrode 22E, and another L-shaped main shaft electrode composed of main shaft electrode 22B and main shaft electrode 22F. Multiple parallel branch electrodes 22C and 22D are respectively connected to main shaft electrode 22E and main shaft electrode 22F. The main shaft electrode 22A and main shaft electrode 22B are arranged along a first direction (e.g., the X direction), the main shaft electrode 22E and main shaft electrode 22F are arranged along a second direction (Y direction), and the branch electrodes 22C and 22D are arranged along the second direction (e.g., the Y direction). Furthermore, viewed along the X direction, branch electrodes 22C and 22D are arranged alternately, for example, from left to right in the order of branch electrode 22D, branch electrode 22C, branch electrode 22D, branch electrode 22C… The lengths of branch electrodes 22C and 22D in the Y direction are preferably the same. The main shaft electrodes 22A, 22B, 22E, 22F and branch electrodes 22C, 22D are all electrode patterns made of a highly conductive material (e.g., metal). Therefore, the upper metal layer 22 contains the main shaft electrodes 22A, 22B, 22E, 22F and branch electrodes 22C, 22D made of conductive material, forming an interdigitated electrode pattern. The interdigitated electrode pattern is located in a dielectric layer (not shown), which serves as the conductive layer of the MOM capacitor structure, while the dielectric layer serves as the oxide layer of the MOM capacitor structure.

[0032] In addition, the upper metal layer 22 includes two L-shaped main spindle electrodes (i.e., main spindle electrodes 22A and 22E constitute one L-shaped main spindle electrode, and main spindle electrodes 22B and 22F constitute the other L-shaped main spindle electrode) which are connected to different polarities. For example, main spindle electrode 22A is connected to a high polarity signal, while main spindle electrode 22B is connected to a low polarity signal. Therefore, each branch electrode 22C connected to main spindle electrode 22A will also maintain high polarity, and conversely, each branch electrode 22D connected to main spindle electrode 22B will also maintain low polarity. From the X direction, each branch electrode 22C and each branch electrode 22D are arranged alternately, so each branch electrode is also arranged in the order of low polarity, high polarity, low polarity, high polarity...

[0033] Referring also to Figure 4, for any branch electrode (21C, 21D or 22C, 22D) included in the upper metal layer 21 and the lower gold metal layer 22, the adjacent branch electrodes in the XY plane have opposite polarities to themselves. In other words, if a branch electrode 21C with high polarity is selected, then the adjacent branch electrode 21D in the XY plane is low polarity. On the other hand, if a branch electrode 21D with low polarity is selected, then the adjacent branch electrode 21C in the XY plane is high polarity. In addition, as mentioned above, the arrangement direction of branch electrodes 21C / 21D is perpendicular to the arrangement direction of branch electrodes 22C / 22D. For clarity, different backgrounds are used in Figure 4 to represent high polarity and low polarity respectively. Additionally, Figure 4 shows two more upper metal layers 23 and 24 stacked above upper metal layer 22, indicating that the Woven MOM capacitor 20 can contain more upper electrode layers besides upper metal layers 21 and 22. The pattern features of upper metal layers 23 and 24 are similar to those of upper metal layers 21 and 22, respectively, so their detailed features will not be repeated here.

[0034] In addition, the Woven MOM capacitor 20 may also include multiple contact plugs V2, which are used to connect different metal electrode layers with the same polarity (e.g., both high polarity or both low polarity). Therefore, the signal output from the signal source can be transmitted to each metal electrode layer. In this embodiment, because the spindle electrode has a large linewidth, each contact plug V2 overlaps with each spindle electrode 21A / 21B / 21E / 21F / 22A / 22B / 22E / 22F. This makes it easy for the contact plugs V2 to align with each spindle electrode 21A / 21B / 21E / 21F / 22A / 22B / 22E / 22F without misalignment. However, the invention is not limited to this; in other embodiments of the invention, the position of the contact plugs V2 can be adjusted as needed. In addition, since each spindle electrode is L-shaped, even if the arrangement directions of adjacent upper metal layers are perpendicular to each other, the contact plug V2 can still connect different upper metal layers in the Z direction.

[0035] In addition, it is worth noting that the Woven MOM capacitor 20 is stacked on top of the APMOM capacitor 10, and the linewidth and spacing between the branch electrodes of the Woven MOM capacitor 20 may be more spacious than those of the APMOM capacitor 10. This is because in semiconductor manufacturing, the layers closer to the substrate (i.e., where the APMOM capacitor 10 is located) may form more high-density electronic components (such as transistors), while the upper layers farther from the substrate (i.e., where the Woven MOM capacitor 20 is located) are mainly used to form connecting elements such as wires. Therefore, the component density in the upper layers is usually lower, allowing for more spacious linewidths and spacing. In this embodiment, for example, the linewidth (or spacing between branch electrodes) of the Woven MOM capacitor 20 is approximately 1.25 times that of the APMOM capacitor 10, but the invention is not limited to this. If the minimum linewidth of the APMOM capacitor 10 is 36 nanometers, then the minimum linewidth of the Woven MOM capacitor 20 is approximately 45 nanometers. Furthermore, since the minimum linewidth of the Woven MOM capacitor 20 is relatively large, each upper metal layer in the Woven MOM capacitor 20 can be manufactured by a single exposure and development process, without the need to manufacture the lower metal layer by a two-exposure and development process, thus saving process steps.

[0036] As shown in Figures 3 and 4, the Woven MOM capacitor 20 is characterized by the adjacent upper metal layers being arranged in a vertical direction. Specifically, the arrangement direction of the branch electrodes 21C / 21D of the upper metal layer 21 is perpendicular to the arrangement direction of the branch electrodes 22C / 22D of the upper metal layer 22. Under this arrangement, although the overlap area between the upper metal layers is not as large as the overlap area between the lower metal layers of the aforementioned APMOM capacitor 10, the routing direction of the upper metal layers is more flexible, thus making it suitable for formation in upper structures dominated by conductive wire structures.

[0037] Figure 5 shows a top view of a composite capacitor according to an embodiment of the present invention, and Figure 6 shows a schematic diagram of the arrangement structure of the composite capacitor in Figure 5. As shown in Figures 5 and 6, the composite capacitor 30 of the present invention includes a lower APMOM capacitor 10 and a Woven MOM capacitor 20 stacked on top, wherein the APMOM capacitor 10 and the Woven MOM capacitor 20 are interconnected by a contact plug or similar structure. The features of the APMOM capacitor 10 and the Woven MOM capacitor 20 have been described in the above paragraphs, and therefore will not be repeated here. In addition, in this embodiment, the arrangement direction of the branch electrodes of the bottommost layer of the Woven MOM capacitor 20 (i.e., the upper metal layer closest to the APMOM capacitor 10) is perpendicular to the arrangement direction of the branch electrodes of the APMOM capacitor 10.

[0038] It is worth noting that in this embodiment, the Woven MOM capacitor 20 is stacked on top of the APMOM capacitor 10, and the two are preferably electrically connected by contact plugs to transmit high-polarity or low-polarity signals emitted by the signal source to the electrodes. As mentioned in the preceding paragraph, the advantage of the APMOM capacitor 10 is that it has a higher overlap area, resulting in a higher unit capacitance, while the advantage of the Woven MOM capacitor 20 is that it has higher routing flexibility and fewer process steps. Therefore, the composite capacitor 30 of the present invention combines the APMOM capacitor 10 and the Woven MOM capacitor 20. According to the applicant's experimental results, compared with embodiments that use only Woven MOM capacitors as capacitors in the semiconductor structure, the capacitance value of the composite capacitor 30 of the present invention is increased by approximately 2% to 8%. Therefore, the capacitance value of the MOM capacitor is improved while remaining compatible with the prior art.

[0039] Figure 7 illustrates a top view of a composite capacitor according to another embodiment of the present invention, and Figure 8 illustrates a schematic diagram of the arrangement structure of the composite capacitor in Figure 7. As shown in Figures 7 and 8, in another embodiment of the present invention, the composite capacitor 30' can be formed by stacking an APMOM capacitor 10' and a Woven MOM capacitor 20. The features of the Woven MOM capacitor 20 have been described in the above paragraphs. The difference between the APMOM capacitor 10' and the aforementioned APMOM capacitor 10 is that its area is smaller; the other features are the same and will not be repeated here. The main difference between this embodiment and the above embodiment is that the area of ​​the APMOM capacitor 10' is smaller than the area of ​​the Woven MOM capacitor 20. As shown in Figure 8, an electronic component 40 (such as a transistor, but not limited to) occupies a portion of the substrate area. The remaining area on the substrate can then be used to form the APMOM capacitor 10', and then the Woven MOM capacitor 20 is formed and stacked on top of the APMOM capacitor 10' and the electronic component 40. In this embodiment, the remaining area on the substrate can be fully utilized to form an APMOM capacitor 10' in the area not occupied by the electronic component 40, thus saving process space and achieving the goal of component miniaturization.

[0040] According to the above description and figures, the present invention provides a capacitor structure 30, comprising a first capacitor structure (APMOM capacitor 10) located on a substrate, wherein the first capacitor structure 10 is a metal-oxide-metal (MOM) capacitor structure, comprising multiple layers of lower electrode layers 11 / 12, wherein each lower electrode layer 11 / 12 is arranged in the same direction and stacked on top of each other along a height direction (Z direction), and a second capacitor structure (Woven The second capacitor structure 20 is a metal-oxide-metal (MOM) capacitor structure, which includes multiple upper electrode layers 21 / 22. A portion of the upper electrode layers 21 / 22 (e.g., upper electrode layer 21) are arranged in a first direction (X direction), and another portion of the upper electrode layers (e.g., upper electrode layer 22) are arranged in a second direction (Y direction). The first direction and the second direction are perpendicular to each other, and the upper electrode layers 21 arranged in the first direction (X direction) and the upper electrode layers 22 arranged in the second direction (Y direction) are stacked alternately along the height direction (Z direction).

[0041] In some embodiments of the present invention, each lower electrode layer 11 / 12 includes two first comb patterns (e.g., 11A / 11B or 12A / 12B), wherein each first comb pattern includes a main axis electrode 11A with a plurality of branch electrodes 11C, and each branch electrode 11C is arranged along a second direction (Y direction).

[0042] In some embodiments of the present invention, in the two first comb-shaped patterns included in the lower electrode layer, the main spindle electrode 11A is arranged along a first direction (X direction) and the main spindle electrode 11A presents an elongated pattern.

[0043] In some embodiments of the present invention, the branch electrodes 11C / 11D of the two first comb patterns included in the lower electrode layer 11 are arranged alternately to form an interdigital electrode pattern.

[0044] In some embodiments of the present invention, among the multiple upper electrode layers 21 / 22 included in the second capacitor structure 20, the upper electrode layer 21 closest to the first capacitor structure 10 is defined as a junction electrode layer (i.e., upper electrode layer 21), wherein the junction electrode layer includes a plurality of branch electrodes 21C / 21D, and each branch electrode 21C / 21D is arranged along a first direction (X direction).

[0045] In some embodiments of the present invention, the interface electrode layer includes two second comb patterns, each second comb pattern including a main axis electrode (e.g., 21A and 21E) and a plurality of branch electrodes 21C, wherein the main axis electrode presents an L-shaped pattern.

[0046] In some embodiments of the present invention, the plurality of lower electrode layers 10 have the same first linewidth, and the plurality of upper electrode layers 20 include the same second linewidth.

[0047] In some embodiments of the present invention, the first line width is smaller than the second line width. For example, the second line width is 1.25 times the first line width, but is not limited thereto.

[0048] In some embodiments of the present invention, the area of ​​the first capacitor structure 10 is smaller than the area of ​​the second capacitor structure 20 when viewed from a top view (see Figure 7).

[0049] In some embodiments of the present invention, an electronic component 40 is located on a substrate and adjacent to a first capacitor structure 10, wherein the electronic component 40 is covered by a second capacitor structure 20.

[0050] The present invention further provides a method for fabricating a capacitor structure, comprising forming a first capacitor structure (APMOM capacitor 10) located on a substrate, wherein the first capacitor structure 10 is a metal-oxide-metal (MOM) capacitor structure, comprising multiple layers of lower electrode layers 11 / 12, wherein each lower electrode layer 11 / 12 is arranged in the same direction and stacked on top of each other along a height direction (Z direction), and forming a second capacitor structure (Woven The second capacitor structure 20 is a metal-oxide-metal (MOM) capacitor structure, which includes multiple upper electrode layers 21 / 22. A portion of the upper electrode layers 21 / 22 (e.g., upper electrode layer 21) are arranged in a first direction (X direction), and another portion of the upper electrode layers (e.g., upper electrode layer 22) are arranged in a second direction (Y direction). The first direction and the second direction are perpendicular to each other, and the upper electrode layers 21 arranged in the first direction (X direction) and the upper electrode layers 22 arranged in the second direction (Y direction) are stacked alternately along the height direction (Z direction).

[0051] In summary, the present invention is characterized by providing a composite capacitor structure, which is composed of a lower alternating polarity MOM capacitor (APMOM capacitor) and an upper braided MOM capacitor (Woven MOM capacitor). The APMOM capacitor has a higher overlap area and capacitance value, while the Woven MOM capacitor offers more flexible routing and simpler manufacturing steps. Therefore, the composite capacitor of the present invention combines these two types of MOM capacitors, thus obtaining the advantages of both. Specifically, the APMOM capacitor can be used in the lower layer structure of the semiconductor device to increase the capacitance value, while the Woven MOM capacitor in the upper layer structure offers advantages such as more flexible routing direction and reduced manufacturing difficulty. Therefore, the composite capacitor structure of the present invention has advantages such as higher capacitance value, lower manufacturing difficulty, and compatibility with existing technologies. The above description is only a preferred embodiment of the present invention, and all equivalent variations and modifications made within the scope of the claims of the present invention should be considered within the scope of the present invention. [Simplified Explanation of the Diagram]

[0052] To make the following text easier to understand, reference can be made to the drawings and detailed textual descriptions while reading this invention. The specific embodiments of the invention are explained in detail through the specific embodiments described herein and with reference to the corresponding drawings, which serve to illustrate the working principle of the specific embodiments of the invention. Furthermore, for clarity, the features in the drawings may not be drawn to scale, and therefore the dimensions of some features in certain drawings may be intentionally enlarged or reduced. Figure 1 shows a top view overlay of an alternating polarity MOM (APMOM) capacitor in the composite capacitor of the present invention. Figure 2 shows a schematic diagram of the arrangement structure of the alternating polarity MOM (APMOM) capacitor in Figure 1. Figure 3 shows a top view overlay of a braided MOM (Woven MOM) capacitor in the composite capacitor of the present invention. Figure 4 shows a schematic diagram of the arrangement structure of the braided MOM (Woven MOM) capacitor in Figure 3. Figure 5 shows a top view overlay of a composite capacitor according to an embodiment of the present invention. Figure 6 shows a schematic diagram of the arrangement structure of the composite capacitor in Figure 5. Figure 7 illustrates an overlaid top view of a composite capacitor according to another embodiment of the present invention. Figure 8 illustrates a schematic diagram of the arrangement structure of the composite capacitor in Figure 7.

Claims

1. A capacitor structure comprising: a first capacitor structure located on a substrate, wherein the first capacitor structure is a metal-oxide-metal (MOM) capacitor structure comprising multiple lower electrode layers, wherein each lower electrode layer is arranged facing the same direction and stacked together along a height direction (Z direction); and a second capacitor structure located on the first capacitor structure, wherein the second capacitor structure is a metal-oxide-metal (MOM) capacitor structure comprising multiple upper electrode layers, wherein a portion of the multiple upper electrode layers is arranged facing a first direction (X direction), and another portion of the upper electrode layers is arranged facing a second direction (Z direction). The first capacitor structure is arranged in the Y direction, and the first direction is perpendicular to the second direction. The upper electrode layer arranged in the first direction (X direction) and the upper electrode layer arranged in the second direction (Y direction) are stacked alternately along the height direction (Z direction). From a top view, the area of ​​the first capacitor structure is smaller than the area of ​​the second capacitor structure. The first capacitor structure includes an electronic component located on the substrate and next to the first capacitor structure. The electronic component is covered by the second capacitor structure and overlaps with each other in the height direction. The electronic component is aligned with the first capacitor structure in the first direction or the second direction.

2. The capacitor structure according to claim 1, wherein each of the underlying electrode layers includes two first comb patterns, wherein each of the first comb patterns includes a main axis electrode and a plurality of branch electrodes, and each of the branch electrodes is arranged along the second direction (Y direction).

3. The capacitor structure according to claim 2, wherein in the two first comb-shaped patterns included in the lower electrode layer, the main axis electrode is arranged along the first direction (X direction), and the main axis electrode presents an elongated pattern.

4. The capacitor structure according to claim 2, wherein the branch electrodes of the two first comb patterns included in the lower electrode layer are arranged alternately to form an interdigital electrode pattern.

5. The capacitor structure according to claim 2, wherein the upper electrode layer closest to the first capacitor structure among the multiple upper electrode layers included in the second capacitor structure is defined as a junction electrode layer, wherein the junction electrode layer includes a plurality of branch electrodes, and each of the branch electrodes is arranged along the first direction (X direction).

6. The capacitor structure according to claim 5, wherein the junction electrode layer includes two second comb patterns, each of the second comb patterns including a main axis electrode and a plurality of the branch electrodes, wherein the main axis electrode presents an L-shaped pattern.

7. The capacitor structure according to claim 1, wherein the plurality of lower electrode layers have the same first linewidth and the plurality of upper electrode layers include the same second linewidth.

8. The capacitor structure according to claim 7, wherein the first linewidth is smaller than the second linewidth.

9. A method for fabricating a capacitor structure, comprising: forming a first capacitor structure on a substrate, wherein the first capacitor structure is a metal-oxide-metal (MOM) capacitor structure comprising multiple layers of bottom electrode layers, wherein each bottom electrode layer is arranged in the same direction and stacked on top of each other along a height direction (Z direction); and forming a second capacitor structure on the first capacitor structure, wherein the second capacitor structure is a metal-oxide-metal (MOM) capacitor structure comprising multiple layers of top electrode layers, wherein a portion of the multiple top electrode layers is arranged in a first direction (X direction), and another portion of the top electrode layers is arranged in a second direction. The first capacitor structure is arranged in a direction (Y direction), which is perpendicular to the second direction. The upper electrode layers arranged in the first direction (X direction) and the upper electrode layers arranged in the second direction (Y direction) are stacked alternately along the height direction (Z direction). From a top view, the area of ​​the first capacitor structure is smaller than the area of ​​the second capacitor structure. The first capacitor structure includes an electronic component located on the substrate and next to the first capacitor structure. The electronic component is covered by the second capacitor structure and overlaps with each other in the height direction. The electronic component is aligned with the first capacitor structure in the first direction or the second direction.

10. A method for manufacturing a capacitor structure according to claim 9, wherein each of the underlying electrode layers comprises two first comb patterns, wherein each of the first comb patterns comprises a main axis electrode and a plurality of branch electrodes, and each of the branch electrodes is arranged along the second direction (Y direction).

11. The method for manufacturing a capacitor structure according to claim 10, wherein in the two first comb-shaped patterns included in the lower electrode layer, the main axis electrode is arranged along the first direction (X direction), and the main axis electrode presents an elongated pattern.

12. The method for manufacturing a capacitor structure according to claim 10, wherein the branch electrodes in the two first comb patterns included in the lower electrode layer are arranged alternately to form an interdigital electrode pattern.

13. The method for manufacturing a capacitor structure according to claim 10, wherein the upper electrode layer closest to the first capacitor structure among the multiple upper electrode layers included in the second capacitor structure is defined as a junction electrode layer, wherein the junction electrode layer includes a plurality of branch electrodes, and each of the branch electrodes is arranged along the first direction (X direction).

14. The method for manufacturing a capacitor structure according to claim 13, wherein the junction electrode layer includes two second comb-shaped patterns, each of the second comb-shaped patterns including a main axis electrode and a plurality of the branch electrodes, wherein the main axis electrode presents an L-shaped pattern.

15. The method for manufacturing a capacitor structure according to claim 9, wherein the plurality of lower electrode layers have the same first linewidth, and the plurality of upper electrode layers include the same second linewidth.

16. The method for manufacturing a capacitor structure according to claim 15, wherein the first linewidth is smaller than the second linewidth.

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