Chiplet pairing to reduce power variation

Abstract

The disclosed techniques provide a method for creating a system-on-chip (SoC) integrated circuit (IC). The method includes, for each chiplet, determining a tested leakage power consumption of cores on the chiplet. The pre-binning also includes categorizing the chiplets into categories. The categories are based on the tested leakage power consumption of the chiplets. The categories include a first category and a second category, such that each chiplet that is categorized in the first category has a tested leakage power consumption that is less than a nominal leakage power consumption, and such that each chiplet that is categorized in the second category has a tested leakage power consumption that is greater than the nominal leakage power consumption. The method also includes creating the SoC IC such that the SoC IC includes at least one chiplet from the first category and at least one chiplet from the second category.

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