Semiconductor structure and manufacturing method thereof

Abstract

A first mask is formed on the substrate. A first implantation process is performed using a first mask to form a first implantation area in the substrate. A first spacer and a second spacer are formed on the side wall of the first mask. A first wet etching process is performed to remove the first spacer. A second wet etching process is performed to remove a portion of the first mask. A second implantation process is performed using the first mask and the second spacer to form a second implantation area in the substrate, and the second implantation area is self-aligned with the first implantation area. A third wet etching process is performed to remove the second spacer. A fourth wet etching process is performed to remove a portion of the first mask. A third implantation process is performed using the first mask to form a first well area in the substrate, and the first well area is self-aligned with the second implantation area.

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor structure and a method for manufacturing the same. [Previous Technology]

[0002] With the rapid development of power electronics technologies such as solar energy, automotive electronics, and high-frequency, high-power-density power modules in recent years, higher requirements have been placed on the power density of power electronic devices. As the complexity of transistor components increases, exposure errors are more likely to occur during the definition of component structures, thereby reducing quality. [Summary of the Invention]

[0003] According to some embodiments disclosed herein, a method for manufacturing a semiconductor structure is provided. The method includes the following steps: providing a substrate and forming a first mask on the substrate. Performing a first implantation process with the first mask to form a first implantation region in the substrate. Forming a first spacer on a sidewall of the first mask and forming a second spacer on a sidewall of the first spacer to cover the first implantation region, wherein the first mask, the first spacer, and the second spacer are formed of different materials. Removing the first spacer. Removing a first portion of the first mask. Performing a second implantation process with the first mask and the second spacer to form a second implantation region in the substrate, such that the second implantation region is self-aligned with the first implantation region. Removing the second spacer. Removing a second portion of the first mask, wherein a fourth etchant is the same as the second etchant. Performing a third implantation process with the first mask to form a first well region in the substrate, such that the first well region is self-aligned with the second implantation region.

[0004] In some embodiments, a first wet etching process is performed using a first etchant to remove a first spacer, wherein the first spacer comprises polycrystalline silicon and the first etchant comprises tetramethylammonium hydroxide; a second wet etching process is performed using a second etchant to remove a first portion of a first mask, wherein the first mask comprises silicon nitride and the second etchant comprises phosphoric acid; a third wet etching process is performed using a third etchant to remove a second spacer, wherein the second spacer comprises silicon oxide and the third etchant comprises hydrofluoric acid and ammonium fluoride; and a fourth wet etching process is performed using a fourth etchant to remove a second portion of the first mask, wherein the fourth etchant comprises phosphoric acid.

[0005] In some embodiments, the substrate has a heavily doped layer, a lightly doped layer above the heavily doped layer, and a current dispersing layer within the lightly doped layer, and a first mask covers the lightly doped layer.

[0006] In some embodiments, after performing a second wet etching process using a second etchant, the first mask and the second spacer together expose a portion of the first implantation region and a portion of the lightly doped layer adjacent to the first implantation region.

[0007] In some embodiments, after a fourth wet etching process is performed using a second etchant, the first mask exposes the first implantation region, the second implantation region, and a portion of the lightly doped layer adjacent to the second implantation region.

[0008] In some embodiments, the method further includes: after forming the first well region, removing the first mask and forming a second mask to cover the first implantation region, the second implantation region and the first well region, and exposing the lightly doped layer.

[0009] In some embodiments, the method further includes: performing a fourth implantation process with a second mask to form a transistor in a lightly doped layer of a substrate, performing a thermal annealing process to form a gate oxide layer on the substrate, and forming a gate on the gate oxide layer.

[0010] According to some aspects of this disclosure, a method for manufacturing a semiconductor structure is provided. The method includes the following steps: providing a substrate and forming a first mask on the substrate. Performing a first implantation process with the first mask to form a first implantation region in the substrate. Forming a first spacer and a second spacer on the sidewalls of the first mask, wherein the first spacer is located between the first mask and the second spacer, and the first spacer and the second spacer cover the first implantation region, wherein the first mask, the first spacer, and the second spacer are formed of different materials. Removing the first spacer to form a first opening, wherein the sidewalls of the first implantation region are aligned with the first sidewalls of the first opening. Removing a first portion of the first mask to enlarge the first opening into a second opening. Performing a second implantation process with the first mask and the second spacer to form a second implantation region in the substrate, wherein the sidewalls of the second implantation region are aligned with the second sidewalls of the second opening. Removing the second spacer to enlarge the second opening into a third opening, wherein the sidewalls of the second implantation region are aligned with the third sidewalls of the third opening. Removing a second portion of the first mask to enlarge the third opening into a fourth opening. A third implantation process is performed using a first mask to form a first well region in the substrate, wherein the sidewall of the first well region is aligned with the fourth sidewall of the fourth opening.

[0011] In some embodiments, the substrate and the first implantation process include different types of dopants.

[0012] In some embodiments, the first implantation process and the second implantation process include different types of dopants.

[0013] In some embodiments, the first implantation process and the third implantation process include the same type of dopant.

[0014] In some embodiments, the first mask has a first thickness before the first fabrication process is performed, and the first thickness is greater than 5 micrometers.

[0015] According to some aspects disclosed herein, a semiconductor structure is provided. The semiconductor structure includes a substrate, a transistor, a first well region, a first implantation region, and a second implantation region. The substrate includes a current dispersing layer. The transistor is located on the current dispersing layer and has a first sidewall and a second sidewall. The first well region is located on the current dispersing layer and is in contact with the first sidewall and the second sidewall of the transistor, respectively, wherein the bottom surface of the first well region is lower than the top surface of the current dispersing layer. The first implantation region is located in the first well region. The second implantation region is located in the first well region and is located between the first implantation region and the transistor. The second implantation region has a first sidewall and a second sidewall, wherein there is a first distance between the first sidewall of the second implantation region and the first sidewall of the transistor, and there is a second distance between the second sidewall of the second implantation region and the second sidewall of the transistor, and the first distance and the second distance are equal.

[0016] In some embodiments, the substrate further includes a heavily doped layer and a lightly doped layer. The heavily doped layer is located below the current dispersing layer. The lightly doped layer is located between the current dispersing layer and the heavily doped layer.

[0017] In some embodiments, the semiconductor structure further includes a gate and a gate oxide layer. The gate is located above the transistor. The gate oxide layer is located between the transistor and the gate.

[0018] In some embodiments, the bottom surface of the first implantation area and the bottom surface of the second implantation area are higher than the bottom surface of the first well area.

[0019] In some embodiments, the top surface of the first implantation area, the top surface of the second implantation area, and the top surface of the first well area are coplanar.

Implementation Method

[0020] Reference will now be made in detail to embodiments disclosed herein, examples of which are shown in the drawings. Where possible, the same reference numerals are used in the drawings and description to refer to the same or similar parts.

[0021] It should be understood that the following disclosure provides many different embodiments or examples for implementing different features of this disclosure. Specific embodiments or examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or above a second feature in the following description may include embodiments where the first and second features are formed in direct contact, or embodiments where an additional feature is formed between the first and second features such that the first and second features may not be in direct contact. Additionally, reference numerals and / or symbols may be repeated in various examples in this disclosure. Such repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0022] Furthermore, for ease of description, this disclosure may use spatially relative terms, such as "below," "under," "lower," "above," "upper," etc., to describe the relationship of an element or feature to one or more other elements or features, as shown in the accompanying drawings. The spatially relative terms are intended to cover not only the orientation illustrated in the drawings but also different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly.

[0023] Figures 1 through 15 are schematic cross-sectional views of various intermediate stages in the formation of a semiconductor structure 100 according to some embodiments. The semiconductor structure 100 can be applied to an integrated circuit (IC) or a portion thereof, such as a logic circuit, resistor, capacitor, sensor, or storage device. It should be understood that, for the sake of simplicity, some components of the semiconductor structure 100 are not shown in Figures 1 through 15, and other embodiments of the semiconductor structure 100 may include additional components.

[0024] First, referring to Figure 1, a semiconductor structure 100 is provided. The semiconductor structure 100 includes a substrate 110 and a first mask 120 disposed on the substrate 110. The substrate 110 includes a heavily doped layer 112, a lightly doped layer 114, and a current dispersing layer 116. The substrate 110 can be a semiconductor substrate, such as a silicon carbide (SiC) substrate. Since silicon carbide is a wide bandgap semiconductor material, it has a wide bandgap characteristic, thus exhibiting a higher breakdown electric field and lower leakage current. Furthermore, because silicon carbide has better thermal conductivity than silicon, it is very suitable for environments requiring operation at high temperatures, such as automotive transistors.

[0025] In some embodiments, the heavily doped layer 112 and the lightly doped layer 114 have the same first dopant type. For example, the heavily doped layer 112 and the lightly doped layer 114 have N-type doping. Alternatively, the heavily doped layer 112 and the lightly doped layer 114 have P-type doping. In some embodiments, the substrate 110 includes an N-type heavily doped layer 112 and an N-type lightly doped layer 114 epitaxially grown on the N-type heavily doped layer 112. In other embodiments, the N-type heavily doped layer 112 and the N-type lightly doped layer 114 may also be formed by ion implantation. Next, a current dispersing layer 116 is formed in the lightly doped layer 114 by ion implantation. The current dispersing layer 116 is entirely located in the lightly doped layer 114; in other words, a portion of the lightly doped layer 114 is located above the current dispersing layer 116.

[0026] Next, a first mask 120 is formed over the substrate 110, exposing a portion of the substrate 110. In some embodiments, the first mask 120 may be silicon nitride (SiN). In some embodiments, the first mask 120 may be formed using a suitable deposition process, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc. In some embodiments, the first mask 120 has a first thickness T1. For good thickness uniformity and sufficient shielding, the first thickness T1 is at least 5 micrometers. As shown, the first mask 120 has a first width W1.

[0027] Referring to Figure 2, a first implantation process is performed to form a first implantation region 130 in a lightly doped layer 114 of a substrate 110 through the pattern of a first mask 120. The first implantation region 130 is formed in the lightly doped layer 114 of the substrate 110 exposed by the first mask 120. The bottom surface of the first implantation region 130 lies in the lightly doped layer 114 and does not contact the current dispersing layer 116. In some embodiments, the first implantation region 130 has a second dopant type, wherein the second dopant type is different from the first dopant type. For example, when the lightly doped layer 114 has N-type doping, the first implantation region 130 has P-type doping. For example, when the lightly doped layer 114 has P-type doping, the first implantation region 130 has N-type doping. In some embodiments, the first implantation region 130 may be a P+ region.

[0028] Referring to Figure 3, a first spacer 122 is formed on the sidewall of the first mask 120. The first spacer 122 covers a portion of the top surface of the first implantation region 130. In some embodiments, the first spacer 122 may be polycrystalline silicon. In some embodiments, the first spacer 122 may be formed using a suitable deposition process, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc.

[0029] Referring to Figure 4, a second spacer 124 is formed on the sidewall of the first spacer 122. The second spacer 124 completely covers the top surface of the first implantation region 130. In some embodiments, the second spacer 124 may be an oxide, such as silicon oxide (SiO2). In some embodiments, the materials forming the first spacer 122 and the second spacer 124 may be interchanged. In some embodiments, after the second spacer 124 is formed, a planarization process may be performed on the first mask 120, the first spacer 122, and the second spacer 124.

[0030] Referring to Figure 5, a first wet etching process (or an isotropic etching process) is performed using a first etchant to remove the first spacer 122 and expose a portion of the top surface of the first implantation region 130. After removing the first spacer 122, a first opening O1 is formed. As shown, the first sidewall S1 of the first opening O1 is aligned with the sidewall 130S of the first implantation region 130. In some embodiments, when the material of the first spacer 122 is polycrystalline silicon, the first etchant includes tetramethylammonium hydroxide (TMAH). In some embodiments, the first wet etching process is performed at a first temperature, which is in the temperature range of 60°C to 80°C. The first etchant has an etching rate of 50 to 400 nm per minute on the first spacer 122. Since the first mask 120, the first spacer 122, and the second spacer 124 are all formed of different materials, any etchant with a faster etching rate on the first spacer 122 can be selected to remove the first spacer 122. Removing the first spacer 122 provides etching gaps for subsequent wet etching processes.

[0031] Referring to Figure 6, a second wet etching process (or an isotropic etching process) is performed with a second etchant to remove a first portion of the first mask 120, wherein the second etchant is different from the first etchant. After performing the second wet etching process, the first opening O1 is enlarged to a second opening O2. After the second wet etching process, the first mask 120 has a second thickness T2 and a second width W2. The second thickness T2 is less than the first thickness T1, and the second width W2 is less than the first width W1. In some embodiments, the second etchant comprises phosphoric acid (H3PO4). In some embodiments, the second wet etching process is performed at a second temperature, which is between 150°C and 180°C. The first temperature is higher than the second temperature. The second etchant has a slower etching rate of 20 to 50 nm per minute on the first mask 120, thus allowing for precise control of the etching condition of the first mask 120.

[0032] Referring to Figure 7, a second implantation process is performed to form a second implantation region 132 in the substrate 110 through the first mask 120 and the second spacer 124. By removing a portion of the first mask 120, the second implantation region 132 is self-aligned with the first implantation region 130. As shown, the second sidewall S2 of the second opening O2 is aligned with the sidewall 132S of the second implantation region 132. In other words, the difference between the first width W1 and the second width W2 of the first mask 120 is approximately equal to the width of the second implantation region 132. The second implantation region 132 is formed in the lightly doped layer 114 of the substrate 110 exposed by the first mask 120 and the second spacer 124. The bottom surface of the second implantation region 132 is located in the lightly doped layer 114 and does not contact the current dispersing layer 116. In some embodiments, the second implantation region 132 has a first dopant type. In some embodiments, the second implantation region 132 may be an N+ region.

[0033] Referring to Figure 8, a third wet etching process is performed using a third etchant to remove the second spacer 124. After the second spacer 124 is removed, the top surface of the first implantation region 130 is exposed. As shown, the second opening O2 expands into a third opening O3, and the third opening O3 near the third sidewall S3 of the first mask 120 remains aligned with the sidewall 132S of the second implantation region 132. In some embodiments, when the second spacer 124 is silicon oxide, the third etchant is a buffered oxide etchant (BOE), which includes hydrogen fluoride (HF) and ammonium fluoride (NH4F). In some embodiments, the third wet etching process is performed at a third temperature of approximately 25°C. The third etchant has an etching rate of 20 to 50 nm per minute on the second spacer 124.

[0034] In some embodiments, when the materials of the first spacer 122 and the second spacer 124 are exchanged, the etching environments used are also exchanged. Specifically, when the first spacer 122 is silicon oxide, the first etchant is a buffered oxide layer etchant, and the first temperature is about 25°C. When the second spacer 124 is polycrystalline silicon, the third etchant is tetramethylammonium hydroxide, and the third temperature is between 60°C and 80°C.

[0035] Referring to Figure 9, a fourth wet etching process is performed with a fourth etchant to remove a second portion of the first mask 120 and expose a portion of the top surface of the lightly doped layer 114 of the substrate 110. As shown, the third opening O3 expands into a fourth opening O4. At this time, the first mask 120 has a third thickness T3 and a third width W3. The third thickness T3 is less than the second thickness T2, and the third width W3 is less than the second width W2. In some embodiments, the fourth etchant is the same as the second etchant. In some embodiments, the fourth wet etching process is performed in the same etching environment as the second wet etching process. In some embodiments, the fourth etchant comprises phosphoric acid (H3PO4). In some embodiments, the fourth wet etching process is performed at a temperature range of 150°C to 180°C. The fourth etchant has a relatively slow etching rate of 20 to 50 nm per minute on the first mask 120.

[0036] Referring to Figure 10, a third implantation process is performed, forming a first well region 134 in the substrate 110 through a first mask 120. By removing a portion of the first mask 120, the first well region 134 is self-aligned with the second implantation region 132. As shown, the fourth sidewall S4 of the fourth opening O4 is aligned with the sidewall 134S of the first well region 134. In other words, the difference between the second width W2 and the third width W3 of the first mask 120 is approximately equal to the width of the first well region 134 at the top surface of the substrate 110. The first well region 134 is formed in the lightly doped layer 114 and the current dispersing layer 116 of the substrate 110. That is, the bottom surface of the first well region 134 is located in the current dispersing layer 116. In some embodiments, the first well region 134 has a second dopant type. In some embodiments, the first well region 134 is a p-well. By precisely removing the first mask 120 in stages through wet etching, two self-aligned ion implantations can be performed with one mask, simplifying the mask formation process and reducing ion implantation errors caused by mask offset.

[0037] Referring to Figure 11, the first mask 120 is removed, exposing the top surface of the substrate 110. Specifically, the top surfaces of the lightly doped layer 114, the first implantation region 130, the second implantation region 132, and the first well region 134 are exposed. The first mask 120 can be removed using a suitable etching process. Referring to Figure 12, a second mask 140 is formed, exposing the top surface of the lightly doped layer 114 of the substrate 110. Specifically, the second mask 140 covers the top surfaces of the first implantation region 130, the second implantation region 132, and the first well region 134, and the fifth opening O5 of the second mask 140 exposes the top surface of the lightly doped layer 114. Next, a fourth implantation process is performed on the lightly doped layer 114 to form a transistor 150. In some embodiments, the transistor 150 may be a junction field effect transistor (JFET). In some embodiments, the transistor 150 has a first dopant type. In some embodiments, the fifth sidewall S5 of the fifth opening O5 is aligned with the sidewall 150S of the transistor 150. In some embodiments, the width of the transistor 150 is a third width W3. Specifically, the width of the transistor 150 is the same as the width of the first mask 120 after performing the second wet etching process.

[0038] Referring to Figure 13, the second mask 140 is removed, exposing the top surface of the substrate 110. The second mask 140 can be removed using a suitable etching process. Referring to Figure 14, a high-temperature annealing process is performed on the top surface of the substrate 110 to form a gate oxide layer 160. In some embodiments, the gate oxide layer 160 can be formed using a suitable deposition process. Referring to Figure 15, a gate 170 is formed on the gate oxide layer 160, and a back-end process element 180 is formed on the gate 170.

[0039] As shown in Figure 15, the semiconductor structure 100 includes a substrate 110, a first implantation region 130, a second implantation region 132, and a first well region 134. The substrate 110 includes a heavily doped layer 112, a lightly doped layer 114, and a current dispersing layer 116. The lightly doped layer 114 is located between the heavily doped layer 112 and the current dispersing layer 116. The first implantation region 130, the second implantation region 132, and the first well region 134 are located on the current dispersing layer 116, and the first implantation region 130 and the second implantation region 132 are located in the first well region 134. The bottom surface 134B of the first well region 134 is lower than the top surface 116T of the current dispersing layer 116. The bottom surface 130B of the first implantation region 130 and the bottom surface 132B of the second implantation region 132 are coplanar. The bottom surface 130B of the first implantation region 130 and the bottom surface 132B of the second implantation region 132 are higher than the bottom surface 134B of the first well region 134. The top surface 130T of the first implantation area 130, the top surface 132T of the second implantation area 132, and the top surface 134T of the first well area 134 are coplanar.

[0040] The semiconductor structure 100 includes a transistor 150, a gate oxide layer 160, and a gate 170. The transistor 150 is located between the first well regions 134 and on the top surface 116T of the current dispersing layer 116. The transistor 150 has a first sidewall 150S1 and a second sidewall 150S2. The distance between the first sidewall 150S1 of the transistor 150 and the first sidewall 132S1 of the second implantation region 132 is a first distance D1. The distance between the second sidewall 150S2 of the transistor 150 and the second sidewall 132S2 of the second implantation region 132 is a second distance D2. Since two self-aligned implantations are performed with a single mask, the first distance D1 is equal to the second distance D2, without causing offset. Gate oxide layer 160 is located above the top surface 130T of the first implantation region 130, the top surface 132T of the second implantation region 132, the top surface 134T of the first well region 134, and the top surface of transistor 150. Gate 170 is located above gate oxide layer 160. Semiconductor structure 100 includes back-end process element 180. Back-end process element 180 is located above gate oxide layer 160 and gate 170.

[0041] The method disclosed herein removes the first mask in stages through a precise wet etching process, enabling two self-aligned ion implantations to be performed with one mask, simplifying the mask formation process and reducing ion implantation errors caused by the offset of forming multiple masks.

[0042] Although this disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are also possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

[0043] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of this disclosure without departing from the scope or spirit of this disclosure. In view of the foregoing, this disclosure is intended to cover modifications and variations of this disclosure that fall within the scope of the appended claims. [Simplified Explanation of the Diagram]

[0044] To make the purpose of this disclosure more apparent and understandable, the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings: Figures 1 to 15 are cross-sectional views of intermediate stages in the manufacture of semiconductor structures according to some embodiments. [Biomaterial Storage]

[0046] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A method for manufacturing a semiconductor structure, comprising: A substrate is provided, including a current dispersing layer; A first mask is formed on the substrate; A first implantation process is performed using the first mask to form a first implantation area in the substrate; a first spacer is formed on the sidewall of the first mask, and a second spacer is formed on the sidewall of the first spacer to cover the first implantation area, wherein the first mask, the first spacer, and the second spacer are formed of different materials; the first spacer is removed. Remove a first portion of the first mask; A second implantation process is performed using the first mask and the second spacer to form a second implantation area in the substrate, such that the second implantation area is self-aligned with the first implantation area. Remove the second spacer; remove a second portion of the first mask; and perform a third implantation process with the first mask to form a first well region in the substrate, such that the first well region is self-aligned with the second implantation region, wherein at least a portion of a top surface of the current dispersing layer is located between a bottom surface of the second implantation region and a bottom surface of the first well region.

2. The method of claim 1, wherein a first wet etching process is performed using a first etchant to remove the first spacer, wherein the first spacer comprises polycrystalline silicon and the first etchant comprises tetramethylammonium hydroxide; a second wet etching process is performed using a second etchant to remove the first portion of the first mask, wherein the first mask comprises silicon nitride and the second etchant comprises phosphoric acid; a third wet etching process is performed using a third etchant to remove the second spacer, wherein the second spacer comprises silicon oxide and the third etchant comprises hydrofluoric acid and ammonium fluoride; and a fourth wet etching process is performed using a fourth etchant to remove the second portion of the first mask, wherein the fourth etchant comprises phosphoric acid.

3. The method as claimed in claim 2, wherein the substrate has a heavily doped layer, a lightly doped layer above the heavily doped layer, and a current dispersing layer located within the lightly doped layer, and the first mask covers the lightly doped layer.

4. The method as described in claim 3, wherein after the second wet etching process is performed using the second etchant, the first mask and the second spacer together expose a portion of the first implantation region and a portion of the lightly doped layer adjacent to the first implantation region.

5. The method as described in claim 3, wherein after the fourth wet etching process is performed using the fourth etchant, the first mask exposes the first implantation region, the second implantation region, and a portion of the lightly doped layer adjacent to the second implantation region.

6. The method as described in claim 3, further comprising: After the first well region is formed, the first mask is removed and a second mask is formed to cover the first implantation region, the second implantation region and the first well region, and to expose the lightly doped layer.

7. The method as described in claim 6, further comprising: A fourth implantation process is performed using the second mask to form a transistor in the lightly doped layer of the substrate. A thermal annealing process is performed to form a gate oxide layer on the substrate; and a gate is formed on the gate oxide layer.

8. A method for manufacturing a semiconductor structure, comprising: A substrate is provided, including a current dispersing layer; A first mask is formed on the substrate; A first implantation region is formed in the substrate by performing a first implantation process using the first mask; a first spacer and a second spacer are formed on the sidewall of the first mask, wherein the first spacer is located between the first mask and the second spacer, and the first spacer and the second spacer cover the first implantation region, wherein the first mask, the first spacer, and the second spacer are formed of different materials; the first spacer is removed to form a first opening, wherein a sidewall of the first implantation region is aligned with a first sidewall of the first opening; A first portion of the first mask is removed to enlarge the first opening into a second opening; a second implantation process is performed with the first mask and the second spacer to form a second implantation region in the substrate, wherein one sidewall of the second implantation region is aligned with a second sidewall of the second opening; the second spacer is removed to enlarge the second opening into a third opening, wherein the sidewall of the second implantation region is aligned with a third sidewall of the third opening; a second portion of the first mask is removed to enlarge the third opening into a fourth opening; and a third implantation process is performed with the first mask to form a first well region in the substrate, wherein one sidewall of the first well region is aligned with a fourth sidewall of the fourth opening, wherein at least a portion of a top surface of the current dispersing layer is located between a bottom surface of the second implantation region and a bottom surface of the first well region.

9. The method as described in claim 8, wherein the substrate and the first implantation process include different types of dopants.

10. The method as described in claim 8, wherein the first implantation process and the second implantation process include different types of dopants.

11. The method as described in claim 8, wherein the first implantation process and the third implantation process include the same type of dopant.

12. The method as described in claim 8, wherein the first mask has a first thickness before the first fabrication process is performed, and the first thickness is greater than 5 micrometers.

13. A semiconductor structure comprising: A substrate includes a current dispersing layer; a transistor is located on the current dispersing layer and has a first sidewall and a second sidewall; A first well region is located on the current dispersing layer and contacts the first sidewall and the second sidewall of the transistor, respectively, wherein a bottom surface of the first well region is lower than a top surface of the current dispersing layer; a first implantation region is located in the first well region; and a second implantation region is located in the first well region and between the first implantation region and the transistor, the second implantation region having a first sidewall, a second sidewall and a bottom surface, wherein a first distance is between the first sidewall of the second implantation region and the first sidewall of the transistor, a second distance is between the second sidewall of the second implantation region and the second sidewall of the transistor, and the first distance and the second distance are equal, wherein at least a portion of the top surface of the current dispersing layer is located between the bottom surface of the second implantation region and the bottom surface of the first well region.

14. The semiconductor structure as described in claim 13, wherein the substrate further comprises: A single doped layer is located below the current-dispersing layer; And a lightly doped layer is located between the current-dispersing layer and the heavily doped layer.

15. The semiconductor structure as described in claim 13, further comprising: A gate is located above the transistor; and a gate oxide layer is located between the transistor and the gate.

16. The semiconductor structure as claimed in claim 13, wherein the bottom surface of the first implantation region and the bottom surface of the second implantation region are higher than the bottom surface of the first well region.

17. The semiconductor structure as claimed in claim 13, wherein a top surface of the first implantation region, a top surface of the second implantation region, and a top surface of the first well region are coplanar.

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