Semiconductor structure with tsvs

Abstract

The present invention proposes a semiconductor structure with TSVs, including a pre-metal dielectric layer on a substrate, a peripheral metal interconnect layer on the pre-metal dielectric layer (PMD), an interlayer dielectric layer (ILD) on the pre-metal dielectric layer and the peripheral metal interconnect layer, a BEOL metal interconnect on the interlayer dielectric layer, multiple vias in the interlayer dielectric layer and directly connecting the peripheral metal interconnect layer and the BEOL metal interconnect, and a TSV passing through the substrate and the pre-metal dielectric layer from the backside of the substrate and directly connected to the peripheral metal interconnect layer, wherein the TSV vertically overlaps the vias.

Description

[Technical Field]

[0001] The present invention generally relates to a semiconductor structure having through silicon vias (TSVs), and more particularly, to a semiconductor structure in which the through silicon vias overlap with other vertical vias. [Previous Technology]

[0002] Through-silicon vias (TSVs) are vertical interconnect structures that penetrate a silicon wafer or chip. Unlike vias that connect various metal interconnect layers on a substrate, TSVs pass through the entire substrate or chip, enabling chip-to-chip, chip-to-wafer, and / or wafer-to-wafer circuit interconnections. Using direct silicon wafer vias (TSVs) 3D interconnect technology to replace traditional wire bonding extends the limits of Moore's Law, allowing multiple ICs to be interconnected and packaged together in a three-dimensional stack. This integrates logic, memory, and analog components, operating similarly to a System-on-Chips (SoC). Because the interconnect lines are located between chips, the internal connection paths are shorter, increasing inter-chip transmission speed, reducing noise, and improving overall performance. It also meets high-density requirements and overcomes the process and packaging bottlenecks faced by SoCs.

[0003] Depending on the manufacturing process, the fabrication methods of silicon through-the-vessel (TSV) interconnects can be divided into three types: via first, via middle, and via last. These are respectively performed before the semiconductor front-end-of-line (FEOL) process, after the semiconductor front-end-of-line (FEOL) process, before the semiconductor back-end-of-line (BEOL) process, and after the semiconductor back-end-of-line (BEOL) process. Regarding the via last (TSV) process, since the TSV is fabricated only after the back-end metal interconnect (BEOL interconnect) structure is formed, the current industry practice is to design the layout so that the TSV does not overlap with the formed back-end metal interconnect (via) in the vertical direction.

[0004] More specifically, please refer to Figures 1 and 2, which are respectively schematic diagrams of the layout and cross-section of a through-silicon via (TSV) and metal interconnects in the prior art. As shown in the figures, in terms of the circuit connection hierarchy, component 10 is a TSV, component 20 is a metal interconnect layer directly connected to the TSV 10, component 22 is a via directly connected to the metal interconnect layer 20, and component 30 is a back-end metal interconnect layer directly connected to the vias 22. In terms of semiconductor manufacturing process, the aforementioned back-end metal interconnect layer 30 is a metal circuit fabricated in the back-end semiconductor process (BEOL), such as the commonly known first metal layer (M1), which can be connected to higher-level back-end metal interconnect structures, such as M2, V2, M3, V3, etc., through the first vias V1. The metal interconnect layer 20 and via 22 are metal circuits fabricated in the semiconductor mid-stage process (MEOL). They are responsible for connecting the aforementioned back-end metal interconnect structure to the active region of the substrate, serving as a transition layer between the semiconductor circuit and the metal circuit. In some logic processes, the metal interconnect layer 20 may be referred to as the zeroth metal layer (M0), and the via 22 may be referred to as the zeroth via (V0). In memory processes, the capacitor structure may be located in the semiconductor mid-stage process layer. On the other hand, for the via-last type TSV 10, the metal interconnect layer 20 and via 22 are formed first, and the TSV 10 is then connected to the formed metal interconnect layer 20 by penetrating the substrate and / or dielectric layer located in the semiconductor front-end process (FEOL) layer.

[0005] Referring again to Figures 1 and 2. As can be seen from the figures, in the prior art, TSV 10 is intentionally designed so that it does not overlap with the via 22 in the MEOL layer in the direction perpendicular to the substrate. With this design, the via 22 must be placed in the layout space outside of TSV 10. Since the via 22 and TSV 10 are directly connected to the metal interconnect layer 20 in the vertical direction, the layout pattern of the metal interconnect layer 20 must cover and be larger than the layout pattern of TSV 10. The layout plane between the metal interconnect layer 20 and TSV 10 is the location where the via 22 can be placed. This design increases the layout area of ​​the metal interconnect layer 20. In addition, because the current path from TSV 10 through the metal interconnect layer 20 to the via 22 is longer, the overall resistance of the circuit will also increase. Furthermore, since the rear metal interconnect layer 30 is directly connected to the via 22 in the vertical direction, its layout pattern will be limited by the layout of the via 22. Thus, if the TSV 10 and the via 22 do not overlap in the vertical direction, the layout pattern of the rear metal interconnect layer 30 must also cover and be larger than the layout pattern of the TSV 10, just like the metal interconnect layer 20. This design also increases the difficulty of wiring the rear metal circuit. [Summary of the Invention]

[0006] In view of the various limitations and disadvantages of the prior art, the present invention proposes a novel semiconductor structure with through-silicon vias (TSVs), characterized in that the through-silicon vias can overlap with vias in the semiconductor mid-stage process (MEOL) layer in the vertical direction, thereby reducing the necessary area and resistance of the metal interconnect layer and making the wiring design of the downstream metal circuit more flexible.

[0007] The purpose of this invention is to provide a semiconductor structure with silicon through-hole interconnects, comprising: a substrate having a storage cell region, a peripheral region, and a silicon through-hole region defined on its front side, and a plurality of active regions formed therein; a pre-deposited dielectric layer located on the front side of the substrate; a plurality of storage node contacts located in the pre-deposited dielectric layer on the storage cell region and directly connected to the active regions; a plurality of contacts located in the pre-deposited dielectric layer on the peripheral region and directly connected to the active regions; and a peripheral metal interconnect layer located on the pre-deposited dielectric layer and directly connected to the contacts on the peripheral region. The device includes: an interlayer dielectric layer located on the pre-deposited dielectric layer and the peripheral metal interconnect layer; multiple capacitors located in the interlayer dielectric layer on the storage cell region and connected to the storage node contacts; a rear-end metal interconnect structure located on the interlayer dielectric layer; multiple vias located in the interlayer dielectric layer and directly connecting the peripheral metal interconnect layer and the rear-end metal interconnect structure; and a silicon through-hole interconnect extending from the back side of the substrate through the substrate and the pre-deposited dielectric layer and directly connected to the peripheral metal interconnect layer located in the silicon through-hole region, wherein the silicon through-hole interconnect overlaps with the vias in a direction perpendicular to the substrate.

[0008] Such and other objects of the present invention should become more apparent to the reader after reading the detailed description of the preferred embodiments described below with various illustrations and drawings.

Implementation Method

[0009] Exemplary embodiments of the present invention will now be described in detail below, with reference to the accompanying drawings illustrating the described features to enable the reader to understand and achieve the technical effects. The reader will understand that the descriptions herein are by way of illustration only and are not intended to limit the scope of the invention. Various embodiments of the invention and various non-conflicting features thereof can be combined or rearranged in various ways. Modifications, equivalents, or improvements to the invention will be understood by those skilled in the art without departing from the spirit and scope of the invention, and are intended to be included within the scope of the invention.

[0010] Readers should be able to easily understand that the meanings of “on”, “above” and “above” in this case should be interpreted in a broad sense, such that “on” not only means “directly on” something, but also includes the meaning of being “on” something with an intermediary feature or layer, and that “above” or “above” not only means “on” something, but also includes the meaning of being “on” something without an intermediary feature or layer (i.e., directly on something).

[0011] In addition, spatial terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein for convenience to describe the relationship between one element or feature and one or more other elements or features, as shown in the accompanying drawings.

[0012] Readers can generally understand terms at least partially from their usage in context. For example, depending at least partially on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least partially on the context, terms such as "a," "an," "the," or "the" can also be understood to convey either a singular or a plural usage. In addition, the term "based on" can be understood to not necessarily convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least partially on the context.

[0013] Readers will better understand that when words such as "comprising" and / or "containing" are used in this specification, they expressly define the presence of the stated features, areas, wholes, steps, operations, elements and / or components, but do not preclude the possibility of the presence or addition of one or more other features, areas, wholes, steps, operations, elements, components and / or combinations thereof.

[0014] As used herein, the term "substrate" refers to the material on which subsequent material is added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0015] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a structure below or above, or may have a range smaller than that of the structure below or above. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any horizontal faces at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along an inclined surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where contacts, interconnects, and / or vias are formed) and one or more dielectric layers.

[0016] First, please refer to Figures 3 and 4 simultaneously, which are respectively schematic diagrams of the layout and cross-sectional view of a through-silicon via (TSV) and metal interconnects according to an embodiment of the present invention. As shown in the figures, in terms of the circuit connection hierarchy, component 100 is a TSV, component 110 is a metal interconnect layer directly connected to the TSV 100, component 112 is a via directly connected to the metal interconnect layer 110, and component 120 is a back-end metal interconnect layer directly connected to the vias 112. In terms of semiconductor manufacturing process, the aforementioned back-end metal interconnect layer 120 is a metal circuit fabricated in the back-end semiconductor process (BEOL), such as the conventional first metal layer M1, which can be connected to higher-level back-end metal interconnect structures, such as the second metal layer M2, the second via V2, the third metal layer M3, and the third via V3, through the first via V1. In the diagram, only M1, V1, and M2 represent the entire back-end metal interconnect structure. In the embodiment, the metal interconnect layer 110 and the via 112 are metal circuits fabricated in the semiconductor mid-stage process (MEOL), responsible for connecting the aforementioned back-end metal interconnect structure to the active region of the substrate (not shown), belonging to the transition layer between semiconductor circuits and metal circuits. In some logic processes, the metal interconnect layer 110 may be referred to as the zeroth metal layer (M0), and the via 22 may be referred to as the zeroth via (V0). In memory processes, the capacitor structure and bit lines may be located in the semiconductor mid-stage process layer. On the other hand, for the via-last type TSV 100, the metal interconnect layer 110 and the via 112 are formed first, and the TSV 100 then penetrates the substrate and / or dielectric layer located in the semiconductor front-end process (FEOL) layer to connect to the formed metal interconnect layer 110.

[0017] Referring again to Figures 3 and 4. In this embodiment of the invention, unlike the prior art, the TSV 100 can be designed to overlap with the vias 112 in the MEOL layer in the direction perpendicular to the substrate. As can be seen from the figures, some of the vias 112 are located within the planar layout area of ​​the TSV 100, and some of the vias 112 are located outside the planar layout area of ​​the TSV 100, but still within the planar layout area of ​​the metal interconnect layer 110. With this design, it can be seen from the figures that the rear metal interconnect layer 120, which was originally limited by the layout position of the vias 112, has a more flexible and unrestricted layout pattern design because the position of the vias 112 becomes more free. There is no layout pattern that must cover and be larger than the TSV 100, which can reduce the wiring difficulty of the rear metal circuit. Furthermore, since the via 112 does not necessarily need to be designed within the planar layout space of the metal interconnect layer 110 outside the location of the TSV 100, the area of ​​the metal interconnect layer 110 can be reduced, facilitating circuit miniaturization. In addition, the current path from the TSV 100 through the metal interconnect layer 110 to the via 112 becomes shorter, reducing the overall resistance of the circuit. These are some of the many advantages of the structural design of this invention.

[0018] After explaining the layout diagram and cross-sectional diagram of the aforementioned TSV and metal interconnect structure, the following embodiments will use dynamic random access memory (DRAM) as an example to illustrate the application of the semiconductor structure with TSV in the memory architecture of the present invention.

[0019] Please now refer to Figure 5, which is a cross-sectional schematic diagram of a DRAM structure according to an embodiment of the present invention. In this embodiment, the storage cells and various required components in the DRAM are fabricated on a substrate 101. The substrate 101 may be a silicon substrate, on which a cell region 101a, a peripheral region 101b, and a silicon through-via region 101c are defined, and multiple active regions exposed from the surface of the substrate 101 are separated by a shallow trench isolation structure (STI). Each active region may also be doped with dopants through a doping process to form various doped regions, such as source, drain, well regions, etc. (not shown). In this embodiment, word lines WL, bit lines BL, and storage node contacts SC are formed on the cell region 101a, wherein the word lines WL are embedded in the substrate 101, and can control the switching of the corresponding cell row channel during the read and write operations of the storage cell to achieve the purpose of selecting a specific cell row. The bit line BL and the storage node contact SC are disposed on the substrate 101 and connected to the corresponding active area below. Each storage node contact SC is also connected to the corresponding capacitor C above it. During read and write operations, the bit line BL is the main signal channel. When the corresponding cell row is selected and enabled by the word line WL, the data stored in the capacitor C can be read by transmitting it to the bit line BL through the storage node contact SC, or data from external circuits can be written from the bit line BL to the capacitor C for storage via the storage node contact SC.

[0020] Referring again to Figure 5. The peripheral area 101b is used to house peripheral components for the DRAM, which may include row / column decoders, column amplifiers, row selectors and refresh controllers, data buffers, timing controllers, power management modules, error correction circuits, etc. Its function is to process the read signals and the signals to be written; only one component 111 is represented in the figure. The peripheral area 101b has contacts 103 connecting the active area of ​​the substrate 101 to the upper peripheral metal interconnect layer 110, and then connecting via a via 112 to a metal layer 120 in the upper rear metal interconnect structure, such as the first metal layer (M1). It should be noted that in this invention, a contact specifically refers to a vertical connector connecting the active area of ​​the semiconductor material to the interconnect layer of the metal material, while a via specifically refers to a vertical connector connecting two interconnect layers of metal materials. In this embodiment, a pre-metal dielectric (PMD), such as a silicon oxide layer, is formed on the substrate 101. The aforementioned components 111 are generally formed within this PMD, and contacts 103 are also formed within it, connecting the active region in the substrate 101 to the peripheral metal interconnect layer 110 on the surface of the PMD. In DRAM manufacturing, the various components within the PMD, including word lines (WL), bit lines (BL), memory node contacts (SC), active regions, components 111, and contacts 103, belong to the front-end semiconductor process (FEOL) level.

[0021] Referring again to Figure 5. In this embodiment, a thick dielectric layer, such as an interlayer dielectric (ILD), is formed on the pre-deposited dielectric layer (PMD). The material of ILD can be silicon oxide or a low-k material. In DRAM manufacturing, the ILD belongs to the semiconductor mid-stage process (MEOL) level. It mainly provides space for setting capacitor structures and serves as an interconnect layer between the FEOL and BEOL levels. A capacitor C is formed in the ILD on the storage cell region 101a, which is connected to the corresponding storage node contact SC below. A via 112 is formed in the ILD on the peripheral region 101b, which penetrates the ILD and connects the lower peripheral metal interconnect layer 110 and the upper semiconductor back-end process (BEOL) first metal layer (M1) 120, allowing the components 111 in the peripheral region 101b to be connected to the back-end metal circuit. In this invention, the peripheral metal interconnect layer 110 and the via 112 can be considered as the zeroth metal layer (M0) and the zeroth via (V0) before the subsequent metal interconnect structure. In terms of materials, the contact 103, the peripheral metal interconnect layer 110, and the via 112 are formed of tungsten (W). Furthermore, it should be noted that in some embodiments, the peripheral metal interconnect layer 110 in the peripheral region 101b may belong to the same metal layer and be formed using the same process as the contact pad 113 on the storage node contact SC. Moreover, the element 111 on the peripheral region 101b may be an extension of the bit line BL and formed in the same process as the bit line BL. The capacitor C may also have a portion extending into the peripheral region 101b, for example, the upper electrode TE of the capacitor C in the figure extends into the peripheral region 101b and is located directly above the peripheral metal interconnect layer 110.

[0022] Referring again to Figure 5. In this embodiment, since silicon through-hole interconnects (TSVs) are to be provided, no doped regions, shallow trench isolation structures, or functional components are formed in the substrate 101 of the silicon through-hole region 101c and the pre-deposited dielectric layer PMD. The TSV is intended to be connected from the back side of the substrate 101 to the peripheral metal interconnect layer 110 in the MEOL layer after the BEOL process is completed, and is a via-last type TSV. Similar to the peripheral region 101b, a via (VO) 112 is formed in the interlayer dielectric layer ILD of the silicon through-hole region 101c, which penetrates the interlayer dielectric layer ILD and connects the lower peripheral metal interconnect layer (MO) 110 and the upper first metal layer (M1) 120 in the semiconductor back-end process (BEOL), so that the subsequently connected TSV can be further connected to the back-end metal circuit. In the back-end semiconductor assembly (BEOL) layer, the back-end metal interconnect structure is composed of multiple metal layers, such as a first metal layer M1, a second metal layer M2, M3, etc., connected by corresponding vias, such as V1, V2, V3, etc. The metal layers and vias are located in corresponding inter-metal dielectric (IMD) layers, such as the first inter-metal dielectric layer IMD1, the second inter-metal dielectric layer IMD2, IMD3, etc., and their material can be silicon oxide or phosphorus-doped tetraethoxysilane (P-TEOS). In DRAM manufacturing, the aforementioned back-end metal interconnect structure is made of copper (Cu), unlike the metal interconnect structure in MEOL, which is made of tungsten (W). Since the resistance of tungsten is significantly greater than that of copper, shortening the current path in MEOL can effectively reduce the overall resistance of the semiconductor structure. Furthermore, in this embodiment, a contact pad 105 is formed in the outermost layer of the BEOL, through which the back-end metal circuit can be connected to external circuits. The contact pad 105 can be made of aluminum (Al), which has a simple manufacturing process and good thermal stability and oxidation resistance.

[0023] Now please refer to Figure 6. After completing the aforementioned BEOL process, as shown in Figure 6, the entire substrate 101 is flipped so that its front side faces down and bonded to a carrier substrate 107, such as by thermoforming, to perform subsequent back-side processing. In this embodiment, the TSV 100 passes through the back side of the substrate 101 and the pre-metal deposition dielectric layer (PMD) and connects to the peripheral metal interconnect layer 110 in the MEOL layer. In this embodiment, the fabrication process of TSV 100 may include: forming silicon vias through the substrate 101 and the pre-deposited dielectric layer (PMD) using photolithography processes such as laser or deep reactive ion etching, until the peripheral metal interconnect layer 110 is exposed from the silicon vias; after the silicon vias are formed, processes such as subatmospheric chemical vapor deposition (SA-CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) are performed to form a barrier layer and a seed layer on the surface of the silicon vias; then, the silicon vias are filled with electroplated copper; finally, the metal layer outside the silicon vias is removed by a chemical mechanical planarization (CMP) process, thus forming TSV 100, which connects to the peripheral metal interconnect layer 110 and is exposed from the back side of the substrate 101. As shown in the figure, in this invention, TSV 100 overlaps with vias 112 (V0) in part of the MEOL layer in the vertical direction, meaning the position of vias 112 is not limited by the layout of TSV 100. This design allows for more flexible layout of the subsequent metal interconnect layer 120 (i.e., the first metal layer M1), reducing the difficulty of wiring the subsequent metal circuitry. The area of ​​the peripheral metal interconnect layer 110 (i.e., the zeroth metal layer M0) is also reduced, facilitating circuit miniaturization. Furthermore, because the current path between TSV 100 and vias 112 is shortened, the overall resistance of the circuit is reduced, resulting in numerous advantages of the structural design of this invention.

[0024] Finally, please refer to Figure 7. After the TSV 100 is formed, a redistribution layer (RDL) 109 is then formed on the back of the die, which is directly connected to the TSV 100. In this embodiment, the redistribution layer 109 can rearrange and distribute the I / O contacts (e.g., solder balls, pads) on the surface of the TSV 100 and the substrate 101, making these I / O contacts more suitable for connection to external circuits. In this embodiment, the redistribution layer 109 converts the vertical interconnect signal from the TSV 100 into a horizontal signal and distributes it to the external pads and / or solder balls of the die. In this invention, the TSV 100 can achieve vertical interconnection between wafer or die layers, for example, integrating the circuit connections of multiple vertically stacked DRAM chips into a single circuit, realizing high-density, high-performance electrical connections for 2.5D IC packaging or 3D IC packaging. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made within the scope of the claims of this invention should be included in the scope of this invention. [Simplified Explanation of the Diagram]

[0025] This specification includes accompanying drawings, which form part of this specification, to provide the reader with a further understanding of the embodiments of the present invention. These drawings depict some embodiments of the present invention and, together with the description herein, illustrate its principles. In these drawings: Figure 1 is a schematic layout diagram of a through-silicon via (TSV) and metal interconnects in the prior art; Figure 2 is a schematic cross-sectional view of a TSV and metal interconnect structure in the prior art; Figure 3 is a schematic layout diagram of a TSV and metal interconnect structure according to an embodiment of the present invention; Figure 4 is a schematic cross-sectional view of a TSV and metal interconnect structure according to an embodiment of the present invention; Figure 5 is a schematic cross-sectional view of a dynamic random access memory (DRAM) according to an embodiment of the present invention; Figure 6 is a schematic cross-sectional view of a dynamic random access memory (DRAM) according to an embodiment of the present invention; and Figure 7 is a schematic cross-sectional view of a dynamic random access memory (DRAM) according to an embodiment of the present invention. It should be noted that all illustrations in this specification are for illustrative purposes only. For clarity and ease of illustration, the size and scale of the components in the illustrations may be exaggerated or reduced. Generally, the same reference symbols in the illustrations are used to indicate corresponding or similar component features in modified or different embodiments.

Claims

1. A semiconductor structure with silicon through-hole interconnects, comprising: a substrate having a storage cell region, a peripheral region, and a silicon through-hole region defined on its front side, and a plurality of active regions formed therein; a pre-deposited metal dielectric layer located on the front side of the substrate; a plurality of storage node contacts located in the pre-deposited metal dielectric layer on the storage cell region and directly connected to the active regions; a plurality of contacts located in the pre-deposited metal dielectric layer on the peripheral region and directly connected to the active regions; a peripheral metal interconnect layer located on the pre-deposited metal dielectric layer and directly connected to the contacts on the peripheral region; an interlayer dielectric layer located on the pre-deposited metal dielectric layer and the peripheral metal interconnect layer; a plurality of capacitors located in the interlayer dielectric layer on the storage cell region and connected to the storage node contacts; and a back-end metal interconnect structure located on the interlayer dielectric layer. Multiple vias are located in the interlayer dielectric layer and directly connect the peripheral metal interconnect layer and the subsequent metal interconnect structure; and a silicon through-hole interconnect extends from the back side of the substrate, through the substrate and the pre-deposited dielectric layer, and directly connects to the peripheral metal interconnect layer located in the silicon through-hole region, wherein the silicon through-hole interconnect overlaps with the vias in a direction perpendicular to the substrate. The peripheral metal interconnect layer and the vias are made of a first metal material, and the subsequent metal interconnect structure and the silicon through-hole interconnect are made of a second metal material, wherein the first metal material is different from the second metal material.

2. The semiconductor structure with silicon through-hole interconnects as described in claim 1, wherein the peripheral metal interconnect layer located in the storage cell region is a storage node contact pad that is directly connected to the storage node contacts.

3. A semiconductor structure with silicon through-hole interconnects as described in claim 1, wherein the capacitors have an upper electrode that extends over the peripheral region and is located directly above the peripheral metal interconnect layer.

4. The semiconductor structure with silicon through-hole interconnects as described in claim 1 further includes multiple bit lines located in the pre-deposited dielectric layer on the storage cell region.

5. The semiconductor structure with silicon through-hole interconnects as described in claim 1 further includes a layer located on the back side of the substrate and directly connected to the silicon through-hole interconnects.

6. The semiconductor structure with silicon through-hole interconnects as described in claim 1 further includes a plurality of peripheral elements located in the pre-deposited dielectric layer on the peripheral region.

7. A semiconductor structure having silicon through-hole interconnects as described in claim 1, wherein the first metal material comprises tungsten and the second metal material comprises copper.

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