Die stacked structures and package structures including the same

TW202630942AActive Publication Date: 2026-07-16WINBOND ELECTRONICS CORP
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Patent Information

Authority / Receiving Office
TW · TW
Patent Type
Applications
Current Assignee / Owner
WINBOND ELECTRONICS CORP
Filing Date
2025-02-11
Publication Date
2026-07-16

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    Figure TWG2TA001068168_003
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Abstract

A die stacked structure includes a first die, a second die, and a first connector and a second connector. The first die includes a first interconnect structure, a first capacitor, and a plurality of first through vias. The first capacitor is connected to the first interconnect structure. The first interconnect structure is connected to the plurality of first through vias. The second die is bonded to the first die. The second die includes a second interconnect structure, and a second capacitor. The second capacitor is connected to the second interconnect structure. The first connector and the second connector are connected to the first die. The first capacitor and the second capacitor are connected to each other through the first interconnect structure, a plurality of bonding structures, and the second interconnect structure.
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Claims

1. A wafer stacking structure, comprising: A first wafer includes a first interconnect structure, a first capacitor, and a plurality of first vias, wherein the first capacitor is connected to the first interconnect structure, and the first interconnect structure is connected to the plurality of first vias; a second wafer is bonded to the first wafer, the second wafer including a second interconnect structure and a second capacitor, wherein the second capacitor is directly connected to the second interconnect structure; and a first connector and a second connector are connected to the first wafer, wherein the first capacitor and the second capacitor are connected to each other via the first interconnect structure, the plurality of bonding structures, and the second interconnect structure.

2. The wafer stacking structure as claimed in claim 1, wherein the first wafer and the second wafer are bonded face-to-back, and the first connector and the second connector are respectively connected to the plurality of first vias of the first wafer.

3. The wafer stacking structure as described in claim 1, wherein the second wafer further comprises: Multiple second through holes, wherein the second capacitor is connected to the multiple second through holes via the second interconnect structure.

4. The wafer stacking structure as claimed in claim 3, wherein the first capacitor and the second capacitor are further connected to each other via the second via.

5. The wafer stacking structure as claimed in claim 4, wherein the first capacitor is connected in parallel or in series with the second capacitor.

6. The wafer stacking structure as claimed in claim 4, wherein the first electrode plate of the first capacitor is connected to the first electrode plate of the second capacitor via the first connector, and the second electrode plate of the first capacitor is connected to the second electrode plate of the second capacitor via the second connector.

7. The wafer stacking structure as claimed in claim 4, wherein the first electrode plate of the first capacitor is connected to the first connector, the second electrode plate of the first capacitor is connected to the first electrode plate of the second capacitor, and the second electrode plate of the second capacitor is connected to the second connector.

8. The wafer stacking structure as claimed in claim 1, wherein the first wafer and the second wafer are bonded back-to-back, and the first connector and the second connector connect the first interconnect structure of the first wafer.

9. The wafer stacking structure as claimed in claim 1, wherein the first capacitor and the second capacitor are further connected to each other via the plurality of first vias.

10. The wafer stacking structure as claimed in claim 9, wherein the first capacitor is connected in parallel or in series with the second capacitor.

11. The wafer stacking structure as claimed in claim 9, wherein the second electrode plate of the first capacitor is connected to the second electrode plate of the second capacitor via the first connector, and the first electrode plate of the first capacitor is connected to the first electrode plate of the second capacitor via the second connector.

12. The wafer stacking structure as claimed in claim 9, wherein the second electrode plate of the first capacitor is connected to the first connector, the first electrode plate of the first capacitor is connected to the second electrode plate of the second capacitor, and the first electrode plate of the second capacitor is connected to the second connector.

13. The wafer stacking structure as claimed in claim 1, wherein the first wafer and the second wafer are joined face-to-face, and the first connector and the second connector connect the plurality of first vias of the first wafer.

14. The wafer stacking structure as claimed in claim 13, wherein the first capacitor is connected in parallel or in series with the second capacitor.

15. The wafer stacking structure as claimed in claim 13, wherein the first electrode plate of the first capacitor is connected to the first electrode plate of the second capacitor via the first connector, and the second electrode plate of the first capacitor is connected to the second electrode plate of the second capacitor via the second connector.

16. The wafer stacking structure as claimed in claim 13, wherein the first electrode plate of the first capacitor is connected to the first connector, the second electrode plate of the first capacitor is connected to the first electrode plate of the second capacitor, and the second electrode plate of the second capacitor is connected to the second connector.

17. The wafer stacking structure as claimed in claim 1, wherein the plurality of bonding structures are a hybrid bonding structure or a plurality of microbump bonding structures.

18. The wafer stacking structure as claimed in claim 1, wherein the first interconnect structure includes a plurality of first conductor plugs and a plurality of first conductor layers, wherein each of the plurality of first conductor plugs is connected to the plurality of first conductor layers.

19. A packaging structure, comprising: The wafer stacking structure, third wafer, fourth wafer, and interposer or substrate as described in claim 1, wherein the third wafer is on the fourth wafer, the fourth wafer is on the interposer or the substrate, and wherein the first connector and the second connector are connected to the third wafer, the fourth wafer, the interposer or the substrate.

20. A packaging structure, comprising: The wafer stacking structure, third wafer, and interposer or substrate as described in claim 1, wherein the wafer stacking structure is between the third wafer and the interposer, or between the third wafer and the substrate, wherein the first connector and the second connector are connected to the third wafer.