High-thermal-conductivity locally thinned power chip

Abstract

The present invention discloses a high-thermal-conductivity locally thinned power chip, comprising a semiconductor submount and a plurality of field-effect transistors (FETs) arranged in an array on the semiconductor submount. The active regions of the FETs are collectively integrated with the semiconductor submount, making the semiconductor submount serve as the common drain for the FETs. A heat zone is formed on the semiconductor submount, and a groove is provided on the underside of the semiconductor submount at the location corresponding to the heat zone, creating a thinned section on the semiconductor submount. The semiconductor submount also includes a stress support structure surrounding the periphery of the thinned section. Additionally, the groove is filled with a high thermal conductivity and high electrical conductivity material to enhance heat dissipation efficiency directly beneath the heat zone. ​

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