Time-to-digital converter and calibration method for performing time-to-digital conversion on input signal
Patent Information
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- REALTEK SEMICON CORP
- Filing Date
- 2025-01-17
- Publication Date
- 2026-08-01
AI Technical Summary
Existing time-to-digital converters face accuracy issues due to synchronization errors between the start and end times of the time interval and the clock signal, leading to significant errors in time measurement, and existing solutions to improve accuracy increase circuit complexity, area, and power consumption.
A time-to-digital converter architecture that includes a time counter, correction circuit, and adder to determine correction values based on the relationship between the input signal edges and clock signal edges, minimizing errors without increasing circuit area or power consumption.
The proposed solution reduces measurement errors in time-to-digital converters by correcting initial count values, improving accuracy without significant increases in circuit size or power consumption.
Smart Images
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Abstract
Description
[Technical Field]
[0001] This invention relates to a circuit for measuring time, and more particularly to a time-to-digital converter and a correction method for performing time-to-digital conversion on an input signal. [Previous Technology]
[0002] A time-to-digital converter typically counts based on a high-speed clock signal within a time interval, so that the length of the time interval can be represented by the number of cycles of the clock signal. However, when the start and / or end time of the time interval is out of sync with the clock signal, the error between the time length represented by the digital signal generated by the above-described time-to-digital conversion mechanism and the time length to be measured can reach up to (TCLK is the cycle of the clock signal).
[0003] Some related technologies improve the accuracy of time-to-digital conversion by increasing the number of stages in the unit circuit, but this results in a significant increase in circuit area, susceptibility to manufacturing variations, and a significant increase in power consumption. Other related technologies propose architectures that greatly increase the overall circuit complexity, but this increases the difficulty and risk of implementation.
[0004] Therefore, there is a need for a novel architecture and method for time-to-digital converters to improve the accuracy of time-to-digital conversion with little or no side effects. [Summary of the Invention]
[0005] The purpose of this invention is to provide a time-to-digital converter and a correction method for performing time-to-digital conversion on an input signal, so as to improve the overall performance of the time-to-digital converter without or with minimal side effects.
[0006] At least one embodiment of the present invention provides a time-to-digital converter. The time-to-digital converter includes a time counter, a correction circuit, and an adder, wherein the adder is coupled to the time counter and the correction circuit. The time counter is used to start counting at a first time point on a first edge of an input signal and to end counting at a second time point on a second edge of the input signal to generate an initial count value. The correction circuit is used to generate a first determination bit based on the first edge of the input signal and a first edge of a clock signal, generate a second determination bit based on the second edge of the input signal and a second edge of the clock signal, and generate a correction value based on the first determination bit and the second determination bit. Additionally, the adder is used to add the correction value to the initial count value to generate a final count value.
[0007] At least one embodiment of the present invention provides a correction method for performing time-to-digital conversion on an input signal, comprising: using a time counter to start counting at a first time point on a first edge of the input signal and end counting at a second time point on a second edge of the input signal to generate an initial count value; generating a first determination bit based on the first edge of the input signal and a first edge of a clock signal; generating a second determination bit based on the second edge of the input signal and a second edge of the clock signal; generating a correction value based on the first determination bit and the second determination bit; and adding the correction value to the initial count value to generate a final count value.
[0008] The time-to-digital converter and correction method provided by the embodiments of the present invention can determine whether the output of the time counter needs to be corrected (e.g., incremented by one) based on the relationship between the input signal and the clock signal at the start time and the relationship between the input signal and the clock signal at the end time, thereby reducing the error between the time-to-digital conversion result and the length of time to be measured to (TCLK is the period of the clock signal). Furthermore, the embodiments of the present invention do not significantly increase circuit area and power consumption; therefore, the present invention can improve the accuracy of the time-to-digital converter without or with minimal side effects.
Implementation Method
[0009] Figure 1 is a schematic diagram of an electronic device 10 including a time-to-digital converter 100 according to an embodiment of the present invention. In this embodiment, the electronic device 10 may be a process monitoring chip for measuring the period of a ring oscillator, thereby determining the process variation of the wafer to which the process monitoring chip belongs, but the present invention is not limited thereto. As shown in Figure 1, the electronic device 10 may include a time-to-digital converter 100, a synchronization circuit 110, a frequency divider multiplexer 120, a frequency divider 130, and an output buffer 140, wherein the input of the frequency divider multiplexer 120 is coupled to the output of the synchronization circuit 110, and the input of the time-to-digital converter 100 is coupled to the output of the frequency divider multiplexer 120. In addition, the input of the output buffer 140 is coupled to the output of the frequency divider 130. In this embodiment, the synchronization circuit 110 may receive an oscillation signal ROMEAS from a ring oscillator (not shown) and sample the oscillation signal ROMEAS according to the clock signal CLK to generate a synchronization oscillation signal ROSYNC. Frequency divider multiplexer 120 divides the synchronous oscillation signal ROSYNC to produce multiple frequency division results (e.g., division by 1, 16, 32, and 64), and selects one of these frequency division results as the input signal RODIV for the time-to-digital converter 100 based on the selection signal SELDIV. The time-to-digital converter 100 performs time-to-digital conversion on the duration of the high-level duty cycle (e.g., a period with logic value "1") or low-level duty cycle (e.g., a period with logic value "0") of the input signal RODIV to produce a final count value NFINAL, which represents the ratio between the measured duration of the input signal RODIV (e.g., the duration of the high-level or low-level duty cycle) and the period TCLK of the clock signal CLK. Frequency divider 130 is used to divide the clock signal CLK, and output buffer 140 outputs the frequency-divided clock signal CLKDIV. Since the divisors of the frequency divider multiplexer 120 and the frequency divider 130 are both controllable and known information, test engineers can detect the final count value NFINAL and the frequency-divided clock signal CLKDIV and calculate the frequency of the oscillation signal ROMEAS accordingly, thereby knowing the process variation of the wafer to which the electronic device 10 belongs, but the present invention is not limited thereto.
[0010] In this embodiment, the time-to-digital converter 100 may include a trigger signal generator 101, a time counter 102, a correction circuit 103, and an adder 104, wherein the time counter 102 is coupled to the trigger signal generator 101, and the adder 104 is coupled to the time counter 102 and the correction circuit 103. In this embodiment, the trigger signal generator 101 may generate trigger signals ROS and ROE corresponding to the input signal RODIV based on the selection signal SELDUTY. For example, when the selection signal SELDUTY has a first logic value (e.g., logic value "1"), the trigger signal generator 101 can generate a trigger signal ROS (especially the rising edge of the trigger signal ROS) corresponding to the rising edge of the input signal RODIV and a trigger signal ROE (especially the rising edge of the trigger signal ROE) corresponding to the falling edge of the input signal RODIV, wherein the falling edge of the input signal RODIV is the first falling edge after the rising edge of the input signal RODIV. As another example, when the selection signal SELDUTY has a second logic value (e.g., logic value "0"), the trigger signal generator 101 can generate a trigger signal ROS (especially the rising edge of the trigger signal ROS) corresponding to the falling edge of the input signal RODIV and a trigger signal ROE (especially the rising edge of the trigger signal ROE) corresponding to the rising edge of the input signal RODIV, wherein the rising edge of the input signal RODIV is the first rising edge after the falling edge of the input signal RODIV. Additionally, the time counter 102 is used to start counting at a first time point at a first edge of the input signal RODIV (e.g., starting counting at the rising edge of the trigger signal ROS) and end counting at a second time point at a second edge of the input signal RODIV (e.g., ending counting at the rising edge of the trigger signal ROE) to generate an initial count value NCNT. Therefore, when the selection signal SELDUTY has the first logic value (e.g., logic value "1"), the time counter 102 can generate an initial count value NCNT based on the duration of the high-level working cycle of the input signal RODIV; and when the selection signal SELDUTY has the second logic value (e.g., logic value "0"), the time counter 102 can generate an initial count value NCNT based on the duration of the low-level working cycle of the input signal RODIV. Additionally, the correction circuit 103 is used to generate a first determination bit based on the first edge of the input signal RODIV and the first edge of the clock signal CLK, and to generate a second determination bit based on the second edge of the input signal RODIV and the second edge of the clock signal CLK. The correction circuit 103 can further generate a correction value NCAL based on the first determination bit and the second determination bit. Furthermore, the adder 104 is used to add the correction value NCAL to the initial count value NCNT to generate the final count value NFINAL.
[0011] Figure 2 is a schematic diagram of the concept of time-to-digital conversion according to an embodiment of the present invention, wherein the dashed line on the left side of Figure 2 may represent the first edge of the input signal RODIV (e.g., the rising edge of the trigger signal ROS), and the dashed line on the right side of Figure 2 may represent the second edge of the input signal RODIV (e.g., the rising edge of the trigger signal ROE). In one embodiment, the initial count value NCNT generated by the time counter 102 when the selection signal CNTSEL is set to the logic value "1" can represent the number of rising edges of the clock signal CLK during the counting period TMEAS between the first time point (e.g., the time point of the rising edge of the trigger signal ROS) and the second time point (e.g., the time point of the rising edge of the trigger signal ROE). The first edge of the clock signal CLK can represent the first rising edge of the clock signal CLK after the first edge of the input signal RODIV (e.g., the first solid line to the right of the dashed line indicating ROS), and the second edge of the clock signal CLK can represent the first rising edge of the clock signal CLK after the second edge of the input signal RODIV (e.g., the first solid line to the right of the dashed line indicating ROE). In another embodiment, the initial count value NCNT generated by the time counter 102 when the selection signal CNTSEL is set to the logic value "0" may represent the number of falling edges of the clock signal CLK during the counting period TMEAS between the first time point (e.g., the time point of the rising edge of the trigger signal ROS) and the second time point (e.g., the time point of the rising edge of the trigger signal ROE), wherein the first edge of the clock signal CLK may represent the first falling edge of the clock signal CLK after the first edge of the input signal RODIV (e.g., the first solid line to the right of the dashed line indicating ROS), and the second edge of the clock signal CLK may represent the first falling edge of the clock signal CLK after the second edge of the input signal RODIV (e.g., the first solid line to the right of the dashed line indicating ROE).
[0012] It should be noted that since the first edge and the second edge of the input signal RODIV may be out of sync with the clock signal CLK, the time difference ∆TS between the first edge of the input signal RODIV and the first edge of the clock signal CLK and / or the time difference ∆TE between the second edge of the input signal RODIV and the second edge of the clock signal CLK may affect the accuracy of the initial count value NCNT. For example, although the time counter 102 counts to N clock signal CLK periods TCLK (N is a positive integer) during the counting period TMEAS, the error between the length of the counting period TMEAS (i.e., the length of the measured time of the input signal RODIV) and the actual time can reach a certain value. Therefore, the correction circuit 103 can determine whether the time difference ∆TS between the first edge of the input signal RODIV and the first edge of the clock signal CLK is greater than half a period of the clock signal CLK (i.e., to generate the first determination bit), and determine whether the time difference ∆TE between the second edge of the input signal RODIV and the second edge of the clock signal CLK is greater than half a period of the clock signal CLK (i.e., to generate the second determination bit). Thus, the first determination bit indicates whether the time difference ∆TS between the first edge of the input signal RODIV and the first edge of the clock signal CLK is greater than half a period of the clock signal CLK, and the second determination bit indicates whether the time difference ∆TE between the second edge of the input signal RODIV and the second edge of the clock signal CLK is greater than half a period of the clock signal CLK. When the first judgment bit indicates that the time difference ∆TS is greater than half a cycle of the clock signal CLK (i.e., ∆TS > 1) and the second judgment bit indicates that the time difference ∆TE is less than half a cycle of the clock signal CLK (i.e., ∆TE < 1), the correction value NCAL generated by the correction circuit 103 is one, and the final count value NFINAL is equal to the initial count value NCNT plus one. When the first judgment bit indicates that the time difference ∆TS is less than half a cycle of the clock signal CLK (i.e., ∆TS < 1) or the second judgment bit indicates that the time difference ∆TE is greater than half a cycle of the clock signal CLK (i.e., ∆TE > 1), the correction value NCAL generated by the correction circuit 103 is zero, and the final count value NFINAL is equal to the initial count value NCNT.
[0013] Figure 3 is a schematic diagram of a correction circuit 103 according to an embodiment of the present invention. As shown in Figure 3, the correction circuit 103 may include a first flip-flop such as flip-flop 301, an exclusive-OR (XOR) gate 302, and a second flip-flop such as flip-flop 303, wherein the exclusive-OR gate 302 is coupled to flip-flop 301, and flip-flop 303 is coupled to exclusive-OR gate 302. In this embodiment, the flip-flop 301 is used to sample the input signal RODIV based on the rising edge of the clock signal CLK to generate a first node signal, such as node signal N1. The mutex gate 302 is used to perform a mutual exclusion OR operation on the input signal RODIV and the node signal N1 to generate a second node signal, such as node signal N2. The flip-flop 303 is used to sample the node signal N2 based on the falling edge of the clock signal CLK to generate a correction signal VCAL. The value of the correction signal VCAL at a first delay time point corresponding to the first time point can represent the first judgment bit, such as judgment bit D1. The value of the correction signal VCAL at a second delay time point corresponding to the second time point can represent the second judgment bit, such as judgment bit D2. The correction circuit 103 may further include a delay circuit such as a combinational logic 304, a fourth flip-flop such as flip-flop 305, a fifth flip-flop such as flip-flop 306, and an output logic 307, wherein flip-flops 305 and 306 are coupled to flip-flops 303 and combinational logic 304, and output logic 307 is coupled to flip-flops 305 and 306. Specifically, combinational logic 304 is used to delay the input signal RODIV to generate a delayed input signal RODDIV, wherein combinational logic 304 delays the first edge of the input signal RODIV at the first time point and the second edge at the second time point to generate a first delay edge of the delayed input signal RODDIV at the first delay time point and a second delay edge at the second delay time point. Additionally, flip-flop 305 is used to sample the correction signal VCAL at the first delay time point based on the first delay edge of the delayed input signal RODDIV to generate judgment bit D1, and flip-flop 306 is used to sample the correction signal VCAL at the second delay time point based on the second delay edge of the delayed input signal RODDIV to generate judgment bit D2, wherein output logic 307 can generate correction value NCAL based on judgment bits D1 and D2.
[0014] Figure 4 is a schematic diagram of the relevant signals (e.g., input signal RODIV, clock signal CLK, node signals N1 and N2, delayed input signal RODDIV, and correction signal VCAL) of the correction circuit 103 according to an embodiment of the present invention under a first condition (e.g., ΔTS > and ΔTE <). In this embodiment, the flip-flop 301 can pull the node signal N1 to the logic value "1" at time t1 in response to the rising edge of the clock signal CLK, and pull the node signal N1 to the logic value "0" at time t2 in response to the rising edge of the clock signal CLK. Since the time difference ΔTS is greater than half a cycle of the clock signal CLK, the node signal N2 has the logic value "1" at time t3, so that the flip-flop 303 can pull the correction signal VCAL to the logic value "1" at time t3 in response to the falling edge of the clock signal CLK. Furthermore, since the time difference ∆TE is less than half a cycle of the clock signal CLK, the node signal N2 has a logic value of "0" at time point t4. This allows the flip-flop 303 to maintain the correction signal VCAL at logic value "0" at time point t4, instead of pulling the correction signal VCAL to logic value "1" at time point t4 in response to the falling edge of the clock signal CLK. Therefore, the flip-flop 305 can output a judgment bit D1 with a logic value of "1" at time point t5 in response to the rising edge of the delayed input signal RODDIV, and the flip-flop 306 can output a judgment bit D2 with a logic value of "0" at time point t6 in response to the falling edge of the delayed input signal RODDIV. The output logic 307 can set the correction value NCAL to one when D1 = 1 and D2 = 0.
[0015] Figure 5 is a schematic diagram of the relevant signals (e.g., input signal RODIV, clock signal CLK, node signals N1 and N2, delayed input signal RODDIV, and correction signal VCAL) of the correction circuit 103 according to an embodiment of the present invention under a second condition (e.g., ΔTS < and ΔTE >). In this embodiment, the flip-flop 301 can pull the node signal N1 to the logic value "1" at time t1 in response to the rising edge of the clock signal CLK, and pull the node signal N1 to the logic value "0" at time t2 in response to the rising edge of the clock signal CLK. Since the time difference ΔTS is less than half a cycle of the clock signal CLK, the node signal N2 has the logic value "0" at time t3, so that the flip-flop 303 can maintain the correction signal VCAL at the logic value "0" at time t3 and will not pull the correction signal VCAL to the logic value "1" at time t3 in response to the falling edge of the clock signal CLK. Furthermore, since the time difference ∆TE is greater than half a cycle of the clock signal CLK, the node signal N2 has a logic value "1" at time point t4, allowing the flip-flop 303 to pull the correction signal VCAL to a logic value "1" at time point t4 in response to the falling edge of the clock signal CLK. Therefore, the flip-flop 305 can output a judgment bit D1 with a logic value "0" at time point t5 in response to the rising edge of the delayed input signal RODDIV, and the flip-flop 306 can output a judgment bit D2 with a logic value "1" at time point t6 in response to the falling edge of the delayed input signal RODDIV. The output logic 307 can set the correction value NCAL to zero when D1 = 0 and D2 = 1.
[0016] Figure 6 is a schematic diagram of the relevant signals (e.g., input signal RODIV, clock signal CLK, node signals N1 and N2, delayed input signal RODDIV, and correction signal VCAL) of the correction circuit 103 according to an embodiment of the present invention under a third condition (e.g., ΔTS < and ΔTE <). In this embodiment, the flip-flop 301 can pull the node signal N1 to the logic value "1" at time t1 in response to the rising edge of the clock signal CLK, and pull the node signal N1 to the logic value "0" at time t2 in response to the rising edge of the clock signal CLK. Since the time difference ΔTS is less than half a cycle of the clock signal CLK, the node signal N2 has the logic value "0" at time t3, so that the flip-flop 303 can maintain the correction signal VCAL at the logic value "0" at time t3 without pulling the correction signal VCAL to the logic value "1" at time t3 in response to the falling edge of the clock signal CLK. Furthermore, since the time difference ∆TE is less than half a cycle of the clock signal CLK, the node signal N2 has a logic value of "0" at time point t4. This allows the flip-flop 303 to maintain the correction signal VCAL at logic value "0" at time point t4, instead of pulling the correction signal VCAL to logic value "1" at time point t4 in response to the falling edge of the clock signal CLK. Therefore, the flip-flop 305 can output a judgment bit D1 with a logic value of "0" at time point t5 in response to the rising edge of the delayed input signal RODDIV, and the flip-flop 306 can output a judgment bit D2 with a logic value of "0" at time point t6 in response to the falling edge of the delayed input signal RODDIV. The output logic 307 can set the correction value NCAL to zero when D1 = 0 and D2 = 0.
[0017] Figure 7 is a schematic diagram of the relevant signals (e.g., input signal RODIV, clock signal CLK, node signals N1 and N2, delayed input signal RODDIV, and correction signal VCAL) of the correction circuit 103 according to an embodiment of the present invention under a fourth condition (e.g., ΔTS > and ΔTE >). In this embodiment, the flip-flop 301 can pull the node signal N1 to the logic value "1" at time t1 in response to the rising edge of the clock signal CLK, and pull the node signal N1 to the logic value "0" at time t2 in response to the rising edge of the clock signal CLK. Since the time difference ΔTS is greater than half a cycle of the clock signal CLK, the node signal N2 has the logic value "1" at time t3, so that the flip-flop 303 can pull the correction signal VCAL to the logic value "1" at time t3 in response to the falling edge of the clock signal CLK. Furthermore, since the time difference ∆TE is greater than half a cycle of the clock signal CLK, the node signal N2 has a logic value "1" at time point t4, allowing the flip-flop 303 to pull the correction signal VCAL to a logic value "1" at time point t4 in response to the falling edge of the clock signal CLK. Therefore, the flip-flop 305 can output a judgment bit D1 with a logic value "1" at time point t5 in response to the rising edge of the delayed input signal RODDIV, and the flip-flop 306 can output a judgment bit D2 with a logic value "1" at time point t6 in response to the falling edge of the delayed input signal RODDIV. The output logic 307 can set the correction value NCAL to zero when D1 = 1 and D2 = 1.
[0018] Figure 8 is a schematic diagram of the workflow of a correction method for time-to-digital conversion of an input signal (e.g., the duration of the high-level or low-level duty cycle of the input signal RODIV shown in Figure 1) according to an embodiment of the present invention, wherein the correction method can be performed by a time-to-digital converter (e.g., the time-to-digital converter 100 shown in Figure 1). It should be noted that the workflow shown in Figure 8 is for illustrative purposes only and is not intended to limit the invention. For example, one or more steps may be added, deleted, or modified in the workflow shown in Figure 8. Furthermore, these steps do not necessarily have to be performed in the exact order shown in Figure 8 if the same result can be obtained.
[0019] In step S810, the time-to-digital converter may use a time counter therein to start counting at a first time point at a first edge of the input signal and end counting at a second time point at a second edge of the input signal to generate an initial count value.
[0020] In step S820, the time-to-digital converter may use a correction circuit therein to generate a first judgment bit based on the first edge of the input signal and the first edge of a clock signal.
[0021] In step S830, the time-to-digital converter can use the correction circuit to generate a second judgment bit based on the second edge of the input signal and a second edge of the clock signal.
[0022] In step S840, the time-to-digital converter can use the correction circuit to generate a correction value based on the first judgment bit and the second judgment bit.
[0023] In step S850, the time-to-digital converter may use an adder therein to add the correction value to the initial count value to generate a final count value.
[0024] In summary, the time-to-digital converter of the present invention can determine whether the initial count value NCNT output by the time counter needs to be corrected (e.g., incremented by one) based on the time difference between the start time point of the measured time length and the rising edge of the clock signal, and the time difference between the end time point of the measured time length and the rising edge of the clock signal, so as to reduce the error of the time-to-digital converter. Furthermore, embodiments of the present invention do not significantly increase additional costs (e.g., circuit area, power consumption, etc.). Therefore, the present invention can improve the overall performance of the time-to-digital converter without or with minimal side effects. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made within the scope of the claims of the present invention should be considered within the scope of the present invention. [Simplified Explanation of the Diagram]
[0025] Figure 1 is a schematic diagram of an electronic device including a time-to-digital converter according to an embodiment of the present invention. Figure 2 is a schematic diagram of the concept of time-to-digital conversion according to an embodiment of the present invention. Figure 3 is a schematic diagram of a correction circuit according to an embodiment of the present invention. Figure 4 is a schematic diagram of the relevant signals of the correction circuit according to an embodiment of the present invention in a first state. Figure 5 is a schematic diagram of the relevant signals of the correction circuit according to an embodiment of the present invention in a second state. Figure 6 is a schematic diagram of the relevant signals of the correction circuit according to an embodiment of the present invention in a third state. Figure 7 is a schematic diagram of the relevant signals of the correction circuit according to an embodiment of the present invention in a fourth state. Figure 8 is a schematic diagram of the workflow of a correction method for performing time-to-digital conversion on an input signal according to an embodiment of the present invention.
Claims
1. A time-to-digital converter, comprising: a time counter configured to start counting at a first time point on a first edge of an input signal and end counting at a second time point on a second edge of the input signal to generate an initial count value; a correction circuit configured to generate a first determination bit based on the first edge of the input signal and a first edge of a clock signal, generate a second determination bit based on the second edge of the input signal and a second edge of the clock signal, and generate a correction value based on the first determination bit and the second determination bit; and an adder coupled to the time counter and the correction circuit configured to add the correction value to the initial count value to generate a final count value.
2. The time-to-digital converter as described in claim 1, wherein the first determination bit indicates whether a first time difference between the first edge of the input signal and the first edge of the clock signal is greater than half a period of the clock signal, and the second determination bit indicates whether a second time difference between the second edge of the input signal and the second edge of the clock signal is greater than half a period of the clock signal.
3. The time-to-digital converter as described in claim 2, wherein when the first determination bit indicates that the first time difference is greater than the half-cycle of the clock signal and the second determination bit indicates that the second time difference is less than the half-cycle of the clock signal, the correction value generated by the correction circuit is one.
4. The time-to-digital converter as described in claim 2, wherein the correction value generated by the correction circuit is zero when the first determination bit indicates that the first time difference is less than half a cycle of the clock signal or the second determination bit indicates that the second time difference is greater than half a cycle of the clock signal.
5. The time-to-digital converter as described in claim 1, wherein the initial count value represents the number of rising edges of the clock signal during a counting period between the first time point and the second time point, the first edge of the clock signal represents a first rising edge of the clock signal after the first edge of the input signal, and the second edge of the clock signal represents a first rising edge of the clock signal after the second edge of the input signal.
6. The time-to-digital converter as described in claim 1, wherein the initial count value represents the number of falling edges of the clock signal during a counting period between the first time point and the second time point, the first edge of the clock signal represents a first falling edge of the clock signal after the first edge of the input signal, and the second edge of the clock signal represents a first falling edge of the clock signal after the second edge of the input signal.
7. The time-to-digital converter as described in claim 1, wherein the correction circuit comprises: a first flip-flop for sampling the input signal based on the rising edge of the clock signal to generate a first node signal; a mutex OR gate coupled to the first flip-flop for performing a mutex OR operation on the input signal and the first node signal to generate a second node signal; and a second flip-flop coupled to the mutex OR gate for sampling the second node signal based on the falling edge of the clock signal to generate a correction signal, wherein the value of the correction signal at a first delay time point corresponding to the first time point represents the first decision bit, and the value of the correction signal at a second delay time point corresponding to the second time point represents the second decision bit.
8. The time-to-digital converter as described in claim 7, wherein the correction circuit further comprises: a delay circuit for delaying the input signal to generate a delayed input signal, wherein the delay circuit delays the first edge and the second edge of the input signal respectively to generate a first delayed edge and a second delayed edge of the delayed input signal; a fourth flip-flop coupled to the second flip-flop and the delay circuit for sampling the correction signal at a first delay time point based on the first delayed edge of the delayed input signal to generate the first determination bit; and a fifth flip-flop coupled to the second flip-flop and the delay circuit for sampling the correction signal at a second delay time point based on the second delayed edge of the delayed input signal to generate the second determination bit.
9. A correction method for performing time-to-digital conversion on an input signal, comprising: starting counting at a first time point on a first edge of the input signal and ending counting at a second time point on a second edge of the input signal to generate a preliminary count value; generating a first determination bit based on the first edge of the input signal and a first edge of a clock signal; generating a second determination bit based on the second edge of the input signal and a second edge of the clock signal; generating a correction value based on the first determination bit and the second determination bit; and adding the correction value to the preliminary count value to generate a final count value.
10. The correction method as described in claim 9, wherein the first determination bit indicates whether a first time difference between the first edge of the input signal and the first edge of the clock signal is greater than half a period of the clock signal, and the second determination bit indicates whether a second time difference between the second edge of the input signal and the second edge of the clock signal is greater than half a period of the clock signal.