Mark-live instruction

Abstract

An apparatus comprises instruction decoding circuitry configured to decode instructions; and processing circuitry configured to perform data processing in response to the instructions decoded by the instruction decoding circuitry. Cache control circuitry is configured to set, in response to the instruction decoding circuitry decoding a mark-live instruction specifying mark-live target address information, discard-eligibility metadata associated with one or more target cache lines selected based on the mark-live target address information, to identify the one or more target cache lines as being eligible for being treated as a discardable cache line which is allowed to be discarded without data writeback even if the discardable cache line is dirty. In response to a mark-dead event associated with a given cache line, the cache control circuitry determines depending on the discard-eligibility metadata for the given cache line whether the given cache line is eligible for becoming a discardable cache line.

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