Nested Loop Instruction Buffer and Processor

Abstract

This application relates to an instruction buffer and processor for nested loops, wherein the processor includes an instruction dispatch unit, a control state register, and a processing engine. The instruction buffer for nested loops is configured to: obtain instructions from the instruction dispatch unit; obtain one or more loop count indices associated with one or more nested loops in the instructions by decoding the instructions; obtain one or more loop counts associated with one or more loop count indices from the control state register; and send one or more nested loops to the processing engine based on the one or more loop counts associated with one or more loop count indices.

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