Electronic system and electronic system execution method
Patent Information
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- MITAC COMPUTING TECH
- Filing Date
- 2025-01-16
- Publication Date
- 2026-08-01
AI Technical Summary
The increasing tasks handled by Baseboard Management Controller (BMC) and Complex Programmable Logic Device (CPLD) in servo systems lead to frequent control pin shortages, causing CPLD to execute unexpected tasks and jeopardizing system stability.
Implementing an electronic system with a substrate management controller and programmable logic unit connected via signal pins, where the programmable logic unit detects signal levels to determine the appropriate address for executing different operating modes, ensuring correct task execution.
This method prevents CPLD from performing erroneous operations by accurately determining the address based on signal levels, thereby maintaining system stability and avoiding unexpected work.
Smart Images
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Abstract
Description
[Technical Field]
[0001] The present invention relates to a method for avoiding the execution of erroneous instructions by a hardware device, and more particularly to a method for avoiding the execution of erroneous instructions by a programmable logic unit (CPLD). [Previous Technology]
[0002] In a servo system architecture, the Baseboard Management Controller (BMC) is responsible for the overall management of the system and works in conjunction with the Complex Programmable Logic Device (CPLD) to manage the servo system and its input / output (I / O) control. However, with the advent of the artificial intelligence era, the tasks that the Baseboard Management Controller and the CPLD need to handle are increasing, leading to a frequent shortage of control pins between them.
[0003] Furthermore, designers typically use a serial communication bus to enable complex programmable logic units (CPLDs) to perform multiple tasks. For example, the baseboard management controller (BMC) generates an execution request containing the address number corresponding to the target task and transmits the execution request to the CPLD to control it to execute the task corresponding to the address number. However, under this serial communication architecture, the CPLD may still execute unexpected tasks, leading to system errors and posing a potential risk to the stability of the overall system.
[0004] In view of this, it is necessary to seek a solution to effectively avoid system errors caused by programmable logic units performing unexpected work. [Summary of the Invention]
[0005] Therefore, the object of the present invention is to provide a method for avoiding programmable logic units from performing erroneous operations.
[0006] Thus, the electronic system execution method of the present invention is implemented by an electronic system, the electronic system including a baseboard management controller and a programmable logic unit electrically connected to the baseboard management controller, the baseboard management controller having a first signal pin and a second signal pin respectively connected to the programmable logic unit, the programmable logic unit being able to execute a first operating mode according to a first address, the programmable logic unit being able to execute a second operating mode according to a second address, the electronic system execution method including a step (A), a step (B), a step (C), and a step (D).
[0007] Step (A) is that the substrate management controller executes a first module and sets the second signal pin to a low level signal, or the substrate management controller executes a second module and sets the second signal pin to a high level signal.
[0008] Step (B) is that the programmable logic unit detects the level signal from the second signal pin and determines whether the high level signal is detected.
[0009] Step (C) is when step (B) is determined to be no, the programmable logic unit detects that the level signal from the second signal pin is the low level signal, and the programmable logic unit executes an address switching program, and uses the first address as an address to be executed according to the low level signal, and the programmable logic unit can execute the first working mode according to the address to be executed.
[0010] Step (D) is when step (B) is determined to be yes, the programmable logic unit detects that the level signal from the second signal pin is the high level signal, the programmable logic unit executes the address switching program, and uses the second address as the address to be executed according to the high level signal, and the programmable logic unit can execute the second working mode according to the address to be executed.
[0011] Another object of the present invention is to provide a system for avoiding erroneous operation of programmable logic units.
[0012] Thus, the electronic system of the present invention includes a substrate management controller and a programmable logic unit electrically connected to the substrate management controller.
[0013] The board management controller includes a first signal pin and a second signal pin.
[0014] The programmable logic unit can execute a first working mode according to a first address, and the programmable logic unit can execute a second working mode according to a second address. The board management controller is electrically connected to the programmable logic unit through the first signal pin and the second signal pin.
[0015] Wherein, the substrate management controller executes a first module and sets the second signal pin to a low level signal, or the substrate management controller executes a second module and sets the second signal pin to a high level signal. The programmable logic unit detects the level signal from the second signal pin and determines whether the high level signal is detected. When the programmable logic unit detects that the level signal from the second signal pin is the low level signal, the programmable logic unit executes a... The address switching program uses the low-level signal as the first address to be executed. The programmable logic unit can execute the first working mode according to the address to be executed. When the programmable logic unit detects that the level signal from the second signal pin is the high-level signal, the programmable logic unit executes the address switching program and uses the high-level signal as the second address to be executed. The programmable logic unit can execute the second working mode according to the address to be executed.
[0016] The advantage of the present invention is that: by using the programmable logic unit to detect the level signal from the second signal pin of the substrate management controller and determine whether it is a high level signal or a low level signal, and in conjunction with the execution of the address switching program, the programmable logic unit can use the first address as the address to be executed based on the low level signal or the second address as the address to be executed based on the high level signal. This effectively achieves the goal that after the programmable logic unit detects the level signal from the second signal pin of the substrate management controller, it can first determine the address to be executed, thereby ensuring that the corresponding working mode can be executed subsequently, and thus avoiding the programmable logic unit from performing unexpected work.
Implementation Method
[0017] Before the present invention is described in detail, it should be noted that similar elements are represented by the same numbers in the following description.
[0018] Referring to FIG1, one embodiment of the electronic system execution method of the present invention is implemented by an electronic system 100. The electronic system 100 includes a baseboard management controller 1 (BMC) and a complex programmable logic device 2 (CPLD) electrically connected to the baseboard management controller 1.
[0019] The baseboard management controller 1 includes a first signal pin and a second signal pin.
[0020] The programmable logic unit 2 stores a first preset address and a second preset address, and includes a first logic pin and a second logic pin. The first logic pin is electrically connected to the first signal pin, and the second logic pin is electrically connected to the second signal pin. The programmable logic unit 2 can execute a first operating mode according to the first address, and the programmable logic unit 2 can execute a second operating mode according to the second address.
[0021] It is worth noting that, in this embodiment, both the first signal pin and the first logic pin are pins based on the serial communication bus 800, and both the second signal pin and the second logic pin are pins based on the general-purpose input / output interface 900 (GPIO). The first operating mode is used to access any register of the programmable logic unit 2, and the second operating mode is used to update the programmable logic unit 2, but is not limited thereto.
[0022] Further, when the substrate management controller 1 executes a first module, the substrate management controller 1 transmits a low-level signal to the second logic pin through the second signal pin, and also generates a first working instruction, and transmits the first working instruction to the first logic pin through the first signal pin; when the substrate management controller 1 executes a second module, the substrate management controller 1 transmits a high-level signal to the second logic pin through the second signal pin, and also generates a second working instruction, and transmits the second working instruction to the first logic pin through the first signal pin. The first working instruction includes the first address, and the second working instruction includes the second address.
[0023] The serial communication bus 800 may be an integrated bus circuit (I²C), but is not limited thereto.
[0024] Referring to FIG2, the operation details of each component in the electronic system 100 will be described below with reference to this embodiment of the electronic system execution method of the present invention. The electronic system execution method includes S101 to S108.
[0025] In step S101, when the substrate management controller 1 executes the first module to transmit the low-level signal to the programmable logic unit 2 through the second signal pin, then continues to execute the first module to generate the first working instruction, and transmits the first working instruction to the programmable logic unit 2 through the first signal pin; or, when the substrate management controller 1 executes the second module to transmit the high-level signal to the programmable logic unit 2 through the second signal pin, then continues to execute the second module to generate the second working instruction, and transmits the second working instruction to the programmable logic unit 2 through the first signal pin. In other words, when the substrate management controller 1 wants to control the programmable logic unit 2 to execute the first working mode, in addition to controlling the second signal pin to transmit the low-level signal to the second logic pin, it also transmits the first working instruction to the first logic pin through the first signal pin; and when the substrate management controller 1 wants to control the programmable logic unit 2 to execute the second working mode, in addition to controlling the second signal pin to transmit the high-level signal to the second logic pin, it also transmits the second working instruction to the first logic pin through the first signal pin.
[0026] In step S102, the programmable logic unit 2 determines whether the level signal received through the second logic pin is a high-level signal. When the programmable logic unit 2 determines that the level signal received through the second logic pin is not a high-level signal but a low-level signal, the process step S103 is performed; when the programmable logic unit 2 determines that the level signal received through the second logic pin is a high-level signal, the process step S106 is performed.
[0027] In step S103, the programmable logic unit 2 executes an address switching program, and uses the first address as an address to be executed according to the low-level signal. The programmable logic unit 2 can execute the first operating mode according to the address to be executed (i.e., the first address). Specifically, the programmable logic unit 2 executes the address switching program and, according to the low-level signal, adjusts the setting value of at least one of the multiple bits included in the first preset address, and makes the adjusted first preset address correspond to the first address. For example, the first preset address is composed of 8 bits, namely "A7 A6 A5 A4 A3 A2 A1 A0", and is "0000 0011" (hexadecimal: 0x03). The programmable logic unit 2 then executes the address switching program to adjust the preset value of the A2 bit to "0" according to the low level signal, thereby obtaining the first address as "0000 0 "0"11" (hexadecimal: 0x03), but this example is not the only one.
[0028] In step S104, the programmable logic unit 2 determines whether it has received the first working instruction from the substrate management controller 1 through the first logic pin. When the programmable logic unit 2 determines that it has received the first working instruction from the substrate management controller 1 through the first logic pin, it proceeds to process step S105; when the programmable logic unit 2 determines that it has not yet received the first working instruction from the substrate management controller 1 through the first logic pin, it returns to process step S104.
[0029] In step S105, the programmable logic unit 2 executes the first working mode according to the address to be executed. The first working mode is used to access any register of the programmable logic unit 2. In summary, after receiving the low-level signal through the second logic pin, the programmable logic unit 2 first executes the address switching program and pre-sets the first address as the address to be executed, and waits to receive the first working instruction. Only after receiving the first working instruction does it begin executing the first working mode corresponding to the address to be executed.
[0030] In step S106, the programmable logic unit 2 executes the address switching program and uses the second address as the address to be executed according to the high-level signal. The programmable logic unit 2 can execute the second operating mode according to the address to be executed (i.e., the second address). Specifically, the programmable logic unit 2 executes the address switching program and adjusts the setting value of at least one of the multiple bits included in the second preset address according to the high-level signal, making the adjusted second preset address correspond to the second address. For example, if the second preset address is "0000 0010" (hexadecimal: 0x02), the programmable logic unit 2 adjusts the preset value of bit A2 to "1" according to the high-level signal by executing the address switching program, thereby obtaining the second address as "0000 0 "1" 10" (hexadecimal: 0x06).
[0031] In step S107, the programmable logic unit 2 determines whether it has received the second working instruction from the substrate management controller 1 through the first logic pin. When the programmable logic unit 2 determines that it has received the second working instruction from the substrate management controller 1 through the first logic pin, it proceeds to process step S108; when the programmable logic unit 2 determines that it has not yet received the second working instruction from the substrate management controller 1 through the first logic pin, it returns to process step S107.
[0032] In step S108, the programmable logic unit 2 executes the second operating mode according to the address to be executed. The second operating mode is used to perform updates to the programmable logic unit 2. In summary, after receiving the high-level signal through the second logic pin, the programmable logic unit 2 first executes the address switching program and pre-sets the second address as the address to be executed, and waits to receive the second operating instruction. Only after receiving the second operating instruction does it begin executing the second operating mode corresponding to the address to be executed.
[0033] In summary, the electronic system execution method of the present invention uses a programmable logic unit 2 to determine the level signal received by the second logic pin. When a high-level signal is received, the first address is first used as the address to be executed, and after receiving the first working instruction, the first working mode is executed. Conversely, when a low-level signal is received, the second address is first used as the address to be executed, and after receiving the second working instruction, the second working mode is executed. In this way, the programmable logic unit 2 can execute the corresponding working mode according to the address to be executed, thereby avoiding the programmable logic unit 2 from performing unexpected work, and thus effectively achieving the purpose of the present invention.
[0034] However, the above description is only an embodiment of the present invention and should not be construed as limiting the scope of the present invention. Any simple equivalent changes and modifications made in accordance with the scope of the patent application and the contents of the patent specification of the present invention shall still fall within the scope of the patent of the present invention. [Simplified Explanation of the Diagram]
[0035] Other features and effects of the present invention will be clearly presented in the embodiments with reference to the drawings, wherein: FIG1 is a block diagram illustrating an electronic system for performing one embodiment of the electronic system execution method of the present invention; and FIG2 is a flowchart illustrating the embodiment of the electronic system execution method of the present invention.
Claims
1. An electronic system execution method, implemented by an electronic system, the electronic system comprising a baseboard management controller and a programmable logic unit electrically connected to the baseboard management controller, the baseboard management controller having a first signal pin and a second signal pin respectively connected to the programmable logic unit, the programmable logic unit being executable in a first operating mode according to a first address, the programmable logic unit being executable in a second operating mode according to a second address, the electronic system execution method comprising the following steps: (A) the baseboard management controller executes a first module and sets the second signal pin to a low level signal, or the baseboard management controller executes a second module and sets the second signal pin to a high level signal; (B) the programmable logic unit detects a level signal from the second signal pin and determines whether the high level signal is detected; (C) When step (B) is determined to be negative, the programmable logic unit detects that the level signal from the second signal pin is the low level signal, and the programmable logic unit executes an address switching program, and uses the first address as an address to be executed according to the low level signal. The programmable logic unit can execute the first working mode according to the address to be executed; and (D) when step (B) is determined to be positive, the programmable logic unit detects that the level signal from the second signal pin is the high level signal, the programmable logic unit executes the address switching program, and uses the second address as the address to be executed according to the high level signal. The programmable logic unit can execute the second working mode according to the address to be executed.
2. The electronic system execution method as described in claim 1, wherein the programmable logic unit has a first logic pin connected to the first signal pin of the substrate management controller, and a second logic pin connected to the second signal pin of the substrate management controller, wherein, In step (A), after the substrate management controller executes the first module to set the second signal pin to the low level signal and transmits the low level signal to the second logic pin through the second signal pin, the substrate management controller continues to execute the first module to generate a first working instruction and transmits the first working instruction to the first logic pin through the first signal pin; or after the substrate management controller executes the second module to set the second signal pin to the high level signal and transmits the high level signal to the second logic pin through the second signal pin, the substrate management controller continues to execute the second module to generate a second working instruction and transmits the second working instruction to the first logic pin through the first signal pin; after step (C), the following step is further included: (E) After receiving the first working instruction through the first logic pin, the programmable logic unit executes the first working mode according to the address to be executed; and after step (D), the following step is further included: (F) After receiving the second working instruction through the first logic pin, the programmable logic unit executes the second working mode according to the address to be executed.
3. The electronic system execution method as described in claim 2, wherein, In step (A), the first signal pin and the first logic pin are both pins based on a serial communication bus, and the second signal pin and the second logic pin are both pins based on a general-purpose input / output interface.
4. The electronic system execution method as described in claim 1, wherein the programmable logic unit stores a first preset address and a second preset address, wherein, In step (C), the programmable logic unit executes the address switching program and adjusts the setting value of at least one of the multiple bits contained in the first preset address according to the low level signal, and makes the adjusted first preset address correspond to the first address; and in step (D), the programmable logic unit executes the address switching program and adjusts the setting value of at least one of the multiple bits contained in the second preset address according to the high level signal, and makes the adjusted second preset address correspond to the second address.
5. The electronic system execution method as described in claim 1, wherein, In step (C), the first operating mode is used to perform access to any register of the programmable logic unit; and in step (D), the second operating mode is used to perform an update of the programmable logic unit.
6. An electronic system comprising: a baseboard management controller including a first signal pin and a second signal pin; and a programmable logic unit (PLU), wherein the baseboard management controller is electrically connected to the PLU via the first signal pin and the second signal pin, the PLU being operable to execute a first operating mode according to a first address, and the PLU being operable to execute a second operating mode according to a second address; wherein... The substrate management controller executes a first module and sets the second signal pin to a low level signal, or the substrate management controller executes a second module and sets the second signal pin to a high level signal. The programmable logic unit (PLU) detects the level signal from the second signal pin and determines whether a high level signal is detected. When the PLU detects that the level signal from the second signal pin is a low level signal, the PLU executes an address switching program and uses the first address as a pending address based on the low level signal. The PLU can then execute the first operating mode according to the pending address. When the programmable logic unit detects that the level signal from the second signal pin is the high level signal, the programmable logic unit executes the address switching program and uses the second address as the address to be executed according to the high level signal. The programmable logic unit can execute the second working mode according to the address to be executed.
7. The electronic system as claimed in claim 6, wherein, The programmable logic unit includes a first logic pin and a second logic pin. The first logic pin is electrically connected to the first signal pin, and the second logic pin is electrically connected to the second signal pin. After the substrate management controller executes the first module to set the second signal pin to a low level signal and transmits the low level signal to the second logic pin through the second signal pin, the substrate management controller continues to execute the first module to generate a first operating instruction and transmits the first operating instruction to the first logic pin through the first signal pin. Alternatively, after the substrate management controller executes the second module to set the second signal pin to a high level signal and transmits the high level signal to the second logic pin through the second signal pin, the substrate management controller continues to execute the second module to generate a second operating instruction and transmits the second operating instruction to the first logic pin through the first signal pin. After receiving the first working instruction through the first logic pin, the programmable logic unit executes the first working mode according to the address to be executed. After receiving the second working instruction through the first logic pin, the programmable logic unit executes the second working mode according to the address to be executed.
8. The electronic system as claimed in claim 7, wherein, Both the first signal pin and the first logic pin are pins based on a serial communication bus, while both the second signal pin and the second logic pin are pins based on a general-purpose input / output interface.
9. The electronic system as claimed in claim 6, wherein, The programmable logic unit (PLU) stores a first preset address and a second preset address. When the PLU detects that the level signal from the second signal pin is a low level signal, the PLU executes the address switching program and adjusts the setting value of at least one of the multiple bits contained in the first preset address according to the low level signal, and makes the adjusted first preset address correspond to the first address. When the PLU detects that the level signal from the second signal pin is a high level signal, the PLU executes the address switching program and adjusts the setting value of at least one of the multiple bits contained in the second preset address according to the high level signal, and makes the adjusted second preset address correspond to the second address.
10. The electronic system as claimed in claim 6, wherein, The first operating mode is used to access any register of the programmable logic unit, and the second operating mode is used to perform updates to the programmable logic unit.