Memory controller

Abstract

This invention aims to improve the performance of a memory system. The memory system of the embodiment includes non-volatile memory and a memory controller. The non-volatile memory comprises a plurality of physical complete blocks, and within each of the plurality of physical complete blocks, a plurality of physical sub-blocks each contain memory cells, which are connected in series or in parallel to the same bit line. The memory controller independently performs data erasure operations on each of the plurality of physical sub-blocks within the plurality of physical complete blocks, and sets all of the plurality of physical sub-blocks to the same memory mode within the plurality of physical complete blocks. The memory mode represents the setting state of the number of bits of data stored in the memory cells contained in each of the plurality of physical sub-blocks; the same number of bits of data are stored in the memory cells contained in physical sub-blocks set to the same memory mode.

Images