Sparse compute-in-memory tensor core

Abstract

A compute-in-memory (CIM) tensor core includes a memory, a control circuit, and a plurality of processing units (PUs) organized in a 2-dimensional (2D) mesh network. Each PU includes a first circuit configured for low-precision (LP) compute-in-memory (CIM) operations. Additionally, a subset of PUs within a central region of the 2D mesh network further includes a second circuit configured for high-precision (HP) CIM operations, in addition to the LP circuit. This architecture enables integrated storage and computation within the same hardware units, reducing data movement and improving processing efficiency.

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