Semiconductor memory devices

Abstract

This invention provides a semiconductor memory device that can shorten processing time. The semiconductor memory device of the embodiment includes: a first wiring layer, a second wiring layer, and a plurality of third wiring layers, which are arranged sequentially and separately in a first direction; a memory column extending in the first direction, the portion of which intersects with the first wiring layer functions as a first memory cell; and a control circuit that controls the readout operation of data stored in the first memory cell; and during the readout operation, the control circuit performs: a first operation, which causes the voltage of the plurality of third wiring layers to change from a first voltage to a second voltage higher than the first voltage with a first gradient; a second operation, which causes the voltage of the second wiring layer to change from a first voltage to a third voltage higher than the second voltage with a second gradient larger than the first gradient; and a third operation, which causes the voltage of the first wiring layer to change to a fourth voltage corresponding to the readout level of the first memory cell.