Memory device

Abstract

This invention provides a high-speed memory device. One embodiment of the memory device includes a bit line, a source line, a first cell transistor between the bit line and the source line, a second cell transistor between the first cell transistor and the bit line, a third cell transistor between the first cell transistor and the source line, a first word line connected to the gate of the first cell transistor, a second word line connected to the gate of the second cell transistor, and a third word line connected to the gate of the third cell transistor. A first voltage is applied to the source line during a first period. At a first moment within the first period, a second voltage greater than or equal to the threshold voltage of the first, second, and third cell transistors is applied to at least one of the second and third word lines. At a second moment later than the first moment within the first period, a third voltage greater than or equal to the threshold voltage of the first, second, and third cell transistors is applied to the first word line.

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