Semiconductor memory devices

Abstract

This invention provides a semiconductor memory device capable of improving processing power. According to an embodiment, the semiconductor memory device includes: a plurality of memory strings, each containing a plurality of memory cells, the plurality of memory cells being stacked at intervals along a first direction, arranged in a second direction, and connected in series by current paths; word lines connected to the plurality of first memory cells stacked at intervals along the first direction; and a plurality of bit lines. The plurality of memory cells are capable of storing data corresponding to any one of a plurality of states. During programming, the plurality of states are classified into a plurality of groups, and the column decoder applies a plurality of pulse voltages corresponding to each of the plurality of groups to the word lines. During programming verification, the column decoder applies a plurality of verification voltages corresponding to each of the plurality of states to the word lines.

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