Memory device and programming method thereof

Abstract

A memory device and a programming method thereof are provided. The memory device is, for example a three dimensional NAND flash memory circuit, and provides a storage media with high-performance and high-capacity. The programming method includes: after a first program operation on a plurality of memory planes of the memory device, performing a program verify operation on each of the memory planes; performing a second program operation on each of the memory planes of the memory device, and performing an error bit count detection operation accompanying the second program operation to determine at least one verified plane of the memory planes; and disabling accessing operation on the at least one verified plane.

Description

[Technical Field]

[0001] This invention relates to a memory device and a programming method thereof, and more particularly to a memory device and a programming method thereof that can reduce the interaction interference between memory planes during the programming process. [Previous Technology]

[0002] To improve the data writing efficiency of memory devices, a multi-plane memory device has been proposed. In this multi-plane memory device, when programming operations are performed on memory planes, in the prior art, a single control circuit can be used to program all memory planes. Under this approach, due to differences in electrical characteristics between memory planes, some memory planes may complete the programming verification relatively early. However, in the prior art, memory devices require continuous programming operations on all memory planes until all memory planes have completed the programming verification. As a result, memory planes that complete the programming verification relatively early will still be subject to the bias voltage of the programming operation after passing the verification, causing interference to the characteristics of the memory cells within them. [Summary of the Invention]

[0003] The present invention provides a memory device and a programming method thereof, which can reduce interference caused by different completion rates of programming actions on the memory plane.

[0004] The programming method of the present invention includes: performing a programming verification operation on each memory plane of the memory device after a first programming operation on a plurality of memory planes of the memory device; performing a second programming operation on each memory plane of the memory device, and performing an error bit count detection operation along with the second programming operation to determine that at least one of the memory planes has passed the verification; and closing the access operation of the at least one memory plane that has passed the verification.

[0005] The memory device of the present invention includes a plurality of memory planes and a control circuit. The control circuit is coupled to the memory planes. The control circuit is configured to: perform a programmed verification operation on each memory plane of the memory device after a first programmed operation on the plurality of memory planes of the memory device; perform a second programmed operation on each memory plane of the memory device, and perform an error bit count detection operation accompanied by the second programmed operation, so as to determine that at least one of the memory planes has passed the verification; and disable the access operation of the at least one memory plane that has passed the verification.

[0006] Based on the above, in this embodiment of the invention, after the first programmed action and the corresponding programmed verification action in the memory device, an error bit detection action is performed in subsequent programmed actions. Through the error bit detection action, one or more memory planes that have passed verification can be identified from among multiple memory planes. After a memory plane that has passed verification is identified, it is closed, and subsequent programmed actions will not access or access it. In this way, the memory plane that passes verification quickly can avoid interference from subsequent programmed actions, maintaining the stability of the programmed memory plane.

Implementation Method

[0007] Please refer to Figure 1, which illustrates a flowchart of a programming method for a memory device according to an embodiment of the present invention. The memory device has multiple memory planes. In step S110, a first programming operation is performed on the multiple memory planes of the memory device. After the first programming operation, a programming verification operation is performed on each memory plane of the memory device. Next, in step S120, a second programming operation is performed on the multiple memory planes that have failed verification. In the second programming operation, an error bit count detection operation is performed on the multiple memory planes to detect whether the multiple memory planes have one or more verified memory planes. Specifically, the error bit count detection (FBD) operation is used to detect the number of memory cells that have not been programmed in each memory plane, i.e., the number of error bits. When the number of error bits detected in a detected memory plane is lower than a preset threshold, the detected memory plane can be set as a verified memory plane.

[0008] In step S130, the access operation of at least one verified memory plane determined in step S120 is turned off. Simultaneously, if one or more memory planes fail verification, these failed verification memory planes need to undergo subsequent programming operations and error bit count detection operations. Therefore, by turning off at least one verified memory plane, the subsequent programming operations and error bit count detection operations will not interfere with the at least one verified memory plane, allowing the electrical characteristics of the memory cells on the at least one verified memory plane to remain in a stable programmed state, preventing procedural issues from occurring.

[0009] Furthermore, in this embodiment of the invention, by shutting down at least one verified memory plane, the number of memory planes targeted in subsequent programmed actions and error bit detection actions can be reduced, which can effectively reduce the required power consumption and achieve the effect of energy saving and carbon reduction.

[0010] Please refer to FIG2 below. FIG2 illustrates a flowchart of a programming method for a memory device according to another embodiment of the present invention. FIG2 is a flowchart of programming operations for multiple memory planes of a memory device having multiple memory planes. In step S210, a first programming operation is performed for multiple memory planes. Next, in step S220, a programming verification operation is performed corresponding to the programming operation in step S210 to verify the programming state of each memory plane. It is worth mentioning that in this embodiment, the programming verification operation can be performed for multiple layers where the critical voltage of each memory cell is located. That is, the memory cell in the memory device can be a flash memory cell of a multi-level storage unit. Furthermore, step S220 can be a programming verification operation for each memory plane performed corresponding to one of the multiple layers.

[0011] In step S230, the error bit count detection action and the corresponding programmed verification action in step S210 are executed simultaneously. In the error bit count detection action and the programmed verification action, if a memory plane is found to have passed verification, the corresponding memory plane that has passed verification can be closed. Specifically, for each memory plane, when the verification results of the error bit count detection actions from the first level to the target level are all passed, each detected memory plane can be a memory plane that has passed verification.

[0012] On the other hand, in step S230, the verified memory plane can be masked to isolate it from receiving related signals of subsequent programmed actions, programmed verification actions, and error bit count detection actions.

[0013] In step S240, it is determined whether all memory planes have passed the error bit count detection action. If the determination result of step S240 is yes, step S250 can be executed; otherwise, if the determination result is no, it is necessary to return to step S220.

[0014] In step S250, it can be determined whether the error bit count detection action performed in step S230 corresponds to the target level in the storage level of the memory cell. If the determination result of step S250 is yes, the current multi-memory plane programmable action can be ended; conversely, if the determination result of step S250 is no, the level corresponding to the error bit count detection action can be incremented by 1, and step S220 can be re-executed to perform the error bit count detection action of the next level.

[0015] Please note that the target level in step S250 can be, for example, the last level in the storage hierarchy of the memory cell. For example, if the storage hierarchy of the memory cell is level A to level G, where level A to level G correspond to a plurality of sequentially increasing critical voltage ranges, level G can be the last level (highest level) in the storage hierarchy. In this embodiment, the target level can be any of level A to level G, which can be set by the engineer and is not subject to any certain restrictions.

[0016] In addition, the hierarchical increment action in step S260 can cause the error bit detection action to be raised from the hierarchical level corresponding to the relatively low critical voltage range to the hierarchical level corresponding to the higher critical voltage range, for example, changing from hierarchical level A to hierarchical level B, or changing from hierarchical level B to hierarchical level C.

[0017] Incidentally, the target layer mentioned above can also be a combination of multiple layers. When the error bit count detection actions of multiple target layers in each memory plane all pass, each memory plane can be set as a verified memory plane.

[0018] In addition, in other embodiments of the present invention, when it is determined that one or more memory planes in the memory planes are verified memory planes, the memory device may provide multiple programmed pulses to the verified memory planes and then perform a shutdown operation on the verified memory planes to ensure that the verified memory planes have completed the programmed operation.

[0019] Please refer to Figure 3 below. Figure 3 illustrates a flowchart detailing the implementation of a programming method for a memory device according to an embodiment of the present invention. In Figure 3, the controller of the memory device can execute a control flow, wherein the error bit detection circuit can perform a corresponding error bit detection action in accordance with the control flow. The memory device may have multiple memory planes.

[0020] Step S311 is the high voltage setting process HVSET in the memory device, and the subsequent step S312 is the programmed action process PGM. Step S313 is the programmed verification action process PV. Correspondingly, the error bit count detection circuit can be synchronized with step S313 to perform the programmed verification action of the corresponding level A.

[0021] Next, step S314 is another programmed action flow PGM, where the error bit count detection circuit executes the corresponding level B smart skip program verification action SSPV_B and the corresponding level A error bit count detection action FBD_A. Taking the example that both the level B smart skip program verification action SSPV_B and the level A error bit count detection action FBD_A in step S314 fail, in step S315, the next programmed verification action flow PV is entered, and in step S316, another programmed action flow PGM is executed.

[0022] Corresponding to step S315, the error bit count detection circuit can again execute the programmed verification action PVA of the corresponding layer A. Corresponding to step S316, the error bit count detection circuit can again execute the fast-skip programmed verification action SSPV_B of the corresponding layer B and the error bit count detection action FBD_A of the corresponding layer A. For example, the verification result of the fast-skip programmed verification action SSPV_B of layer B corresponding to step S316 is pass, while the error bit count detection action FBD_A of the corresponding layer A is fail, for example.

[0023] After completing step S316, the process can proceed to node N1.

[0024] Continuing from node N1, in step S321, the flow control is a programmed verification action flow. In step S321, the error bit count detection circuit can execute programmed verification actions PVA and PVB corresponding to levels A and B, respectively. In step S322, the flow control is a programmed action flow PGM, and the error bit count detection circuit can execute the fast-skip programmed verification action SSPV_C corresponding to level C and the error bit count detection action FBD_A corresponding to level A. In this embodiment, the fast-skip programmed verification action SSPV_C corresponding to level C and the error bit count detection action FBD_A corresponding to level A are, for example, both passed.

[0025] Steps S323 and S325 are the programmed verification action flow PV, and step S324 is the programmed action flow PGM. Corresponding to step S323, the error bit count detection circuit can execute programmed verification actions PVB and PVC corresponding to levels B and C respectively. Corresponding to step S324, the error bit count detection circuit can execute the fast-skip programmed verification action SSPV_D corresponding to level D and the error bit count detection action FBD_B corresponding to level B. In this embodiment, the fast-skip programmed verification action SSPV_D and the error bit count detection action FBD_B are both, for example, passed. Corresponding to step S325, the error bit count detection circuit can execute programmed verification actions PVC and PVD corresponding to levels C and D respectively.

[0026] After step S325, the programmed action flow and programmed verification action flow can be executed one or more times in an alternating manner, and then the process can enter node N2.

[0027] Following node N2, steps S331 to S334 can sequentially execute the programmed action flow PGM, the programmed verification action flow PV, the programmed action flow PGM, and the programmed verification action flow PV, respectively. Corresponding to step S331, the error bit count detection circuit can execute the fast-skip programmed verification action SSPV_G for level G, and the error bit count detection action FBD_E for level E. Here, we take the example of fast-skip programmed verification action SSPV_G passing and error bit count detection action FBD_E failing. Next, corresponding to step S332, the error bit count detection circuit can execute the programmed verification actions PVE~PVG for levels E to G. Corresponding to step S333, the error bit count detection circuit can execute the error bit count detection actions FBD_G and FBD_E for levels G and E, respectively.

[0028] Here, taking the target level as level G as an example, in the detection result of the error bit count detection action FBD_G in step S333, the detection result of some memory planes is passed, while the detection result of other memory planes is failed. Here, the memory planes whose detection results are passed can be closed to stop access.

[0029] Furthermore, in this embodiment, the error bit count detection action FBD_E is, for example, a failure.

[0030] Next, corresponding to step S334, the error bit detection circuit can perform programmed verification actions PVE to PVG of layers E to G for the memory plane that has not been turned off.

[0031] Similarly, in step S334, the programmed action flow and programmed verification action flow can be executed one or more times in succession, and then enter node N3.

[0032] Following node N3, steps S341 to S345 can sequentially execute the programmed action flow PGM, the programmed verification action flow PV, the programmed action flow PGM, the programmed verification action flow PV, and the programmed action flow PGM. Corresponding to step S341, the error bit detection circuit can execute error bit detection actions FBD_G and FBD_E corresponding to levels G and E, respectively. Here, we take an example where the error bit detection action FBD_G for another part of the memory plane passes, while the detection results of the remaining error bit detection actions FBD_G still fail. The detection result of error bit detection action FBD_E is then all passes.

[0033] Similarly, in step S341, the error bit count detection action FBD_G means that the memory plane that has passed can be turned off to stop access.

[0034] Corresponding to step S342, the error bit detection circuit can execute the programmed verification actions PVF and PVG for the corresponding layers F and G. Corresponding to step S343, the error bit detection circuit can execute the error bit detection actions FBD_G and FBD_F for the corresponding layers G and F, respectively. Here, we take the example where the detection result of the error bit detection action FBD_F is all passed. In the detection result of the error bit detection action FBD_G, some memory planes also pass the detection result. These memory planes that pass the detection can also be turned off.

[0035] Corresponding to step S344, the error bit detection circuit can execute the programmed verification action PVG of the corresponding level G, and in the corresponding step S345, execute the error bit detection action FBD_G. The detection results of the remaining memory planes during this execution of the error bit detection action FBD_G are all passed. Accordingly, the programmed action flow can be completed.

[0036] Of course, the detection results in the above-described action flow are merely illustrative examples. The illustration in Figure 3 is only intended to enable those skilled in the art to understand the operational details of the embodiments of the present invention, and does not represent that the pass or fail of the error bit count detection result will be consistent with the above description in all programmed actions.

[0037] Please refer to FIG4, which illustrates a schematic diagram of a memory device according to an embodiment of the present invention. The memory device 400 includes a plurality of memory planes P0~PN, a voltage generator 420, an address decoder 430, a control circuit 440, a page buffer circuit 450, and a data input / output circuit 460. The voltage generator 420 receives a power supply PWR and provides a character line voltage VWL to the address decoder 430 according to the power supply PWR. The control circuit 440 receives a control signal CTRL, a command signal CMD, and an address signal ADDR. The control circuit 440 provides access location information ADI to the address decoder 430 according to the address signal ADDR. The address decoder 430 can generate and provide a selection signal SSL, a character line signal WL, and a ground selection line signal GSL to the memory planes P0~PN according to the access location information ADI.

[0038] The page buffer circuit 450 is coupled to the bit lines of the memory plane P0~PN to receive or transmit bit line signals BL. The page buffer circuit 450 can generate data DL for read data by sensing the bit line signals BL, or generate the bit line signals BL based on the data DL for write data. The data DL for read data can be received by the data input / output circuit 460 and generate output data DATA. Alternatively, the data DL for write data can be generated based on the input data DATA provided by the data input / output circuit 460.

[0039] It is worth noting that in this embodiment, the control circuit 440 includes an error bit detection circuit (FBD) 441. The error bit detection circuit (FBD) 441 can be a digital circuit and can be used to perform error bit detection operations.

[0040] The flow of the programmed actions performed by the control circuit 440 has been described in detail in the embodiments of Figures 1 to 3 above, and will not be repeated here.

[0041] In summary, during the programming process, the memory device of the present invention detects each memory plane by performing an error bit count detection operation. Furthermore, when a memory plane is a verified memory plane, the memory device can prevent the verified memory plane from being interfered with by subsequent programming operations by turning off this memory plane, and can maintain the stability of the stored data of the memory cells of the verified memory plane. [Simplified Explanation of the Diagram]

[0042] Figure 1 illustrates a flowchart of a programming method for a memory device according to an embodiment of the present invention. Figure 2 illustrates a flowchart of a programming method for a memory device according to another embodiment of the present invention. Figure 3 illustrates a flowchart detailing the implementation of a programming method for a memory device according to an embodiment of the present invention. Figure 4 illustrates a schematic diagram of a memory device according to an embodiment of the present invention.

Claims

1. A method for programming a memory device, comprising: After a first programmed action on a plurality of memory planes of the memory device, a programmed verification action is performed on each of the memory planes of the memory device. A second programmed action is performed on each memory plane of the memory device, and an error bit count detection action is performed along with the second programmed action to determine that at least one of the memory planes has passed verification; and access operations on the at least one verified memory plane are closed.

2. The programmed method as described in claim 1, wherein when the verification result of the error bit count detection action corresponding to a target layer is passed, the corresponding memory plane is the corresponding passed verification memory plane.

3. The procedural method as described in claim 2 further includes: Between the procedural verification action corresponding to the first level and the error bit count detection action corresponding to the first level, a fast-jump procedural verification action corresponding to the second level is executed.

4. The procedural method as described in claim 3, wherein the fast-jump procedural verification action corresponding to the second level is executed synchronously with the second procedural action.

5. The procedural method as described in claim 3 further includes: When the verification result of the fast-jump procedural verification action corresponding to the second level is passed, the procedural verification action corresponding to the second level is initiated.

6. The procedural method as described in claim 3 further includes: For these memory planes, the programmed method is completed when the verification result of the error bit count detection action from the first level to the target level is passed.

7. The programming method as described in claim 3, wherein the target layer is one of the first layer to the highest layer.

8. The procedural method as described in claim 1, wherein when the verification result of the error bit count detection action corresponding to multiple layers is passed, the corresponding memory plane is the respective passed verification memory plane.

9. The procedural method as described in claim 1 further includes: Once it is determined that at least one of the memory planes has passed verification, multiple programmed pulses are provided to the at least one verified memory plane, and then the at least one verified memory plane is turned off.

10. A memory device, comprising: Multiple memory planes; And a control circuit coupled to the memory planes, the control circuit being configured to: perform a programmed verification operation on each of the memory planes of the memory device after a first programmed operation on the plurality of memory planes of the memory device; perform a second programmed operation on each of the memory planes of the memory device, and perform an error bit count detection operation accompanying the second programmed operation to determine at least one of the memory planes that has passed verification; and disable access operations on the at least one verified memory plane.

11. The memory device as claimed in claim 10, wherein the control circuit is further configured to: when the verification result of the error bit count detection action corresponding to a target level is passed, the corresponding memory plane is the respective passed verification memory plane.

12. The memory device as claimed in claim 11, the control circuitry is further configured to: execute a fast-skip procedural verification action corresponding to a second level between the procedural verification action corresponding to a first level and the error bit count detection action corresponding to the first level.

13. The memory device as claimed in claim 12, the control circuitry is further configured to: synchronously execute the fast-jump procedural verification action corresponding to the second level and the second procedural action.

14. The memory device as claimed in claim 12, the control circuitry is further configured to: initiate the programmed verification action corresponding to the second level when the verification result of the fast-skip procedural verification action corresponding to the second level is passed.

15. The memory device as claimed in claim 12, wherein the target layer is one of the first layer to the highest layer.

16. The memory device as claimed in claim 11, wherein the control circuitry is further configured to: when the verification results of the error bit count detection actions corresponding to multiple target layers are all passed, the corresponding memory plane is the respective passed verification memory plane.

17. The memory device as claimed in claim 10, wherein the control circuitry includes: An error bit count detection circuit is used to perform the error bit count detection action.

18. The memory device as claimed in claim 10, further comprising: A voltage generator, coupled to the control circuit, is used to provide the character line voltage; An address decoder, coupled between the voltage generator and the memory planes, is used to generate multiple address signals; a page buffer circuit, coupled to the control circuit and to multiple bit lines of the memory planes; And a data input / output circuit, coupled between the page buffer and the control circuit.

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