Memory device and control method thereof

Abstract

A memory device and a control method thereof are provided. The memory device may be a three-dimensional NAND flash memory with high capacity and high performance. The memory device includes a memory array and a memory controller. The memory array includes a plurality of memory pages. The memory controller is coupled to the memory array, and configured to control the memory array. In a program operation of a current memory page, the memory controller applies a plurality of compensation voltages to a plurality of low threshold parts of a plurality of states of a threshold voltage distribution of a previous memory page through a previous word line, and memory controller further applies a pass voltage to another plurality of states of the threshold voltage distribution of the previous memory page and a plurality of corresponding states of a threshold voltage distribution of the current memory page through the previous word line and a current word line.

Description

[Technical Field]

[0001] This invention relates to a control technology for memory devices (e.g., NAND flash memory), and more particularly to a memory device and a control method thereof. [Previous Technology]

[0002] High-capacity and high-performance integrated circuit memory, including three-dimensional (3D) NAND flash memory, is under continuous development. It is hoped that the size of memory cells can be reduced and the data storage density can be increased by using three-dimensional stacking technology and triple-level cells (TLC).

[0003] For a typical memory device, during the write operation of the memory controller performing incremental step pulse programming (ISPP) on the current memory page, the multiple write voltages of the multiple states of the threshold voltage distribution applied to the current memory page may generate additional programming noise interference and program pattern effect on the multiple states of the threshold voltage distribution of the previous memory page. Therefore, it is easy to cause data errors in the data stored in the multiple memory cells of the previous memory page. [Summary of the Invention]

[0004] The present invention provides a memory device and its control method, which can provide reliable data storage function.

[0005] The memory device of the present invention includes a memory array and a memory controller. The memory array includes a plurality of memory pages. The memory controller is coupled to the memory array and is used to control the memory array. In a write operation of the current memory page, the memory controller applies a plurality of compensation voltages through a previous word line to a plurality of low threshold portions of a plurality of states of a threshold voltage distribution of the previous memory page, and the memory controller also applies through voltages to the plurality of states of the threshold voltage distribution of the previous memory page and the corresponding plurality of states of the current memory page through the previous word line and the current word line.

[0006] The control method of the present invention is applicable to a memory device. The memory device includes a memory array. The memory array includes a plurality of memory pages. The control method includes the following steps: in a write operation of the current memory page, applying a plurality of compensation voltages through a previous word line to a plurality of low threshold portions of a plurality of states of a threshold voltage distribution of the previous memory page; and in a write operation of the current memory page, further applying through voltages to a plurality of other states of the threshold voltage distribution of the previous memory page and corresponding states of the current memory page through the previous word line and the current word line.

[0007] Based on the above, the memory device and control method of the present invention can compensate for multiple states in the threshold voltage distribution of the previous memory page during the write operation of the current memory page, so as to effectively reduce the influence of multiple states in the threshold voltage distribution of the previous memory page caused by rapid charge loss (short-term retention), interference caused by additional programming noise, and program pattern effect.

[0008] In order to make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below, and detailed descriptions are given in conjunction with the accompanying drawings.

Implementation Method

[0009] Figure 1 is a schematic diagram of a memory device according to an embodiment of the present invention. Figure 2 is a three-dimensional architecture schematic diagram of a memory array according to an embodiment of the present invention. Referring first to Figure 1, the memory device 100 includes a memory controller 110 and a memory array 120. The memory controller 110 is coupled to the memory array 120 and is used to control the memory array 120. In this embodiment, the memory device 100 may be a three-dimensional NAND memory device. The memory array 120 may include a plurality of memory cells, and the plurality of memory cells are arranged in a three-dimensional manner.

[0010] Referring next to Figure 2, Figure 2 presents an equivalent circuit example of a three-dimensional NAND memory in a three-dimensional manner. As shown in Figure 2, in the XYZ coordinate system, the memory array 120 can be divided into four sub-blocks Sub_0 to Sub_3, and each sub-block can be operated independently. In this example, taking sub-block Sub_0 as an example, sub-block Sub_0 includes serial rows 121 to 123, each of which includes multiple memory cells connected in series along the Z direction. Each of the multiple memory cells on serial rows 121 to 123 corresponds to one of the word lines WL_1 to WL_m, wherein the word lines WL_1 to WL_m can be respectively set in one layer in the parallel XY plane. The plurality of memory cells in sub-blocks Sub_0 to Sub_3 can be coupled to the string select transistors of SSL0 to SSL3 respectively, and the plurality of memory cells can be coupled to the ground select transistors coupled to the corresponding ground select lines GSL respectively.

[0011] In this example, the serial select transistor and the ground select transistor are located on opposite sides of the memory cells in the corresponding serial array. In the example of Figure 2, multiple serial arrays coupled to the same plane (e.g., the plane defined by the X and Z directions) on the same serial select line can be defined as a sub-block.

[0012] In this example, each serial string is coupled to a corresponding bit line BL_1~BL_3 via a corresponding serial select transistor on the corresponding serial select line. Furthermore, serial strings in the same column along the Y direction from different sub-blocks can be coupled to the same corresponding bit line. The serial select line SSL can be formed as a conductor or layer above the top of the top word line layer of the memory array. Each serial string can be coupled to the same common source line CSL via a corresponding ground select transistor on the ground select line GSL. The ground select line GSL can be formed as a conductor or layer below the bottom of the bottom word line layer of the memory array. The common source line CSL can be formed as a conductive layer above the substrate of the three-dimensional memory.

[0013] In this example, the multiple serial select lines in the memory array 120 may be located on the same conductive layer, but are divided into multiple separate stripes. Furthermore, each separate strip on the same conductive layer can independently control the operation of the corresponding sub-block in the memory array 120 of the three-dimensional NAND memory.

[0014] In one example, multiple memory cells coupled to the same word line or word line layer in a sub-block can be defined as a memory page (in single-level cell (SLC) mode). In another example, multiple memory cells coupled to the same word line or word line layer can be defined as three memory pages (in triple-level cell (TLC) mode). In the three-level cell mode, the three memory pages include a high page, a middle page, and a low page. Furthermore, multiple memory cells on the same word line can be subjected to the same voltage. The same word line can be coupled to a corresponding driver circuit, which may be, for example, an X decoder (or scan driver).

[0015] In one example, one or more virtual lines or layers (not shown) may be provided between the serial select line and the topmost word line layer of the serial string, and / or the ground select line GSL and the bottommost word line layer of the serial string. In another embodiment, one or more virtual lines or layers (not shown) may be provided in the middle portion of the serial string.

[0016] Figure 3 is a schematic diagram of the threshold voltage distribution according to an embodiment of the present invention. Referring to Figures 1 to 3, in this embodiment, the memory controller 110 can sequentially program multiple memory pages coupled to word lines WL_m to WL_1, starting from the side closest to bit line BL_1. The following description takes two memory pages coupled to word lines WL_(n+1) and WL_n as examples, where n is between 1 and m. After the memory controller 110 completes encoding the memory page preceding the coupled word line WL_(n+1), the memory controller 110 can then encode the current memory page coupled to word line WL_n.

[0017] This invention uses a three-level cell (TLC) storage mode as an example, but it is not limited to this. The memory device 100 of this invention can also be applied to other multi-level storage mode. In this embodiment, after the previous memory page is encoded, the previous memory page may have a threshold voltage distribution 300 as shown in FIG3. The threshold voltage distribution 300 of the previous memory page can be divided into multiple states S0 to S7 by voltages V1 to V7, wherein state S0 is the erase state.

[0018] In this embodiment, before encoding the current memory page of the coupled character line WL_n, the memory controller 110 can apply seven read voltages Vs1 to Vs7 with specific voltage levels to the threshold voltage distribution 300 of the previous memory page through the character line WL_(n+1) to distinguish the low threshold portion and the high threshold portion of each of states S1 to S7, and read the stored data content of the low threshold portion S1D to S7D and the high threshold portion S1U to S7U of states S1 to S7 through the read voltages Vs1 to Vs7.

[0019] Figure 4 is a schematic diagram of the programming relationship between the previous memory page and the current memory page according to an embodiment of the present invention. Referring to Figures 1 to 4, continuing the embodiment of Figure 3, during the write operation of the memory controller 110 on the current memory page, the memory controller 110 can compensate for multiple states S1 to S7 of the threshold voltage distribution 300 of the previous memory page to effectively reduce factors that broaden the threshold voltage distribution, such as rapid charge loss (short-term retention), reduce interference caused by additional programming noise, and reduce the influence of the program pattern effect. It is worth noting that the write operation refers to the voltage application operation of incremental step pulse programming (ISPP) on the current memory page.

[0020] As shown in Figure 4, which is a schematic diagram of a programming relation table 400, the memory controller 110 can determine whether to compensate for the low threshold portions S1D ​​to S7D of the threshold voltage distribution 300 of the previous memory page according to the programming relation table 400. As shown in Figure 4, the current memory page threshold voltage distribution state S0 is an erase state, and the cells of state S0 do not involve ISPP, but the memory controller 110 still compensates for the low threshold portions S1D ​​to S7D of the threshold voltage distribution 300 of the previous memory page. When the memory controller 110 performs an ISPP write operation in states S1 to S7, the compensation operation can be embedded in the compensation period P2 of the bit line voltage waveforms V2_BL and V3_BL shown in Figures 6B and 6C.

[0021] When the memory controller 110 performs an ISPP write operation on the states S1 to S4 of the threshold voltage distribution of the current memory page, the memory controller 110 may compensate for the low threshold portions S1D ​​to S7D of the states S1 to S7 of the threshold voltage distribution 300 of the previous memory page (represented in a table without diagonal lines). Furthermore, the memory controller 110 may not compensate for the high threshold portions S1U to S7U of the states S1 to S7 of the threshold voltage distribution 300 of the previous memory page (represented in a table with diagonal lines).

[0022] Furthermore, during the ISPP write operation on the threshold voltage distribution states S5~S7 of the current memory page through the current character line WL_n, the threshold voltage distribution states S0~S7 of the previous memory page may be subject to strong interference effects when the current memory page's threshold voltage distribution states S5~S7 are written. Therefore, when the memory controller 110 performs an ISPP write operation on the threshold voltage distribution states S0~S7 of the current memory page, the memory controller 110 does not compensate for the threshold voltage distribution states S0~S7 of the previous memory page (represented by a table with diagonal lines).

[0023] However, the state without compensation is not limited to the embodiment of FIG4. In one embodiment, during the ISPP write operation in the states S1 to S6 of the current memory page threshold voltage distribution, the memory controller 110 may also compensate for the low threshold portions S1D ​​to S7D of the states S1 to S7 of the previous memory page threshold voltage distribution 300, and may not compensate for the low threshold portions S1D ​​to S7D of the states S1 to S7 of the previous memory page threshold voltage distribution 300 during the ISPP write operation in the states S0 and S7 of the current memory page threshold voltage distribution.

[0024] FIG5 is a flowchart of a control method for a memory device according to an embodiment of the present invention, which is the second stage of the ISPP of the current memory page (indicated by symbol P2 in FIG6A). Referring to FIG1 to FIG5, in this embodiment, during the ISPP write operation of the current memory page, the memory controller 110 may execute the following steps S510 to S530. In step S510, the memory controller 110 performs a write operation of the current memory page. In step S520, during the write operation of the current memory page (i.e., the second stage P2), the memory controller 110 applies multiple compensation voltages through the previous character line WL_(n+1) to multiple low threshold portions of multiple states of the threshold voltage distribution 300 of the previous memory page. For example, as shown in Figure 4, during the ISPP write operation in the state S1~S4 of the current memory page threshold voltage distribution, the memory controller 110 applies a compensation voltage through the previous word line WL_(n+1) to the low threshold portion S1D~S7D of the state S1~S7 of the previous memory page threshold voltage distribution 300.

[0025] In step S530, during the second stage of the write operation of the current memory page, the memory controller 110 also applies a pass voltage through the previous word line WL_(n+1) to multiple states of the threshold voltage distribution 300 of the previous memory page and multiple states of the current memory page (symbol P2, but not shown in FIG6A). For example, as shown in FIG4, during the ISPP write operation in states S5 to S7 of the threshold voltage distribution of the current memory page, in the second stage (symbol P2, but not shown in FIG6A), the memory controller 110 may apply a pass voltage through the previous word line WL_(n+1) to states S0 to S7 of the threshold voltage distribution 300 of the previous memory page. Alternatively, the memory controller 110 may apply the write voltage only to states S1 to S7 of the threshold voltage distribution of the current memory page.

[0026] Step S530 has another example. In the write operation of the current memory page (second stage P2), the memory controller 110 can apply multiple compensation voltages to multiple states of the threshold voltage distribution 300 of the previous memory page through the previous word line WL_(n+1) (as shown in Figure 6A). At the same time, in the second stage P2, the bit line voltage waveforms V1_BL and V4_BL are subject to suppression voltages (as shown in Figures 6B and 6C).

[0027] Furthermore, in this embodiment, in the second stage (symbol P2 but not shown in FIG. 6A), the memory controller 110 also applies a high threshold portion of the state of the threshold voltage distribution 300 of the previous memory page through the previous word line WL_(n+1). For this purpose, as shown in FIG. 4, during the ISPP write operation in the state S1~S7 of the current memory page threshold voltage distribution, in the second stage (symbol P2 but not shown in FIG. 6A), the memory controller 110 may apply a high threshold portion S1U~S7U of the state S1~S7 of the threshold voltage distribution 300 of the previous memory page through the previous word line WL_(n+1).

[0028] Furthermore, during the ISPP write operation of the memory controller 110 on the threshold voltage distribution of the current memory page, if multiple states of the threshold voltage distribution of the current memory page do not require voltage application, but multiple states of the threshold voltage distribution 300 of the previous memory page require compensation, then the memory controller 110 provides a 0-volt voltage to the bit line in the first stage (symbol P1 indicated in FIG. 6). In the second stage (symbol P2 indicated in FIG. 6), the memory controller 110 switches to providing a suppression voltage Vdd to the bit line to apply a suppression voltage to the multiple states of the threshold voltage distribution 300 of the previous memory page.

[0029] Next, referring to FIG6A, FIG6A is a schematic diagram of the voltage waveform of the word line according to an embodiment of the present invention. The voltage waveform V_WL_(n+1) of the previous word line WL_(n+1) and the voltage waveform V_WL_n of the current word line WL_n can be shown in FIG6A. In this embodiment, during the process of the memory controller 110 performing an ISPP write operation on the threshold voltage distribution of the current memory page, during the write period P1 (first stage) from time t1 to time t2, the memory controller 110 can apply a programming voltage Vpgm to the state S1 to S7 of the threshold voltage distribution of the current memory page through the current word line WL_n, wherein the programming voltage Vpgm can be determined according to the current programming of the state S1 to S7 of the threshold voltage distribution of the current memory page. Furthermore, during the write operation P1, the memory controller 110 can apply a pass voltage Vpass to the previous memory page state S0~S7 via the previous character line WL_(n+1).

[0030] Next, during the compensation period P2 (second stage) from time t2 to time t3, when the ISPP write operation of the current memory page's threshold voltage distribution states S1~S4 (from time t1 to time t2) is in the first stage, the memory controller 110 can compensate for the low threshold portions S1D~S7D of the previous memory page's threshold voltage distribution 300 states S1~S7 that need compensation. To do this, the memory controller 110 can apply a compensation voltage Vc through the previous word line WL_(n+1) to the low threshold portions S1D~S7D of the previous memory page's threshold voltage distribution 300 states S1~S7. Furthermore, during the compensation period P2, the memory controller 110 can apply a pass voltage Vpass through the current word line WL_n to the current memory page states S0~S7.

[0031] In this embodiment, the compensation voltage Vc can be determined according to one of the corresponding states S0 to S7 of the threshold voltage distribution 300 of the previous memory page. In this embodiment, the compensation voltage Vc is higher than the pass voltage Vpass.

[0032] Figures 6B and 6C are schematic diagrams of bit line voltage waveforms according to an embodiment of the present invention. In one embodiment, the memory controller 110 may also apply different bit line voltages to bit line BL_1 by modulating the bit line voltage. Specifically, referring to Figure 6B, during the process of the memory controller 110 performing an ISPP write operation on the threshold voltage distribution of the current memory page, if multiple states of the threshold voltage distribution of the current memory page do not require a write operation (suppression) and multiple states of the threshold voltage distribution 300 of the previous memory page do not require compensation, then as shown in the bit line voltage waveform V1_BL, the memory controller 110 provides a suppression voltage Vdd to bit line BL_1 during the write period P1 to apply the suppression voltage Vdd to the multiple states of the threshold voltage distribution of the current memory page. Furthermore, during the compensation period P2, the memory controller 110 continuously provides a suppression voltage Vdd to bit line BL_1 to apply the suppression voltage Vdd to the multiple states of the threshold voltage distribution 300 of the previous memory page. Similarly, in one embodiment, the compensation voltage can still be applied to the previous word line WL_(n+1), but since the suppression voltage Vdd is applied to the bit line BL_1, the plurality of states of the threshold voltage distribution 300 of the previous memory page will be suppressed.

[0033] During the ISPP write operation of the memory controller 110 on the threshold voltage distribution of the current memory page, if multiple states of the threshold voltage distribution of the current memory page require voltage application, and multiple states of the threshold voltage distribution 300 of the previous memory page require compensation voltage application, then as shown in the bit line voltage waveform V2_BL, the memory controller 110 provides a 0-volt voltage to bit line BL_1 during the write period via P1. Furthermore, during the compensation period, the memory controller 110 can switch to providing bit line voltage VBL to bit line BL_1 via P2. In this embodiment, the bit line voltage VBL is determined according to the corresponding state of the threshold voltage distribution of the previous memory page.

[0034] Referring again to FIG6C, during the ISPP write operation of the memory controller 110 on the threshold voltage distribution of the current memory page, if multiple states of the threshold voltage distribution of the current memory page do not require writing, but multiple states of the threshold voltage distribution 300 of the previous memory page do not require compensation voltage, then as shown in the bit line voltage waveform V3_BL, the memory controller 110 provides a suppression voltage Vdd to the bit line BL_1 during the write period to apply the suppression voltage Vdd to the multiple states of the threshold voltage distribution of the current memory page. Furthermore, during the compensation period, the memory controller 110 can switch to providing the bit line voltage VBL to the bit line BL_1.

[0035] During the ISPP write operation of the memory controller 110 on the threshold voltage distribution of the current memory page, if multiple states of the threshold voltage distribution of the current memory page do not require voltage application, but multiple states of the threshold voltage distribution 300 of the previous memory page require compensation, then as shown in the bit line voltage waveform V4_BL, the memory controller 110 provides a 0-volt voltage to the bit line BL_1 during the write period via P1. Furthermore, during the compensation period, the memory controller 110 switches to providing a suppression voltage Vdd to the bit line BL_1 via P2 to apply the suppression voltage Vdd to the multiple states of the threshold voltage distribution 300 of the previous memory page.

[0036] Figure 7 is a schematic diagram of the compensated threshold voltage distribution according to an embodiment of the present invention. Referring to Figure 7, after compensation according to the above embodiment, the previous memory page may have a threshold voltage distribution 700 as shown in Figure 7. As shown in Figure 7, the voltage distribution boundaries of the overall states S1 to S7 of the threshold voltage distribution 700 of the previous memory page may shift towards the voltage distribution boundaries of the higher threshold portion. In this way, during the ISPP write operation of the current memory page's threshold voltage distribution, the lower threshold portion of the states S1 to S7 of the previous memory page's threshold voltage distribution 700 may be less affected by interference and programming mode effects, thus effectively maintaining the fidelity of the stored data of the previous memory page.

[0037] In summary, the memory device and control method of the present invention can apply a corresponding compensation voltage through the previous word line during the write operation of the current memory page to compensate for the low threshold portion of multiple states in the threshold voltage distribution of the previous memory page, and can effectively reduce the interference caused by additional programming noise and the influence of the program pattern effect on the overall state of the threshold voltage distribution of the previous memory page.

[0038] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0039] Figure 1 is a schematic diagram of a memory device according to an embodiment of the present invention. Figure 2 is a three-dimensional architecture schematic diagram of a memory array according to an embodiment of the present invention. Figure 3 is a schematic diagram of the threshold voltage distribution according to an embodiment of the present invention. Figure 4 is a schematic diagram of the programming relationship between the previous memory page and the current memory page according to an embodiment of the present invention. Figure 5 is a flowchart of a control method according to an embodiment of the present invention. Figure 6A is a schematic diagram of the voltage waveform of the word line according to an embodiment of the present invention. Figures 6B and 6C are schematic diagrams of the voltage waveform of the bit line according to an embodiment of the present invention. Figure 7 is a schematic diagram of the compensated threshold voltage distribution according to an embodiment of the present invention.

Claims

1. A memory device, comprising: A memory array comprising multiple memory pages; And a memory controller coupled to the memory array and used to control the memory array, wherein in a write operation of a current memory page, the memory controller applies a plurality of compensation voltages through a previous word line to a plurality of low threshold portions of a plurality of states of a threshold voltage distribution of a previous memory page, and the memory controller also applies a pass voltage through the previous word line and a current word line to the states of the threshold voltage distribution of the previous memory page and the corresponding plurality of states of the current memory page.

2. The memory device as claimed in claim 1, wherein the memory controller further applies the through voltage to a plurality of high-threshold portions of the states of the threshold voltage distribution of the previous memory page via the previous character line.

3. The memory device as claimed in claim 1, wherein the memory controller applies the through voltage to the states of the threshold voltage distribution of the current memory page through the current character line, corresponding to the low threshold portions of the states of the threshold voltage distribution of the previous memory page.

4. The memory device as claimed in claim 1, wherein the compensation voltages are determined based on the states of the threshold voltage distribution of the preceding memory page.

5. The memory device as claimed in claim 1, wherein the compensation voltages are higher than the pass voltage.

6. The memory device as claimed in claim 1, wherein during the write operation of the current memory page, the memory controller further applies a plurality of bit line voltages to the states of the threshold voltage distribution of the previous memory page by modulating bit line voltages.

7. The memory device as claimed in claim 6, wherein during the write operation of the current memory page, the memory controller further applies a suppression voltage to the states of the threshold voltage distribution of the previous memory page by modulating the bit line voltage.

8. The memory device as claimed in claim 7, wherein the bit line voltages are determined based on the states of the threshold voltage distribution of the preceding memory page.

9. The memory device as claimed in claim 1, wherein the states corresponding to the current memory page include an erase state.

10. A method for controlling a memory device, wherein the memory device includes a memory array, and the memory array includes a plurality of memory pages, wherein the control method includes: In a write operation to a current memory page, multiple compensation voltages are applied through a previous word line to multiple low-threshold portions of multiple states of the threshold voltage distribution of the previous memory page; and in the write operation to the current memory page, a pass voltage is also applied through the previous word line and a current word line to the states of the threshold voltage distribution of the previous memory page and the corresponding multiple states of the current memory page.

11. The control method as described in claim 10 further includes: In the write operation of the current memory page, multiple high-threshold portions of the states of the threshold voltage distribution of the previous memory page are also applied through the previous word line.

12. The control method as described in claim 10 further includes: In the write operation of the current memory page, the low threshold portion of the individual states of the threshold voltage distribution of the previous memory page is also applied through the current word line to the states of the threshold voltage distribution of the current memory page.

13. The control method as claimed in claim 10, wherein the compensation voltages are determined based on the states of the threshold voltage distribution of the preceding memory page.

14. The control method as claimed in claim 10, wherein the compensation voltages are higher than the pass voltage.

15. The control method as described in claim 10 further includes: In the write operation of the current memory page, multiple bit line voltages are also applied to the states of the threshold voltage distribution of the previous memory page by modulating the bit line voltage.

16. The control method as described in claim 15 further includes: In the write operation of the current memory page, a suppression voltage is also applied to the states of the threshold voltage distribution of the previous memory page by modulating the bit line voltage.

17. The control method as described in claim 16, wherein the bit line voltages are determined based on the states of the threshold voltage distribution of the preceding memory page.

18. The control method as described in claim 10, wherein the states corresponding to the current memory page include an erase state.

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