Semiconductor memory devices

Abstract

The objective of this invention is to apply a high voltage to a memory cell outside the write target without energizing the sense amplifier module. The semiconductor memory device according to the embodiment includes: a stacked body formed by alternating layers of a plurality of first insulating layers and a plurality of second insulating layers; a plurality of channel layers respectively disposed in the plurality of first insulating layers and extending along the plurality of first insulating layers and in a first direction; word lines extending within the stacked body along the stacking direction of the stacked body and intersecting the plurality of channel layers; a plurality of bit lines respectively connected to the plurality of channel layers; and a boost circuit respectively disposed in the plurality of first insulating layers and connected to each of the plurality of bit lines.

Claims

1. A semiconductor memory device, comprising: A laminate is formed by alternating layers of first insulating layers and multiple layers of second insulating layers; Multiple channel layers are respectively disposed in the multiple first insulating layers and extend along the multiple first insulating layers and in a first direction; a character line extends in the stack body along the stacking direction of the stack body and intersects with the multiple channel layers; multiple bit lines are respectively connected to the multiple channel layers; and multiple boost circuits are respectively disposed in the multiple first insulating layers and connected to each of the multiple bit lines.

2. The semiconductor memory device as claimed in claim 1, wherein, The plurality of boost circuits are arranged to overlap each other in the stacking direction.

3. The semiconductor memory device as claimed in claim 2, wherein, Each of the plurality of boost circuits includes a metal-oxide-semiconductor field-effect transistor having a gate electrode, a source electrode, and a drain electrode, wherein the gate electrode, the source electrode, and the drain electrode of each metal-oxide-semiconductor field-effect transistor included in the plurality of boost circuits overlap with each other in the stacking direction.

4. The semiconductor memory device as claimed in claim 3, wherein, The gate electrode, the source electrode, and the drain electrode each have: an insulating first pillar extending along the stacking direction within the stacked body; and a first diffusion layer independently disposed within the plurality of first insulating layers and surrounding the first pillar.

5. The semiconductor memory device as claimed in claim 3, wherein, The metal-oxide-semiconductor field-effect transistor further has a back gate, which has: a conductive second pillar extending along the stacking direction within the stacked body; and a gate insulating layer independently disposed within the plurality of first insulating layers and surrounding the second pillar. And a semiconductor layer, independently disposed within the plurality of first insulating layers, and surrounding the gate insulating layer.

6. The semiconductor memory device as claimed in claim 1, wherein, Each of the plurality of boost circuits includes a plurality of metal-oxide-semiconductor field-effect transistors, wherein the source and drain of each plurality of metal-oxide-semiconductor field-effect transistors are arranged in a row in corresponding first insulating layers of the plurality of first insulating layers.

7. The semiconductor memory device as claimed in claim 6, wherein, The plurality of boost circuits are configured at positions overlapping the plurality of channel layers in the first direction, and the rows of the source and drain of the plurality of metal-oxide-semiconductor field-effect transistors extend along the first direction.

8. The semiconductor memory device as claimed in claim 1, further comprising: Multiple memory cells are disposed at each intersection of the multiple channel layers and the character lines; And a sensing amplifier module, which reads data from the plurality of memory cells, wherein each of the plurality of bit lines includes: a plurality of local bit lines, which are respectively disposed in the plurality of first insulating layers and extend from the position that overlaps with the plurality of channel layers in the first direction to a second direction that intersects the first direction and the stacking direction; And multiple global bit lines, which extend along the second direction at positions overlapping with the multiple channel layers in the stacking direction, respectively electrically connecting the multiple local bit lines to the sense amplifier module, and each of the multiple boost circuits is connected to the corresponding local bit line among the multiple local bit lines.

9. The semiconductor memory device as claimed in claim 8, wherein, Each of the plurality of boost circuits includes a plurality of metal-oxide-semiconductor field-effect transistors (MOSFETs). The sources and drains of the plurality of MOSFETs are arranged in a row in corresponding first insulating layers of the plurality of first insulating layers. The rows of the sources and drains of the plurality of MOSFETs extend in a direction that intersects with the extension direction of the plurality of local bit lines.

10. The semiconductor memory device as claimed in claim 1, further comprising: Multiple memory cells are disposed at each intersection of the multiple channel layers and the character lines; The sequencer controls the writing of data to the plurality of memory cells. The sequencer supplies a first voltage, which allows the writing of data, to the memory cell to be written via a first bit line electrically connected to the memory cell to be written. The sequencer supplies a second voltage, which is higher than the first voltage and inhibits the writing of data, to the memory cell to be written via a second bit line electrically connected to a memory cell other than the memory cell to be written. The second voltage is further boosted by a boost circuit connected to the second bit line and then applied to the memory cell to be written.