Channel model implementation circuit and channel model implementation method, memory controller, electronic device and memory system

Abstract

The present disclosure provides a channel model implementation circuit, a channel model implementation method, a memory controller, an electronic device and a memory system. The channel model implementation circuit includes at least one channel model implementation sub-circuit. The channel model implementation sub-circuit includes: a random number generation circuit configured to generate random numbers; and a channel output information determination circuit configured to receive a sub-data of channel input information; and determine channel output information corresponding to the sub-data based on a random number, random number interval group information and the sub-data. The sub-data includes at least two data states, and the random number interval group information includes a mapping relationship between a plurality of random number intervals and a plurality of pieces of channel output information under different data states.

Description

[Technical Field]

[0001] This invention relates to the field of electronic information technology, and to, but is not limited to, a channel model implementation circuit and a channel model implementation method, a memory controller, an electronic device, and a memory system. [Previous Technology]

[0002] In recent years, information technology has experienced rapid development, and information interaction in society has become increasingly frequent. Various channel models are frequently used in fields such as communications, electronics, and semiconductors for data processing; for example, channel models can be applied to data encoding and decoding. However, the implementation of channel models typically requires complex calculations, thus consuming significant hardware and software resources. [Summary of the Invention]

[0003] Embodiments of the present invention provide a channel model implementation circuit and channel model implementation method, a memory controller, an electronic device, and a memory system.

[0004] In a first aspect, embodiments of the present invention provide a channel model implementation circuit, including at least one channel model implementation sub-circuit; the channel model implementation sub-circuit includes: a random number generation circuit configured to generate a random number; a channel output information determination circuit configured to receive a sub-data of channel input information; and determine channel output information corresponding to the sub-data based on the random number, random number interval group information, and the sub-data; wherein the sub-data includes at least two data states, and the random number interval group information includes a mapping relationship between multiple random number intervals and multiple channel output information under different data states.

[0005] In a second aspect, embodiments of the present invention provide a memory controller, the memory controller including an error-detection circuit and a control unit; the error-detection circuit includes the channel model implementation circuit, encoding circuit and decoding circuit described in the above embodiments; wherein, the control unit is configured to: output raw data; the encoding circuit is configured to: encode the raw data to generate the channel input information; the decoding circuit is configured to: obtain decoded data based on the test check matrix and the channel output information corresponding to each sub-data of the channel input information.

[0006] In a third aspect, embodiments of the present invention provide an electronic device, the electronic device including a processor and a memory controller as described in the above embodiments; wherein, the processor is configured to: generate the random number interval group information; the control unit is further configured to: transmit the random number interval group information to the channel model implementation circuit.

[0007] In a fourth aspect, embodiments of the present invention provide a channel model implementation method, the channel model implementation method comprising: generating random numbers; determining channel output information corresponding to each sub-data of the channel input information based on the random numbers, random number interval group information and each sub-data of the channel input information; wherein, the sub-data includes at least two data states, and the random number interval group information includes a mapping relationship between multiple random number intervals and multiple channel output information under different data states.

[0008] In a fifth aspect, embodiments of the present invention provide a memory system, comprising: at least one memory device; and a memory controller as described in the above embodiments, coupled to the at least one memory device and configured to control the memory device.

[0009] In this embodiment of the invention, the channel output information determination circuit determines the channel output information corresponding to a sub-data based on random numbers, random number interval group information, and a sub-data of channel input information. The sub-data includes at least two data states, and the random number interval group information includes mapping relationships between multiple random number intervals and multiple channel output information under different data states. In other words, the invention can pre-generate mapping relationships between multiple random number intervals and multiple channel output information through methods such as simulation and statistics. The channel model implementation circuit then directly determines the channel output information corresponding to each sub-data of the channel input information based on the random number interval group information containing the aforementioned mapping relationships. Thus, the channel model implementation circuit does not need to perform a large amount of computation, which helps save software and hardware resources.

Implementation Method

[0010] Exemplary embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0011] Numerous specific details are set forth in the following description to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, to avoid confusion with the invention, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0012] In the accompanying drawings, the same reference numerals denote the same elements throughout.

[0013] It should be understood that spatial relation terms such as "below," "under," "below," "below," "above," "over," etc., may be used herein for convenience of description to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then the element or feature described as "below" or "under" or "below" the other element or feature will be oriented "over" the other element or feature. Thus, the exemplary terms "below" and "under" can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0014] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms "compose" and / or "comprise," when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0015] In some embodiments, various channel models are commonly used in fields such as communications, electronics, and semiconductors to process data. For example, Binary Phase Shift Keying (BPSK) and Additive White Gaussian Noise (AWGN) models can be used to obtain noisy soft information, thereby performing performance tests on Low Density Parity Check (LDPC) soft decoding. LDPC codes are a parallel iterative decoding algorithm based on a sparse array, possessing performance approaching the datum limit. Decoding is simple and can be performed in parallel, making it one of the most widely used error-detection codes. For example, LDPC codes can be used for error detection and correction of data in memory.

[0016] In this invention, the memory can be volatile memory, including but not limited to Static Random Access Memory (SRAM), Synchronous Static Random Access Memory (SSRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate (DDR) Synchronous Dynamic Random Access Memory, Enhanced Synchronous Dynamic Random Access Memory (ESDRAM), SyncLink Dynamic Random Access Memory (SLDRAM), Direct Rambus Random Access Memory (DRRAM), etc.; the memory can also be non-volatile memory, including but not limited to Read Only Memory (ROM) and Programmable Read-Only Memory (PROM). Memory includes NAND flash memory, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic random access memory (FRAM), and flash memory. The present invention will now be described using a memory system including NAND flash memory as an example.

[0017] Figure 1 is a schematic diagram of an exemplary system with a memory system provided in an embodiment of the present invention. In this embodiment, system 100 may be a mobile phone, desktop computer, notebook computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory therein. As shown in Figure 1, system 100 may include a host 101 and a memory system 102, and memory system 102 may include one or more memory devices 103 and a memory controller 104. Host 101 may include a processor of an electronic device, such as a central processing unit (CPU), or a system on a chip (SoC), such as an application processor (AP). Host 101 may be configured to send data to memory system 102 or receive data from memory system 102.

[0018] In some embodiments, the memory controller 104 is coupled to the memory device 103 and the host 101 and is configured to control the memory device 103. The memory controller 104 can manage data stored in the memory device 103 and communicate with the host 101. In some embodiments, the memory controller 104 is designed to operate in a low duty cycle environment, such as in a secure digital card, a compact flash card (CFC), a universal serial bus (USB) flash memory drive, or in other media used in electronic devices such as personal calculators, digital cameras, and mobile phones. In other embodiments, the memory controller 104 is designed to operate in a high duty cycle environment, such as in a solid-state drive or an embedded multi-media card (eMMC).

[0019] In some embodiments, the memory controller 104 and one or more memory devices 103 can be integrated into various types of storage devices, that is, the memory system 102 can be implemented and packaged into different types of terminal electronic products.

[0020] In one example shown in FIG. 2, the memory controller 104 and a single memory device 103 can be integrated into a memory card 201. The memory card 201 can be a compact flash memory card, a smart media card (SMC), a memory stick (MS), a multi-media card (MMC), such as RS-MMC, MMCmicro, eMMC, etc., a secure digital card, such as a Mini SD card, Micro SD card, SDHC card, etc., or a general-purpose flash memory card. The memory card 201 may also include a memory card connector 202 that couples the memory card 201 to a host device (e.g., host 101 in FIG. 1). In another example shown in FIG. 3, the memory controller 104 and multiple memory devices 103 can be integrated into an SSD 203. The SSD 203 may also include an SSD connector 204 that couples the SSD 203 to a host device (e.g., host 101 in FIG. 1). In some implementations, the storage capacity and / or operating speed of SSD 203 is greater than that of memory card 201.

[0021] FIG4 is a circuit diagram of an exemplary memory device 300 including peripheral circuitry provided in an embodiment of the present invention. The memory device 300 may be an example of the memory device 103 in FIG1. ​​The memory device 300 may include a memory array 301 and peripheral circuitry 302 coupled to the memory array 301. Taking the memory array 301 as a three-dimensional NAND type memory array as an example, wherein the memory cells 305 are NAND memory cells, and the memory cells 305 are provided in the form of an array of memory cell strings 304, each memory cell string 304 extending vertically above a substrate (not shown). In some embodiments, each memory cell string 304 includes a plurality of memory cells 305 coupled in series and stacked vertically. Each memory cell 305 may maintain a continuous analog value, such as voltage or charge, which depends on the number of electrons trapped in the region of the memory cell 305. Each memory cell 305 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0022] In some embodiments, each memory cell 305 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some embodiments, each memory cell 305 is a multi-level cell capable of storing more than a single bit of data in four or more memory states, such as a multi-level cell (MLC) storing two bits per cell, a triple-level cell (TLC) storing three bits per cell, or a quad-level cell (QLC) storing four bits per cell.

[0023] As shown in FIG. 4, each memory cell string 304 may include a bottom select transistor (BST) 307 at its source end and a top select transistor (TST) 306 at its drain end. The bottom select transistor 307 and the top select transistor 306 may be configured to activate the selected memory cell string 304 during read and program operations. In some embodiments, the sources of memory cell strings 304 in the same memory block 303 may be coupled via a common source line (CSL) 310. In other words, all memory cell strings 304 in the same memory block 303 have a common source (ACS). According to some embodiments, the top select transistor 306 of each memory cell string 304 is coupled to a corresponding bit line (BL) 311, and data may be read from or written to the bit line 311 via an output bus (not shown). In some implementations, each memory cell string 304 is configured to be selected or deselected by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the top select transistor 306) or a deselect voltage (e.g., 0V) to the top select gate (TSG) of the corresponding top select transistor 306 via one or more top select lines (TSL) 308 and / or by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the bottom select transistor 307) or a deselect voltage (e.g., 0V) to the bottom select gate (BSG) of the corresponding bottom select transistor 307 via one or more bottom select lines (BSL) 309.

[0024] As shown in FIG. 4, the memory cell string 304 can be organized into multiple memory blocks 303, each of which can have a common source line 310. In some embodiments, each memory block 303 is the basic data unit for an erase operation, i.e., all memory cells 305 on the same memory block 303 are erased simultaneously. To erase memory cells 305 in a selected memory block, an erase voltage bias can be used to couple the common source line 310 to the selected memory block and the unselected memory blocks on the same plane as the selected memory block. It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 305 of adjacent memory cell strings 304 can be coupled via word lines 312, which select which row of memory cells 305 is affected by a read or program operation.

[0025] In some embodiments, the peripheral circuitry 302 may include any suitable analog, digital, and mixed-signal circuitry for applying voltage and / or current signals to each target memory cell 305 via bit lines 311, word lines 312, common-source lines 310, bottom select lines 309, and top select lines 308, and for sensing voltage and / or current signals from each target memory cell 305 to enable operation of the memory array 301. The peripheral circuitry 302 may include various types of peripheral circuitry formed using metal-oxide-semiconductor technology.

[0026] Figure 5 illustrates some exemplary peripheral circuitry, including a page buffer / sensor amplifier 401, a column decoder / bit line driver 402, a row decoder / word line driver 403, a voltage generator 404, control logic 405, a register bank 406, a flash memory interface 407, and a data bus 408. It should be understood that in some examples, additional peripheral circuitry not shown in Figure 5 may also be included.

[0027] The page buffer / sensor amplifier 401 can be configured to read data from and program (write) data to the memory array 301 according to control signals from the control logic 405. In one example, the page buffer / sensor amplifier 401 can store a page of programming data (write data) to be programmed into the memory array 301. In another example, the page buffer / sensor amplifier 401 can perform a programming verification operation to ensure that data has been correctly programmed into the memory cell coupled to the selected word line. In yet another example, the page buffer / sensor amplifier 401 can also sense a low-power signal from the bit line representing the data bits stored in the memory cell and amplify a small voltage swing to a recognizable logic level during a read operation. The column decoder / bit line driver 402 can be configured to be controlled by the control logic 405 and to select one or more memory cell strings by applying a bit line voltage generated from the voltage generator 404.

[0028] The line decoder / word line driver 403 can be configured to be controlled by control logic 405 and to select / deselect memory blocks of the memory array 301 and select / deselect word lines of the memory blocks. The line decoder / word line driver 403 can also be configured to drive word lines using word line voltages generated from voltage generator 404. In some embodiments, the line decoder / word line driver 403 can also select / deselect and drive bottom select lines and top select lines. As described in detail below, the line decoder / word line driver 403 is configured to perform programming operations on memory cells coupled to one or more selected word lines. The voltage generator 404 can be configured to be controlled by control logic 405 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 301.

[0029] Control logic 405 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. A register group 406 can be coupled to control logic 405 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Flash memory interface 407 can be coupled to control logic 405 and acts as a control buffer to buffer control commands received from a host device (not shown) and relay them to control logic 405, as well as to buffer status information received from control logic 405 and relay it to the memory controller. Flash memory interface 407 can also be coupled to column decoder / bit line driver 402 via data bus 408 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory array 301.

[0030] Figure 6 is a schematic diagram of a system including a host and a memory system provided in an embodiment of the present invention. As shown in Figure 6, the memory system 102 is connected to the host 101. The memory system 102 may include a memory controller 104 and a memory device 103. The memory controller 104 is used to control the memory device 103 to perform read, write, erase, and other operations. The memory controller 104 and the memory device 103 may also be coupled in any suitable manner. The memory controller 104 may include a host interface (I / F) 1041, a memory interface (I / F) 1042, a control unit 1043, a debugging circuit 1044, a cache memory 1047, and a bus 1040. The host interface 1041 is a connection interface connecting the host 101 and the memory controller 104. The host interface 1041 allows the host 101 and the memory controller 104 to communicate according to a specific protocol, send read and write requests, and perform other operations. The memory interface 1042 is a connection interface between the memory controller 104 and the memory device 103, and is used to realize data transmission between the memory controller 104 and the memory device 103. The control unit 1043 is used to control the memory system 102 as a whole.

[0031] In some specific embodiments, the control unit 1043 may include one or more units with logic operation capabilities, such as a central processing unit (CPU) and / or a microcontroller unit (MCU).

[0032] In some specific embodiments, the cache memory 1047 is used to cache data and can be a volatile memory device with relatively fast read and write speed, such as static random-access memory (SRAM) and / or dynamic random-access memory (DRAM).

[0033] In some specific embodiments, the error-detecting circuit 1044 can be configured to encode and decode data in the memory system using error-detecting code technology. Specifically, the error-detecting circuit 1044 may include an encoding circuit 1045 and a decoding circuit 1046, wherein the encoding circuit 1045 can be configured to encode the data to be written to the memory device during a write operation; the decoding circuit 1046 can be configured to decode the codeword to be decoded in the read data during a read operation. In some embodiments, the decoding circuit 1046 can decode the codeword to be decoded using LDPC layered decoding (also called decoding). Specifically, the decoding circuit 1046 can decode the codeword to be decoded based on the LDPC code parity check matrix.

[0034] To improve the error correction capability of memory systems, the industry typically conducts software decoding performance tests on LDPC parity-check matrices to determine suitable LDPC parity-check matrices. For example, the encoding circuit described above can first generate encoded data based on the original data (test data); then, it can use the BPSK and AWGN models to perform calculations on the encoded data to obtain noisy soft information (such as the noisy fixed-point log-likelihood ratio (LLR)); the decoding circuit then generates decoded data based on the noisy soft information and the LDPC parity-check matrix to be tested; then, by comparing the decoded data with the original data, the test result of the LDPC parity-check matrix to be tested can be obtained; finally, based on the test results of multiple LDPC parity-check matrices to be tested, the optimal LDPC parity-check matrix for decoding operations in the memory system can be determined. However, as shown in Figure 7, the process of generating the noisy fixed-point LLR using the BPSK and AWGN channel models requires complex floating-point operations, thus consuming a large amount of hardware and software resources.

[0035] As shown in Figure 8, this embodiment of the invention provides a channel model implementation circuit 500, including at least one channel model implementation sub-circuit 501; the channel model implementation sub-circuit 501 includes: a random number generation circuit 510, configured to generate random numbers; a channel output information determination circuit 520, configured to receive a sub-data of channel input information; and determine the channel output information corresponding to the sub-data based on the random number, random number interval group information, and the sub-data; wherein, the sub-data includes at least two data states, and the random number interval group information includes the mapping relationship between multiple random number intervals and multiple channel output information under different data states.

[0036] In this embodiment of the invention, the channel model implementation circuit 500 can realize the process of generating channel output information by performing calculations based on channel input information for any channel model. For example, the channel model implementation circuit 500 can implement BPSK and AWGN channel models to perform calculations on encoded data and generate noise-added fixed-point LLR (i.e., channel output information). It should be noted that the channel model implementation circuit 500 can also implement other channel models, including but not limited to combinations of modulation methods such as Quadrature Phase Shift Keying (QPSK), 8 Phase Shift Keying (8PSK), and Quadrature Amplitude Modulation (QAM) with channels such as Binary Symmetric Channel (BSC), Binary Erasure Channel, Distortionless Channel, and AWGN Channel. For ease of understanding, this invention uses the BPSK and AWGN channel models as an example for explanation.

[0037] The channel model implementation circuit 500 can receive channel input information (such as the encoded data described above). The channel input information may include multiple sub-data, each sub-data including at least two data states. For example, when the channel model adopts BPSK, the sub-data may include 2 data states, namely "0" and "1"; when the channel model adopts QPSK, the sub-data may include 4 data states, namely "00", "01", "10" and "11"; when the channel model adopts 8PSK, the sub-data may include 8 data states, namely "000", "001", "010", "011", "100", "101", "110" and "111".

[0038] The channel model implementation circuit 500 may have at least one channel model implementation sub-circuit 501. Each channel model implementation sub-circuit 501 is used to determine the channel output information corresponding to a sub-data based on a sub-data of the channel input information and random interval group information. As shown in Figure 9, the random interval group information includes the mapping relationship between multiple random intervals and multiple channel output information under different data states. This mapping relationship can be obtained in advance through simulation statistics, formula derivation calculation, etc. For example, a device with logic operation capability, such as a processor, can be used to simulate the channel model on a large amount of user data (user data can be obtained through encoding and other methods to obtain corresponding channel input information), thereby calculating the probability of different data states of the channel input information mapping to each channel output information. Figure 10 shows the probabilities P0(-7), P0(-6), P0(-5)...P0(+5), P0(+6), P0(+7) for sub-data in data state "0" to be mapped to noisy fixed-point LLR values ​​-7, -6, -5...+5, +6, +7, respectively, and the probabilities P1(-7), P1(-6), P1(-5)...P1(+5), P1(+6), P1(+7) for data state "1" to be mapped to noisy fixed-point LLR values ​​-7, -6, -5...+5, +6, +7, respectively. Thus, based on the probability of different data states of the channel input information being mapped to the output information of each channel, and the preset random number value RAND_MAX (i.e., the maximum random number value), multiple random number intervals as shown in Figure 9 can be obtained (for example, multiplying the preset random number value by each probability to obtain the size of the corresponding random number interval, and then summing them to obtain the upper and lower limits of each random number interval), and each random number interval can correspond to a noise-added fixed-point LLR value. In some embodiments, the probability of different data states being mapped to the output information of each channel can be a cumulative probability.

[0039] It should be noted that Figure 9 only shows the mapping relationship between the random number interval group information and the channel output information under two data states "0" and "1" (i.e., two sub-random number interval group information). The random number interval group information may also include the mapping relationship between the random number interval and the channel output information under two or more data states (i.e., two or more sub-random number interval group information).

[0040] In some embodiments, as shown in FIG11, the probability of different data states of channel input information being mapped to the output information of each channel follows a normal distribution. Therefore, the above probabilities P0(-7), P0(-6), P0(-5)……P0(+5), P0(+6), P0(+7), and P1(-7), P1(-6), P1(-5)……P1(+5), P1(+6), P1(+7) can be theoretically calculated using the cumulative distribution function of the normal distribution. It should be noted that Figure 11 only shows the probability distribution under symmetrical channels for BPSK and AWGN. In this case, when the noise-adding fixed-point LLR values ​​x and y are opposites (i.e., x + y = 0), the probability P0(x) of data state "0" mapping to noise-adding fixed-point LLR value x is equal to the probability P1(y) of data state "1" mapping to noise-adding fixed-point LLR value y. Furthermore, the probability of different data states of channel input information mapping to the output information of each channel can also follow other channel functions, such as the pink noise distribution function, white noise distribution function, etc. Thus, the above probabilities can be theoretically calculated using the corresponding channel functions.

[0041] Thus, each channel model implementation sub-circuit 501 may include a random number generation circuit 510 and a channel output information determination circuit 520. The random number generation circuit 510 is used to generate random numbers, exemplarily, the random number is greater than or equal to 0 and less than or equal to the aforementioned random number preset value RAND_MAX. The channel output information determination circuit 520 determines, based on the random number generated by the random number generation circuit 510, the data state of a received sub-data, and the random number interval group information, the random number interval in the corresponding data state and the channel output information corresponding to the random number interval. It is understood that the channel output information determination circuit 520 only needs to implement relatively simple logic functions such as comparison, judgment, and selection, so it occupies less hardware and software resources. In some embodiments, the random number generation circuit 510 can be implemented by a shift register or other related circuits; the output information determination circuit 520 can be implemented by a multiplexer (MUX), comparator, or other related circuits.

[0042] In other words, the present invention can generate a mapping relationship between multiple random number intervals and multiple channel output information in advance through simulation statistics and other methods. The channel model implementation circuit 500 then directly determines the channel output information corresponding to each sub-data of the channel input information based on the random number interval group information containing the above mapping relationship. In this way, the channel model implementation circuit 500 does not need to perform a lot of calculations, which is beneficial to saving software and hardware resources.

[0043] In some embodiments, the channel model implementation circuit 500 can be an application-specific integrated circuit (ASIC), which has the advantages of flexible design and low cost.

[0044] In some embodiments, the channel output information determination circuit 520 is further configured to: receive random interval group information; wherein, the sub-data includes N data states, the random interval group information includes N sub-random interval group information corresponding one-to-one with the N data states, and N is an integer greater than 1; the Pth sub-random interval group information includes the mapping relationship between multiple random intervals and multiple channel output information corresponding to the Pth data state, where P is an integer greater than or equal to 1 and P is less than or equal to N.

[0045] In this embodiment of the invention, sub-data may include N data states, such as the 2, 4, and 8 data states corresponding to BPSK, QPSK, and 8PSK respectively in the above embodiments. Thus, the random interval group information may include N sub-random interval group information corresponding one-to-one with the N data states. For example, in Figure 9, the random interval group information includes the first sub-random interval group information and the second sub-random interval group information corresponding to the two data states "0" and "1". The Pth sub-random interval group information includes the mapping relationship between multiple random intervals and multiple channel output information corresponding to the Pth data state. For example, in Figure 9, the first sub-random interval group information includes the mapping relationship between multiple random intervals and multiple channel output information corresponding to the data state "0".

[0046] In some embodiments, in the information of the Pth sub-random number interval group, the size of the random number interval is positively correlated with the probability that the Pth data state is mapped to the corresponding channel output information.

[0047] In this embodiment of the invention, referring to FIG9, in any sub-random number interval group information, the size of the random number interval can be obtained by multiplying the random number preset value RAND_MAX by the probability that the data state is mapped to the channel output information corresponding to the random number interval. For example, in the first sub-random number interval group, the size of the random number interval corresponding to the channel output information "-7" can be obtained by multiplying the random number preset value RAND_MAX by the probability P0(-7). Thus, if the probability P0(-7) is larger, the random number interval corresponding to the channel output information "-7" is larger, the probability that the random number generated by the random number generation circuit 510 falls into the random number interval is greater, and the probability that the channel model implementation sub-circuit 501 outputs the channel output information "-7" is greater.

[0048] In some embodiments, the channel output information determination circuit 520 is specifically configured to: determine the random number interval corresponding to the random number in the first sub-random number interval group information to the Nth sub-random number interval group information, and determine the channel output information corresponding to the sub-data based on the random number interval where the random number is located and the data state of the sub-data.

[0049] In this embodiment of the invention, the channel output information determination circuit 520 can first determine the N random number intervals corresponding to the random number generated by the random number generation circuit 510 in the first sub-random number interval group information to the Nth sub-random number interval group information, and then determine the channel output information corresponding to one of the N random number intervals based on the data state of the sub-data. For example, referring to FIG9, the channel output information determination circuit first determines that the random number generated by the random number generation circuit falls in the random number interval RAND_MAX*P0(-7) in the first sub-random number interval group information, and determines that the random number falls in the random number interval RAND_MAX*P1(+7) in the second sub-random number interval group information, thereby outputting the channel output information "-7" corresponding to the random number interval RAND_MAX*P0(-7) and the channel output information "+7" corresponding to the random number interval RAND_MAX*P1(+7). Then, the channel output information determination circuit selects and outputs channel output information "-7" when the data status is "0", or selects and outputs channel output information "+7" when the data status is "1", based on the data status of the sub-data.

[0050] In some embodiments, as shown in FIG12, the channel output information determination circuit 520 includes: a first comparison circuit 521, configured to: compare the random number with multiple random intervals in each sub-random number interval group information, determine the N random intervals corresponding to the random number in the first sub-random number interval group information to the Nth sub-random number interval group information, and output the N channel output information corresponding to the N random intervals; a first selection circuit 522, configured to: output one of the N channel output information based on the data state of the sub-data.

[0051] In this embodiment of the invention, the channel output information determination circuit 520 includes a first comparison circuit 521 and a first selection circuit 522. The first comparison circuit 521 compares the random number generated by the random number generation circuit with multiple random number intervals in the information from the first sub-random number interval group to the Nth sub-random number interval group, thereby determining the N random number intervals corresponding to the random number in the information from the first sub-random number interval group to the Nth sub-random number interval group, and outputting the N channel output information corresponding to the N random number intervals. For example, referring to FIG9, the first comparison circuit compares the random number with multiple random number intervals in the information from the first sub-random number interval group, thereby determining that the random number falls into the random number interval RAND_MAX*P0(-7), and outputs the corresponding channel output information "-7"; the first comparison circuit compares the random number with multiple random number intervals in the information from the second sub-random number interval group, thereby determining that the random number falls into the random number interval RAND_MAX*P1(+7), and outputs the corresponding channel output information "+7".

[0052] The first selection circuit 522 is used to select and output one of N channel output information based on the data state of the sub-data. For example, the first selection circuit 522 selects and outputs the channel output information "-7" of the first sub-random number interval group information based on the data state of the sub-data being "0", or selects and outputs the channel output information "+7" of the second sub-random number interval group information based on the data state of the sub-data being "1". In some embodiments, the first comparison circuit 521 may include one or more comparators, and the first selection circuit 522 may include a multiplexer.

[0053] In some embodiments, the sub-data includes a first data state and a second data state. The probability that the first data state is mapped to channel output information n is equal to the probability that the second data state is mapped to channel output information m, where n+m=0, and n and m are both integers. The first data state corresponds to a first sub-random number interval group information, and the second data state corresponds to a second sub-random number interval group information. Multiple random number intervals in the first sub-random number interval group information are the same as multiple random number intervals in the second sub-random number interval group information. The channel output information in the first sub-random number interval group information and the channel output information in the second sub-random number interval group information corresponding to the same random number interval are complementary. The first comparison circuit 521 is configured to compare the random number with multiple random number intervals in the first sub-random number interval group information, determine the random number interval corresponding to the random number, and output the first channel output information corresponding to the random number interval. The first selection circuit 522 is configured to output the first channel output information based on the data state of the sub-data being the first data state; or, based on the data state of the sub-data being the second data state, output the flipped first channel output information.

[0054] In this embodiment of the invention, the sub-data may include two data states, and the probability of the first data state mapping to channel output information n is equal to the probability of the second data state mapping to channel output information m, n+m=0, for example, in the symmetrical channel shown in FIG11, P0(x)=P1(y). At this time, multiple random intervals in the first sub-random interval group information and the second sub-random interval group information may be the same, and two complementary channel output information in the first sub-random interval group information and the second sub-random interval group information may correspond to the same random interval. For example, referring to FIG9, in the case of a symmetrical channel, the random interval RAND_MAX*P0(-7) corresponding to the channel output information "-7" in the first sub-random interval group information and the random interval RAND_MAX*P1(+7) corresponding to the channel output information "+7" in the second sub-random interval group information are the same random interval, because the probability P0(-7)=P1(+7), and the size of the corresponding random intervals may also be equal.

[0055] Thus, since multiple random number intervals in the first sub-random number interval group information are the same as multiple random number intervals in the second sub-random number interval group information, the first comparison circuit 521 only needs to compare the random number with multiple random number intervals in any one of the first and second sub-random number interval group information. For example, the first comparison circuit 521 can compare the random number with multiple random number intervals in the first sub-random number interval group information to determine the random number interval corresponding to the random number, and output the first channel output information corresponding to the random number interval (for example, the channel output information "-7" corresponding to the random number interval RAND_MAX*P 0(-7)). The first selection circuit 522 then outputs the first channel output information based on the data state of the sub-data being the first data state; or, based on the data state of the sub-data being the second data state, it outputs the flipped first channel output information. For example, the first selection circuit 522 directly outputs channel output information "-7" based on the data state of the sub-data being "0", or the first selection circuit 522 outputs the flipped channel output information "+7" based on the data state of the sub-data being "1".

[0056] In some embodiments, the channel output information determination circuit 520 is specifically configured to: determine a sub-random number interval group information corresponding to the sub-data in N sub-random number interval group information based on the data state of the sub-data; determine the random number interval corresponding to the random number in the sub-random number interval group information, and output the channel output information corresponding to the random number interval.

[0057] In this embodiment of the invention, the channel output information determination circuit 520 can first select a sub-random number interval group information corresponding to the data state from N sub-random number interval group information based on the data state of the sub-data. For example, referring to FIG9, when the data state of the sub-data is "0", the channel output information determination circuit selects and outputs the first sub-random number interval group information; when the data state of the sub-data is "1", the channel output information determination circuit selects and outputs the second sub-random number interval group information. Then, the channel output information determination circuit 520 can determine the random number interval corresponding to the random number in the sub-random number interval group information and output the corresponding channel output information. For example, referring to FIG9, when the data state of the sub-data is "0", the channel output information determination circuit determines that the random number falls in the random number interval RAND_MAX*P0(-7) in the first sub-random number interval group information, and thus outputs the corresponding channel output information "-7" (the case where the data state of the sub-data is "1" will not be described again).

[0058] In some embodiments, as shown in FIG13, the channel output information determination circuit 520 includes: a second selection circuit 523, configured to: output one sub-random number interval group information corresponding to the data state of the sub-data from among N sub-random number interval group information; and a second comparison circuit 524, configured to: compare the random number with multiple random number intervals in a sub-random number interval group information to determine the random number interval corresponding to the random number, and output the channel output information corresponding to the random number interval.

[0059] In this embodiment of the invention, the channel output information determination circuit 520 includes a second selection circuit 523 and a second comparison circuit 524. The second selection circuit 523 is used to select one sub-random number interval group information corresponding to the data state from N sub-random number interval group information based on the data state of the sub-data. The second comparison circuit 524 is used to compare the random number with multiple random number intervals in the sub-random number interval group information output by the second selection circuit 523, thereby determining the random number interval corresponding to the random number and the channel output information. For example, referring to FIG9, when the data state of the sub-data is "0", the second selection circuit 523 selects and outputs the information of the first sub-random number interval group. The second comparison circuit 524 compares the random number with multiple random number intervals in the information of the first sub-random number interval group and determines that the random number falls within the random number interval RAND_MAX*P0 (-7), thereby outputting the corresponding channel output information "-7". When the data state of the sub-data is "1", the second selection circuit 523 selects and outputs the information of the second sub-random number interval group. The second comparison circuit 524 compares the random number with multiple random number intervals in the information of the second sub-random number interval group and determines that the random number falls within the random number interval RAND_MAX*P1 (+7), thereby outputting the corresponding channel output information "+7".

[0060] In some embodiments, the second comparison circuit 524 may include one or more comparators, and the second selection circuit 523 may include a multiplexer.

[0061] In some embodiments, as shown in FIG8, the channel model implementation circuit 500 further includes: a storage component 502 for storing random number interval group information.

[0062] In this embodiment of the invention, the storage component 502 is used to store information on random number interval groups generated in advance through methods such as simulation statistics and formula derivation calculation. The storage component 502 includes, but is not limited to, SRAM, SSRAM, DRAM, SDRAM, DDR, ESDRAM, SLDRAM, DRRAM, FRAM, NAND Flash, NOR Flash, etc.

[0063] In some embodiments, the sub-data includes Q bits, and the sub-data includes 2Q data states, where Q is a positive integer.

[0064] In this embodiment of the invention, when the channel model uses BPSK, the sub-data may include 1 bit, i.e., two data states "0" and "1"; when the channel model uses QPSK, the sub-data may include 2 bits, i.e., four data states "00", "01", "10", and "11"; when the channel model uses 8PSK, the sub-data may include 3 bits, i.e., eight data states "000", "001", "010", "011", "100", "101", "110", and "111". It is understood that the sub-data may also include more bits, which will not be elaborated here.

[0065] In some embodiments, the channel input information includes encoded data and the channel output information includes a noisy fixed-point log-likelihood ratio.

[0066] In this embodiment of the invention, the channel model can be a BPSK and AWGN channel model. In this case, the channel input information can be encoded data generated by the encoding circuit, while the channel output information can be a noise-added fixed-point LLR.

[0067] Based on the above-described channel model implementation circuit, as shown in Figures 14 and 15, this embodiment of the invention also provides a memory controller 604. The memory controller 604 includes a host interface (I / F) 6041, a memory interface (I / F) 6042, a cache memory 6047, a bus 6040, a debugging circuit 6044, and a control unit 6043. The debugging circuit 6044 includes the channel model implementation circuit 500, an encoding circuit 6045, and a decoding circuit 6046 as described in the above embodiment. The control unit 6043 is configured to output raw data. The encoding circuit 6045 is configured to encode the raw data to generate channel input information. The decoding circuit 6046 is configured to obtain decoded data based on the test check matrix and the channel output information corresponding to each sub-data of the channel input information.

[0068] The memory controller 604 here can be understood by referring to the memory controller 104 shown in Figures 1, 2, 3, and 6. Other details about the memory controller have been described in detail above, and will not be repeated here for the sake of brevity.

[0069] The control unit 6043 outputs raw data, the encoding circuit 6045 encodes the raw data to generate channel input information, the channel model implementation circuit 500 generates channel output information based on the channel input information and random interval group information, and the decoding circuit 6046 obtains decoded data and decoding results based on the test check matrix and the channel output information. Thus, the memory controller 604 can perform software decoding performance testing on the test check matrix.

[0070] It is understood that, since the present invention can generate a mapping relationship between multiple random number intervals and multiple channel output information in advance through simulation statistics and other methods, the channel model implementation circuit 500 directly determines the channel output information corresponding to each sub-data of the channel input information based on the random number interval group information containing the above mapping relationship. In this way, the channel model implementation circuit 500 does not need to perform a lot of calculations, which is beneficial to saving the software and hardware resources of the memory controller 604.

[0071] In some embodiments, the control unit 6043 is further configured to: compare the decoded data with the original data and output the decoding performance test result; and determine the verification matrix for decoding operation based on the decoding performance test results corresponding to multiple verification matrices to be tested.

[0072] In this embodiment of the invention, the control unit 6043 can perform decoding performance tests on multiple test verification matrices, and based on the decoding performance test results of multiple test verification matrices, determine one of the test verification matrices as the verification matrix for the memory controller 604 to perform decoding operations in actual operation.

[0073] In some embodiments, after the decoding performance test of the verification matrix to be tested is performed, the parameters of the verification matrix to be tested can be further adjusted and optimized based on the decoding performance test results, thereby performing multiple repeated optimization operations to finally obtain the verification matrix of the memory controller 604 for decoding operations in actual work.

[0074] In some embodiments, the control unit 6043 is further configured to: simulate or calculate user data to determine the probability that user data is mapped to multiple channel output information; generate multiple random number intervals that correspond one-to-one with the multiple channel output information based on the probability that user data is mapped to multiple channel output information and a random number preset value; the random number preset value is greater than or equal to the random number generated by the channel model implementation sub-circuit; and generate random number interval group information that includes the mapping relationship between the multiple random number intervals and the multiple channel output information.

[0075] In this embodiment of the invention, the control unit 6043 can obtain random number interval group information in advance based on a large amount of user data through methods such as simulation statistics and formula derivation calculation. For example, the control unit 6043 can simulate the BPSK and AWGN channel models on the user data, thereby calculating the probability that different data states of the sub-data of the channel input information (encoded data) are mapped to the output information (noise-added fixed-point LLR) of each channel.

[0076] Figure 10 shows the probabilities P0(-7), P0(-6), P0(-5)...P0(+5), P0(+6), P0(+7) for sub-data in data state "0" to be mapped to noisy fixed-point LLR values ​​-7, -6, -5...+5, +6, +7, respectively, and the probabilities P1(-7), P1(-6), P1(-5)...P1(+5), P1(+6), P1(+7) for data state "1" to be mapped to noisy fixed-point LLR values ​​-7, -6, -5...+5, +6, +7, respectively. It is understood that the above probabilities can be obtained by the control unit through channel model simulation calculations of the user data. Thus, based on the probability of different data states of the channel input information being mapped to the output information of each channel, and the preset random number value RAND_MAX (i.e., the maximum random number value), multiple random number intervals as shown in Figure 9 can be obtained (for example, multiplying the preset random number value by each probability to obtain the size of the corresponding random number interval, and then summing them to obtain the upper and lower limits of each random number interval), and each random number interval can correspond to a noise-added fixed-point LLR value. In some embodiments, the probability of different data states being mapped to the output information of each channel can be a cumulative probability.

[0077] In some embodiments, the control unit 6043 is specifically configured to: calculate the probability of mapping user data to multiple channel output information by a random number preset value, and obtain the size of multiple random number intervals that correspond one-to-one with the multiple channel output information; and generate random number intervals based on the size of the random number intervals.

[0078] In this embodiment of the invention, referring to FIG9, the control unit can multiply the random number preset value RAND_MAX by each probability to obtain the size of the corresponding random number interval, and then perform cumulative calculation to obtain the upper limit or lower limit value of each random number interval. Further, the control unit can generate the corresponding random number interval based on the upper limit and lower limit values ​​of the random number interval.

[0079] In some embodiments, the control unit 6043 is specifically configured to: use channel functions to calculate user data and determine the probability that each data state of the user data is mapped to multiple channel output information.

[0080] In this embodiment of the invention, as shown in FIG11, the probability of different data states of channel input information being mapped to the output information of each channel follows a normal distribution. Therefore, the above probabilities P0(-7), P0(-6), P0(-5)...P0(+5), P0(+6), P0(+7), and P1(-7), P1(-6), P1(-5)...P1(+5), P1(+6), P1(+7) can be theoretically calculated by the control unit through the cumulative distribution function of the normal distribution. It should be noted that Figure 11 only shows the probability distribution under symmetrical channels for BPSK and AWGN. In this case, when the noise-adding fixed-point LLR values ​​x and y are opposites (i.e., x + y = 0), the probability P0(x) of data state "0" mapping to noise-adding fixed-point LLR value x is equal to the probability P1(y) of data state "1" mapping to noise-adding fixed-point LLR value y. Furthermore, the probability of different data states of channel input information mapping to the output information of each channel can also follow other channel functions, such as the pink noise distribution function, white noise distribution function, etc. Thus, the above probabilities can be theoretically calculated using the corresponding channel functions.

[0081] In some embodiments, at least one of the encoding circuit 6045, the control unit 6043, the decoding circuit 6046 and the channel model implementation circuit 500 is a dedicated integrated circuit.

[0082] In this embodiment of the invention, since the process of performing the soft decoding performance test of the test matrix does not require complex calculations, at least one of the encoding circuit 6045, the control unit 6043, the decoding circuit 6046 and the channel model implementation circuit 500 can be a dedicated integrated circuit, thereby simplifying circuit design and reducing costs.

[0083] As shown in FIG14, based on the above memory controller, the present invention also provides an electronic device 700, which includes a processor 6011 and a memory controller 604 in the above embodiment; wherein, the processor 6011 is configured to generate random number interval group information; and the control unit 6043 is further configured to transmit the random number interval group information to the channel model implementation circuit 500.

[0084] In this embodiment of the invention, the electronic device 700 can be understood with reference to the system 100 in FIG1. ​​Other details about the electronic device have been described in detail above, and will not be repeated here for the sake of brevity.

[0085] The electronic device 700 includes a processor 6011, which, exemplarily, may be located in the host 601. Thus, the processor 6011 can also be used to perform simulation calculations of the channel model based on a large amount of user data, thereby generating random interval group information. It is understood that the computing power of the processor 6011 in the host 601 can be stronger than that of the control unit 6043 in the memory controller 604, thus improving the efficiency of the simulation calculation to generate random interval group information faster, while further saving the hardware and software resources of the memory controller 604. The control unit 6043 is used to transmit the random interval group information generated by the processor 6011 to the channel model implementation circuit 500. In some embodiments, the control unit 6043 may also temporarily store the random interval group information in the cache memory 6047 and / or the memory device 603, and provide the random interval group information to the channel model implementation circuit 500 when performing software decoding performance testing of the test parity matrix. For example, memory system 602 includes memory controller 604 and memory device 603.

[0086] In some embodiments, the processor 6011 is specifically configured to: simulate or calculate user data to determine the probability that the user data is mapped to multiple channel output information; generate multiple random number intervals that correspond one-to-one with the multiple channel output information based on the probability that the user data is mapped to multiple channel output information and a random number preset value; the random number preset value is greater than or equal to the random number generated by the channel model implementation sub-circuit; and generate a random number interval group information that includes the mapping relationship between the multiple random number intervals and the multiple channel output information.

[0087] In some embodiments, the processor 6011 is specifically configured to: calculate the probability of mapping user data to multiple channel output information by a random number preset value, and obtain the size of multiple random number intervals that correspond one-to-one with the multiple channel output information; and generate random number intervals based on the size of the random number intervals.

[0088] In some embodiments, the processor 6011 is specifically configured to: use channel functions to calculate user data and determine the probability that each data state of the user data is mapped to multiple channel output information.

[0089] The process by which the processor 6011 generates random number interval group information in the above embodiments has been described in detail in the embodiments related to the memory controller 604, and will not be repeated here for the sake of brevity.

[0090] Based on the above-described channel model implementation circuit, this embodiment of the invention also provides a channel model implementation method, as shown in Figure 16. The channel model implementation method includes the following steps:

[0091] Step S10: Generate random numbers;

[0092] Step S20: Based on the random number, random number interval group information and each sub-data of the channel input information, determine the channel output information corresponding to each sub-data of the channel input information; wherein, the sub-data includes at least two data states, and the random number interval group information includes the mapping relationship between multiple random number intervals and multiple channel output information under different data states.

[0093] In this embodiment of the invention, multiple random number intervals and multiple channel output information can be mapped in advance by means of simulation statistics, etc. Then, the channel output information corresponding to each sub-data of the channel input information can be determined directly based on the random number interval group information containing the above mapping relationship. In this way, the channel model implementation method does not need to perform a lot of calculations, which is beneficial to saving software and hardware resources.

[0094] In some embodiments, the channel model implementation method further includes: receiving random interval group information; wherein, the sub-data includes N data states, the random interval group information includes N sub-random interval group information corresponding one-to-one with the N data states, and N is an integer greater than 1; the Pth sub-random interval group information includes the mapping relationship between multiple random intervals and multiple channel output information corresponding to the Pth data state, and P is an integer greater than or equal to 1, and P is less than or equal to N.

[0095] In some embodiments, in the information of the Pth sub-random number interval group, the size of the random number interval is positively correlated with the probability that the Pth data state is mapped to the corresponding channel output information.

[0096] In some embodiments, generating random numbers includes: generating multiple random numbers, the number of random numbers being the same as the number of sub-data of the channel input information; determining the channel output information corresponding to each sub-data of the channel input information based on the random numbers, random number interval group information, and channel input information, including: determining the random number interval corresponding to each random number in the first sub-random number interval group information to the Nth sub-random number interval group information; and determining the channel output information corresponding to each sub-data of the channel input information based on the random number interval where each random number is located and the data state of each sub-data of the channel input information.

[0097] In some embodiments, determining the random number interval corresponding to each random number in the information from the first sub-random number interval group to the Nth sub-random number interval group includes: comparing the random number with multiple random number intervals in each sub-random number interval group to determine the N random number intervals corresponding to the random number in the information from the first sub-random number interval group to the Nth sub-random number interval group; determining the channel output information corresponding to each sub-data of the channel input information based on the random number interval where each random number is located and the data state of each sub-data of the channel input information, including: outputting the N channel output information corresponding to the N random number intervals; and outputting one of the N channel output information based on the data state of one sub-data of the channel input information.

[0098] In some embodiments, the sub-data includes a first data state and a second data state. The probability that the first data state maps to channel output information n is equal to the probability that the second data state maps to channel output information m, where n+m=0, and n and m are both integers. The first data state corresponds to the first sub-random number interval group information, and the second data state corresponds to the second sub-random number interval group information. Multiple random number intervals in the first sub-random number interval group information are the same as multiple random number intervals in the second sub-random number interval group information. The channel output information in the first sub-random number interval group information and the channel output information in the second sub-random number interval group information corresponding to the same random number interval are complementary. The channel model implementation method specifically includes: comparing the random number with multiple random number intervals in the first sub-random number interval group information, determining the random number interval corresponding to the random number, and outputting the first channel output information corresponding to the random number interval; outputting the first channel output information based on the data state of a sub-data of the channel input information as the first data state; or, outputting the flipped first channel output information based on the data state of a sub-data of the channel input information as the second data state.

[0099] In some embodiments, generating random numbers includes: generating multiple random numbers, the number of random numbers being the same as the number of sub-data of the channel input information; determining the channel output information corresponding to each sub-data of the channel input information based on the random numbers, random number interval group information, and channel input information, including: determining a sub-random number interval group information corresponding to each sub-data in N sub-random number interval group information based on the data state of each sub-data; determining the random number interval corresponding to each random number in the sub-random number interval group information, and outputting the channel output information corresponding to the random number interval.

[0100] The channel model implementation method mentioned in the above embodiments has been described in detail in the foregoing embodiments regarding the channel model implementation circuit, and will not be repeated here for the sake of brevity.

[0101] Figure 17 shows a flowchart of a software decoding performance test of an LDPC code check matrix provided by the present invention. The detailed steps have been described in the above embodiments and will not be repeated here.

[0102] Based on the above memory controller, the present invention also provides a memory system, including: at least one memory device; the memory controller in the above embodiment is coupled to at least one memory device and configured to control the memory device.

[0103] The structure and composition of the memory system described here can be found in the detailed description of Figures 1 to 6 and Figure 14. For the sake of brevity, they will not be repeated here. The memory device here can be the memory device 103 shown in Figures 1 to 6 and the memory device 603 described in Figure 14.

[0104] The features disclosed in the several device embodiments provided by the present invention can be arbitrarily combined without conflict to obtain new device embodiments.

[0105] The methods disclosed in the several method embodiments provided by the present invention can be arbitrarily combined without conflict to obtain new method embodiments.

[0106] The above description is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the protection scope of the present invention. [Simplified Explanation of the Diagram]

[0107] Figure 1 is a schematic diagram of an exemplary system with a memory system according to an embodiment of the present invention. Figure 2 is a schematic diagram of an exemplary memory card with a memory system according to an embodiment of the present invention. Figure 3 is a schematic diagram of an exemplary solid-state driver with a memory system according to an embodiment of the present invention. Figure 4 is a schematic diagram of an exemplary memory device including peripheral circuitry according to an embodiment of the present invention. Figure 5 is a schematic diagram of an exemplary memory including a storage array and peripheral circuitry according to an embodiment of the present invention. Figure 6 is a schematic diagram of another exemplary system with a memory system according to an embodiment of the present invention. Figure 7 is a process for generating a noisy fixed-point log-likelihood ratio using a channel model according to an embodiment of the present invention. Figure 8 is a schematic diagram of a channel model implementation circuit according to an embodiment of the present invention. Figure 9 is a schematic diagram of random number interval group information according to an embodiment of the present invention. Figure 10 is a schematic diagram of the probability of different data states of sub-data mapping to each channel output information according to an embodiment of the present invention. Figure 11 is a schematic diagram of the probability of different data states of channel input information mapping to each channel output information following a normal distribution according to an embodiment of the present invention. Figure 12 is a schematic diagram of the structure of a channel output information determination circuit according to an embodiment of the present invention. Figure 13 is a schematic diagram of the structure of a channel output information determination circuit according to an embodiment of the present invention. Figure 14 is a schematic diagram of an electronic device according to an embodiment of the present invention. Figure 15 is a schematic diagram of a control unit, encoding circuit, decoding circuit, and channel model implementation circuit according to an embodiment of the present invention. Figure 16 is a flowchart of the channel model implementation method according to an embodiment of the present invention. Figure 17 is a flowchart of the soft decoding performance test of the LDPC code parity check matrix according to an embodiment of the present invention.

Claims

1. A channel model implementation circuit, comprising at least one channel model implementation sub-circuit; The channel model implementation sub-circuit includes: a random number generation circuit configured to generate random numbers; and a channel output information determination circuit configured to receive a sub-data of channel input information and determine the channel output information corresponding to the sub-data based on the random number, random number interval group information, and the sub-data; wherein the sub-data includes at least two data states, and the random number interval group information includes a mapping relationship between multiple random number intervals and multiple channel output information under different data states.

2. The channel model implementation circuit according to claim 1, wherein the channel output information determining circuit is further configured to: receive random interval group information; wherein, The sub-data includes N data states, and the random number interval group information includes N sub-random number interval group information corresponding one-to-one with the N data states, where N is an integer greater than 1; the Pth sub-random number interval group information includes the mapping relationship between multiple random number intervals and multiple channel output information corresponding to the Pth data state, where P is an integer greater than or equal to 1 and P is less than or equal to N.

3. The channel model implementation circuit according to claim 2, wherein in the Pth sub-random number interval group information, the size of the random number interval is positively correlated with the probability that the Pth data state is mapped to the corresponding channel output information.

4. The channel model implementation circuit according to claim 2, wherein the channel output information determining circuit is specifically configured to: determine the random number interval corresponding to the random number in the information from the first sub-random number interval group to the Nth sub-random number interval group, and determine the channel output information corresponding to the sub-data based on the random number interval where the random number is located and the data state of the sub-data.

5. The channel model implementation circuit according to claim 4, wherein the channel output information determination circuit includes: The first comparison circuit is configured to: compare the random number with multiple random number intervals in each of the sub-random number interval groups, determine the N random number intervals corresponding to the random number in the first to Nth sub-random number interval groups, and output the N channel output information corresponding to the N random number intervals; the first selection circuit is configured to: output one of the N channel output information based on the data state of the sub-data.

6. The channel model implementation circuit according to claim 5, wherein the sub-data includes a first data state and a second data state, the probability that the first data state maps to channel output information n is equal to the probability that the second data state maps to channel output information m, wherein, n+m=0, where n and m are both integers; the first data state corresponds to the first sub-random number interval group information, and the second data state corresponds to the second sub-random number interval group information; multiple random number intervals in the first sub-random number interval group information are the same as multiple random number intervals in the second sub-random number interval group information; the channel output information in the first sub-random number interval group information and the channel output information in the second sub-random number interval group information corresponding to the same random number interval are complementary; the first comparison circuit is configured to: compare the random number with multiple random number intervals in the first sub-random number interval group information, determine the random number interval corresponding to the random number, and output the first channel output information corresponding to the random number interval; the first selection circuit is configured to: output the first channel output information based on the data state of the sub-data being the first data state; or, output the flipped first channel output information based on the data state of the sub-data being the second data state.

7. The channel model implementation circuit according to claim 2, wherein the channel output information determining circuit is specifically configured to: determine, based on the data state of the sub-data, one of the sub-random number interval groups corresponding to the sub-data in the N sub-random number interval groups; determine the random number interval corresponding to the random number in the sub-random number interval group information, and output the channel output information corresponding to the random number interval.

8. The channel model implementation circuit according to claim 7, wherein the channel output information determination circuit includes: The second selection circuit is configured to: based on the data state of the sub-data, output one of the N sub-random number interval group information corresponding to the data state of the sub-data; the second comparison circuit is configured to: compare the random number with multiple random number intervals in one of the sub-random number interval group information, determine the random number interval corresponding to the random number, and output the channel output information corresponding to the random number interval.

9. The channel model implementation circuit according to claim 1, wherein the channel model implementation circuit further comprises: A storage component for storing the random number interval group information.

10. The channel model implementation circuit according to claim 1, wherein the sub-data includes Q bits, and the sub-data includes 2Q data states, where Q is a positive integer.

11. The channel model implementation circuit according to claim 1, wherein the channel input information includes encoded data and the channel output information includes a noisy fixed-point log-likelihood ratio.

12. A memory controller, comprising a debugging circuit and a control unit; said debugging circuit comprising a channel model implementation circuit, an encoding circuit, and a decoding circuit as described in any one of claims 1 to 11; wherein, The control unit is configured to output raw data; the encoding circuit is configured to encode the raw data to generate channel input information; and the decoding circuit is configured to obtain decoded data based on the test verification matrix and the channel output information corresponding to each sub-data of the channel input information.

13. The memory controller according to claim 12, wherein the control unit is further configured to: simulate or calculate user data to determine the probability that the user data is mapped to multiple channel output information; generate multiple random number intervals corresponding one-to-one with the multiple channel output information based on the probability that the user data is mapped to the multiple channel output information and a random number preset value; wherein the random number preset value is greater than or equal to the random number generated by the channel model implementation sub-circuit; and generate random number interval group information including the mapping relationship between the multiple random number intervals and the multiple channel output information.

14. The memory controller according to claim 13, wherein the control unit is specifically configured to: calculate the probability of mapping the user data to the output information of the multiple channels by the random number preset value, respectively, to obtain the size of a plurality of random number intervals corresponding one-to-one with the output information of the multiple channels; and generate the random number interval based on the size of the random number interval.

15. The memory controller according to claim 13, wherein the control unit is specifically configured to: calculate the user data using a channel function to determine the probability that each data state of the user data is mapped to the output information of a plurality of channels.

16. The memory controller according to claim 12, wherein the control unit is further configured to: compare the decoded data with the original data and output a decoding performance test result; and determine a verification matrix for decoding operation based on the decoding performance test results corresponding to a plurality of the verification matrices to be tested.

17. The memory controller according to claim 12, wherein at least one of the encoding circuit, the control unit, the decoding circuit, and the channel model implementation circuit is a dedicated integrated circuit.

18. An electronic device comprising a processor and a memory controller as claimed in claim 12; wherein, The processor is configured to generate random number interval group information; the control unit is further configured to transmit the random number interval group information to the channel model implementation circuit.

19. The electronic device according to claim 18, wherein the processor is specifically configured to: simulate or calculate user data to determine the probability that the user data is mapped to multiple channel output information; generate multiple random number intervals corresponding one-to-one with the multiple channel output information based on the probability that the user data is mapped to the multiple channel output information and a random number preset value; wherein the random number preset value is greater than or equal to the random number generated by the channel model implementation sub-circuit; and generate random number interval group information including the mapping relationship between the multiple random number intervals and the multiple channel output information.

20. The electronic device according to claim 19, wherein the processor is specifically configured to: calculate the probability of mapping the user data to the output information of the plurality of channels by the random number preset value, respectively, to obtain the size of a plurality of random number intervals corresponding one-to-one with the output information of the plurality of channels; and generate the random number intervals based on the size of the random number intervals.

21. The electronic device according to claim 19, wherein the processor is specifically configured to: calculate the user data using a channel function to determine the probability that each data state of the user data is mapped to a plurality of channel output information.

22. A method for implementing a channel model, comprising: generate random numbers; Based on the random number, random number interval group information, and each sub-data of the channel input information, the channel output information corresponding to each sub-data of the channel input information is determined; wherein, the sub-data includes at least two data states, and the random number interval group information includes the mapping relationship between multiple random number intervals and multiple channel output information under different data states.

23. The channel model implementation method according to request item 22 further includes: Receive random interval group information; wherein, the sub-data includes N data states, the random interval group information includes N sub-random interval group information corresponding one-to-one with the N data states, where N is an integer greater than 1; the Pth sub-random interval group information includes the mapping relationship between multiple random intervals and multiple channel output information corresponding to the Pth data state, where P is an integer greater than or equal to 1 and P is less than or equal to N.

24. The channel model implementation method according to claim 23, wherein in the information of the Pth sub-random number interval group, the size of the random number interval is positively correlated with the probability that the Pth data state is mapped to the corresponding channel output information.

25. The channel model implementation method according to claim 23, wherein the generation of random numbers includes: Generate multiple random numbers, the number of which is the same as the number of sub-data in the channel input information; The step of determining the channel output information corresponding to each sub-data of the channel input information based on the random number, random number interval group information, and each sub-data of the channel input information includes: determining the random number interval corresponding to each random number in the first sub-random number interval group information to the Nth sub-random number interval group information; and determining the channel output information corresponding to each sub-data of the channel input information based on the random number interval in which each random number is located and the data status of each sub-data of the channel input information.

26. The channel model implementation method according to claim 25, wherein determining the random number interval corresponding to each random number in the information from the first sub-random number interval group to the Nth sub-random number interval group includes: The random number is compared with multiple random number intervals in each of the sub-random number interval groups to determine the N random number intervals corresponding to the random number in the information from the first to the Nth sub-random number interval groups; the step of determining the channel output information corresponding to each sub-data of the channel input information based on the random number interval where each random number is located and the data state of each sub-data of the channel input information includes: outputting the N channel output information corresponding to the N random number intervals; and outputting one of the N channel output information based on the data state of one sub-data of the channel input information.

27. The channel model implementation method according to claim 25, wherein the sub-data includes a first data state and a second data state, the probability that the first data state maps to channel output information n is equal to the probability that the second data state maps to channel output information m, wherein, n+m=0, where n and m are both integers; the first data state corresponds to the first sub-random number interval group information, and the second data state corresponds to the second sub-random number interval group information; multiple random number intervals in the first sub-random number interval group information are the same as multiple random number intervals in the second sub-random number interval group information; the channel output information in the first sub-random number interval group information and the channel output information in the second sub-random number interval group information corresponding to the same random number interval are complementary; the method specifically includes: comparing the random number with multiple random number intervals in the first sub-random number interval group information, determining the random number interval corresponding to the random number, and outputting the first channel output information corresponding to the random number interval; outputting the first channel output information based on the data state of a sub-data of the channel input information as the first data state; or, outputting the flipped first channel output information based on the data state of a sub-data of the channel input information as the second data state.

28. The channel model implementation method according to request item 23, wherein the generation of random numbers includes: Generate multiple random numbers, the number of which is the same as the number of sub-data in the channel input information; The step of determining the channel output information corresponding to each sub-data of the channel input information based on the random number, random number interval group information, and channel input information includes: determining a sub-random number interval group information corresponding to each sub-data in N sub-random number interval group information based on the data state of each sub-data; determining the random number interval corresponding to each random number in the sub-random number interval group information, and outputting the channel output information corresponding to the random number interval.

29. A memory system comprising: At least one memory device; The memory controller as described in any one of claims 12 to 17 is coupled to the at least one memory device and configured to control the memory device.

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