Chip architecture of isolation converter and isolation converter

Abstract

The present disclosure relates to a field of chip design technology and discloses a chip architecture of an isolation converter and the isolation converter. The isolation converter comprises a primary control unit, an isolation communication unit, and a secondary control unit. The primary control unit is configured with a primary control chip, a primary drive chip, and a primary transistor. At least some of the primary control chip, the primary drive chip, and the primary transistor can be independently designed. The isolated communication department is configured with a primary demodulation chip and a secondary modulation chip, which are co-packaged. The secondary side control unit is configured with at least a secondary side main control chip and a secondary side rectifier transistor. The secondary side main control chip is configured to control the secondary side rectifier transistor and communicate with the primary side control chip through the secondary side modulation chip and the primary side demodulation chip. The chip architecture proposed in the present disclosure can form multiple co-packaging combinations, reducing chip development costs, improving co-packaging flexibility, and greatly enhancing applicability to different application scenarios.

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