Power stage control circuit applied to voltage converter

Abstract

A power stage control circuit applied to a voltage converter includes a current sensing circuit, a control circuit, and a driving circuit, wherein the voltage converter includes a first switch and a second switch. The current sensing circuit senses a current associated with the first switch, and converts current into a sensing voltage. The control circuit performs multiple first logical operations according to the sensing voltage, a second switch driving signal, a zero crossing detection voltage, a compensation voltage, and a reference voltage, in order to generate a modulation signal and a determination signal, for controlling turn-on and turn-off of the first switch and the second switch and dynamically setting an inductor peak current of an inductor, respectively. The driving circuit performs multiple second logical operations according to the modulation signal and the determination signal in order to generate a first switch driving signal and the second switch driving signal.

Description

Technical Field

[0001] This invention relates to voltage converters, and more particularly to a power stage control circuit for use in voltage converters. Prior Technology

[0002] In the field of buck converters, operating in pulse skip mode (PSM) improves light-load efficiency. Specifically, when a buck converter with PSM operates under light load conditions, the switching frequency between a high-side switch and a low-side switch in one of the power stages of the buck converter can be reduced to decrease power consumption caused by switching. Therefore, the desired light-load efficiency can be achieved through PSM technology. However, when the inductor current of the buck converter operates in discontinuous conduction mode (DCM), the peak current value of the inductor coupled between the high-side and low-side switches may be limited by certain parameters (such as input voltage, output voltage, minimum on-time of the high-side switch, and the inductance value of the inductor), which significantly reduces the design flexibility of the buck converter. Therefore, there is a great need for a novel power stage control circuit for buck converters that can set the peak current value of the inductor through multiple logic control operations. Summary of the Invention

[0003] Therefore, one of the objectives of this invention is to provide a power stage control circuit for a voltage converter to solve the above-mentioned problems.

[0004] According to an embodiment of the present invention, a power stage control circuit for a voltage converter is provided, wherein the voltage converter includes a power stage, the power stage including a first switch and a second switch, the first switch and the second switch being connected in series between an input voltage and a first reference voltage, and the input voltage being higher than the first reference voltage. The power stage control circuit includes a current sensing circuit, a control circuit, and a drive circuit. The current sensing circuit is used to sense a current associated with the first switch and convert the current into a sense voltage. The control circuit is used to perform a plurality of first logic operations based on the sense voltage, a second switch drive signal, a zero-crossover detection voltage, a compensation voltage, and a second reference voltage to generate a modulation signal and a decision signal for controlling the opening and closing of the first switch and the second switch respectively and dynamically setting a peak current of an inductor, wherein the inductor has a first terminal coupled between the first switch and the second switch, and a second terminal coupled to an output pin for providing an output voltage. The drive circuit is used to perform multiple second logic operations based on the modulation signal and the decision signal to generate a first switch drive signal and a second switch drive signal, so as to drive the first switch and the second switch respectively.

[0005] One advantage of this invention is that, by applying this invention to the power stage control circuit of a buck converter (especially the control circuit therein), when the inductor current of the buck converter operates in a discontinuous conduction mode, the peak inductor current of an inductor coupled between the high-side switch and the low-side switch of a power stage contained in the buck converter can be set to be greater than or equal to a reference current through logic control. This allows the peak inductor current to be free from the limitation (or control) of certain parameters (e.g., input voltage, output voltage, minimum turn-on time of the high-side switch, and inductance value of the inductor), and thus significantly improves the design flexibility of the buck converter. Furthermore, when the buck converter's inductor current operates in discontinuous conduction mode, and the peak inductor current is substantially equal to the reference current, the switching between the high-side and low-side switches can be controlled via modulation and decision signals. This ensures that the next charging cycle of the power stage only begins after the inductor current (i.e., the buck converter's inductor current) has been discharged to zero, thus preventing large output voltage ripple. In other words, when the buck converter operates under light load conditions, output voltage ripple can be effectively suppressed through the control circuit. Simple Explanation of the Diagram

[0006] Figure 1 is a block diagram of a power stage control circuit applied to a voltage converter according to an embodiment of the present invention. Figure 2 is a schematic diagram of a control circuit according to an embodiment of the present invention. Figure 3 is a schematic diagram of a driving circuit according to an embodiment of the present invention. Figure 4 is a schematic diagram of a timer circuit according to an embodiment of the present invention. Implementation

[0007] Figure 1 is a block diagram of a power stage control circuit 100 applied to a voltage converter (e.g., a buck converter) according to an embodiment of the present invention. As shown in Figure 1, the buck converter may include a power stage 50, which may be composed of a high-side switch SW HS and a low-side switch SW LS. The high-side switch SW HS has a first terminal coupled to the input voltage V IN and a second terminal coupled to the ground voltage GND. That is, the high-side switch SW HS and the low-side switch SW LS may be connected in series between the input voltage V IN and the ground voltage GND. An inductor L has a first terminal coupled to node N1 and a second terminal coupled to an output pin, wherein node N1 is located between the high-side switch SW HS and the low-side switch SW LS. This output pin is used to provide an output voltage V OUT, and a voltage V SW is provided at node N1. The output capacitor CO is coupled between the second terminal of the inductor L and the ground voltage GND. A load device can be modeled by a load resistor RLoad coupled between the output pin and the ground voltage GND, and the load current ILoad flows through the load resistor RLoad. Resistor R1 has a first terminal coupled to the second terminal of the inductor L and a second terminal coupled to the ground voltage GND. Resistor R2 has a first terminal coupled to the second terminal of resistor R1 and a second terminal coupled to the ground voltage GND. Resistors R1 and R2 can act as a voltage divider. The feedback node NF is located between resistors R1 and R2, and the feedback voltage VFB is provided at the feedback node NF for feedback control.

[0008] The power stage control circuit 100 can receive the feedback voltage VFB from the feedback node NF and control the switching of the high-side switch SWHS and the low-side switch SWLS according to the feedback voltage VFB. Specifically, the power stage control circuit 100 may include a high-side current sensing circuit 102, an error amplifier (EA) 104, a slope compensation circuit 106, a subtraction circuit 108, a control circuit 110, and a drive circuit 112. The high-side current sensing circuit 102 can be coupled to the first terminal of the high-side switch SW HS and can be used to perform a current sensing operation to generate a high-side sensing current associated with the high-side switch SW HS and convert the high-side sensing current into a high-side sensing voltage V HSEN. When the high-side switch SW HS is turned on (conducted) and the low-side switch SW LS is turned off (not conducted), the high-side sensing current is the inductance current IL flowing through the inductor L, and the conductance GC-HS of the high-side current sensing circuit 102 is the product of the inductance current IL and the reciprocal of the high-side sensing voltage V HSEN (i.e., GC-HS = IL / V HSEN).

[0009] Error amplifier 104 has a negative input (labeled "-" in Figure 1), a positive input (labeled "+" in Figure 1), and an output. The negative input receives a feedback voltage VFB from the feedback node NF, the positive input receives a reference voltage VREF, and the error amplifier voltage VEA is generated at the output. Slope compensation circuit 106 can be used to generate a slope compensation voltage VSC. Subtraction circuit 108 can be used to subtract the slope compensation voltage VSC from the error amplifier voltage VEA to generate a compensation voltage VCP (i.e., VCP = VEA - VSC).

[0010] The control circuit 110D can perform multiple first logic operations based on the compensation voltage VCP from the subtraction circuit 108, the high-side sensing voltage VHSEN from the high-side current sensing circuit 102, the low-side switch drive signal VLSG from the drive circuit 112, the zero-crossing detection voltage VZCD from the drive circuit 112, and the reference voltage VPKmin_ref to generate a modulation signal VMOD and a determination signal VPKmin_Det, which are used to control the switching of the high-side switch SWHS and the low-side switch SWLS (e.g., on and off) and dynamically set the peak inductor current IPK of the inductor L, wherein when the zero-crossing detection voltage VZCD has a high voltage level, it can be determined that the inductor current IL of the buck converter is operating in discontinuous conduction mode (DCM); the low-side switch drive signal VLSG can be used to drive the low-side switch SWLS; and the determination signal VPKmin_ref PKmin_Det can be used to determine the value of the inductor peak current I PK.

[0011] In this embodiment, the peak inductor current IPK can be dynamically set according to the reference current IPK_min, the determination signal VPKmin_Det, and the compensation voltage VCP. The reference current IPK_min is the product of the conductance GC-HS of the high-side current sensing circuit 102 and the reference voltage VPKmin_ref (i.e., IPK_min = GC-HS * VPKmin_ref). Specifically, refer to Figure 2. Figure 2 is a schematic diagram of a control circuit 200 according to an embodiment of the present invention, wherein the control circuit 110 shown in Figure 1 can be implemented by the control circuit 200. As shown in Figure 2, the control circuit 200 may include a discontinuous conduction mode detection circuit 202 (labeled as "DCM detection circuit" in Figure 2 for simplicity), a modulation circuit 204, and a current setting circuit 206.

[0012] The discontinuous conduction mode detection circuit 202 can be used to detect whether the inductor current IL of the buck converter operates in discontinuous conduction mode, and may include a pulse generator 208, an AND gate circuit 210, and a set-reset (SR) latch circuit 212. The pulse generator 208 can receive the low-side switch drive signal VLSG from the self-driving circuit 112 and generate a pulse signal VLSG_P based on the low-side switch drive signal VLSG. The AND gate circuit 210 can receive an inverted signal of the pulse signal VLSG_P and a zero-crossing detection voltage VZCD, and perform an AND operation on the inverted signal and the zero-crossing detection voltage VZCD to generate an AND gate output AND_1. The set-reset latch circuit 212 has a reset input (labeled "R" in Figure 2), a set input (labeled "S" in Figure 2), and an output (labeled "Q" in Figure 2). The reset input receives a pulse signal VLSG_P, the set input receives the AND gate output AND_1, and a discontinuous conduction mode detection signal VPKmin_set_OK is generated at the output to determine whether the inductor current IL of the buck converter is operating in discontinuous conduction mode. For example, when the discontinuous conduction mode detection signal VPKmin_set_OK has a high voltage level (i.e., the zero-crossover detection voltage VZCD also has a high voltage level), it can be determined that the inductor current IL of the buck converter is operating in discontinuous conduction mode.

[0013] The modulation circuit 204 may include multiple comparator circuits 214 and 216, a NAND gate circuit 218, and a gate circuit 220. Comparator circuit 214 has a negative input (labeled "-" in Figure 2) coupled to a reference voltage VPKmin_ref and a positive input (labeled "+" in Figure 2) coupled to a high-side sensed voltage VHSEN, and can be used to perform a comparison operation between the reference voltage VPKmin_ref and the high-side sensed voltage VHSEN to generate a comparison result COM_1. Comparator circuit 216 has a negative input (labeled "-" in Figure 2) coupled to a compensation voltage VCP and a positive input (labeled "+" in Figure 2) coupled to a high-side sensed voltage VHSEN, and can be used to perform a comparison operation between the compensation voltage VCP and the high-side sensed voltage VHSEN to generate a comparison result COM_2. The NAND circuit 218 can be used to perform a NAND operation on the discontinuous conduction mode detection signal VPKmin_set_OK and an inverted signal of the comparison result COM_1 to generate the NAND output NAND_1. The gate circuit 220 can be used to perform an AND operation on the NAND output NAND_1 and the comparison result COM_2 to generate a modulation signal VMOD, which is used to control the opening and closing of the high-side switch SW HS and the low-side switch SW LS.

[0014] The current setting circuit 206 may include a gate circuit 222, a delay circuit 224, an inverter circuit 226, and a D-type flip-flop (DFF) circuit 228. The gate circuit 222 can perform an AND operation on the discontinuous conduction mode detection signal VPKmin_set_OK and the comparison result COM_2 to generate a gate-controlled output AND_2. The delay circuit 224 can perform a delay operation on the comparison result COM_1 to generate a delayed result DCOM_1. The inverter circuit 226 can perform an inverting operation on the zero-crossover detection voltage VZCD to generate an inverted result IN_R. The D-type flip-flop circuit 228 has an input terminal (labeled "D" in Figure 2), a clock terminal, and a clear terminal (labeled "..." in Figure 2). The input terminal receives AND_2, the clock terminal receives the delayed result DCOM_1, the clear terminal receives the inverted result IN_R, and the decision signal VPKmin_Det is generated at the output terminal to dynamically set the peak inductance current IPK of the inductor L.

[0015] In detail, the control circuit 200 can dynamically set the peak inductor current IPK of inductor L through feedback control and the aforementioned multiple first logic operations. When the high-side switch SWHS is turned on, the peak inductor current IPK can be set to be substantially equal to the reference current IPK_min (i.e., IPK = IPK_min) because the voltage level of the decision signal VPK_Det is low, and the compensation voltage VCP is less than the reference voltage VPK_ref at the end of the high-side switch SWHS's on-time. In this case, the peak inductor current IPK can be set to be less than the reference current IPK_min (i.e., IPK < IPK_min). When the voltage level of the decision signal VPKmin_Det is low, and the compensation voltage VCP is equal to the reference voltage VPKmin_ref at the end of the high-side switch SWHS's on-time, the inductor peak current IPK can be set to be substantially equal to the reference current IPK_min (i.e., IPK = IPK_min). When the voltage level of the decision signal VPKmin_Det is low, and the compensation voltage VCP is greater than the reference voltage VPKmin_ref at the end of the high-side switch SWHS's on-time, the inductor peak current IPK can be set to be greater than the reference current IPK_min (i.e., IPK > IPK_min). Thus, when the inductor current IL of the buck converter operates in discontinuous conduction mode, the control circuit 200 can set the inductor peak current IPK to be greater than or equal to the reference current IPK_min (i.e., IPK > IPK_min). IPK_min allows the peak inductor current IPK to be free from the limitations (or dominance) of certain parameters (such as input voltage VIN, output voltage VOUT, minimum turn-on time of high-side switch SWHS, and inductance value of inductor L), thus significantly improving the design flexibility of buck converters.

[0016] Furthermore, when the inductor current IL of the buck converter operates in discontinuous conduction mode, and the peak inductor current IPK is substantially equal to the reference current IPK_min, the next charging cycle of power stage 50 will only begin after the inductor current IL flowing through inductor L has been discharged to zero by controlling the switching of the high-side switch SWHS and the low-side switch SWLS through the modulation signal VMOD and the decision signal VPKmin_Det. This avoids large ripple in the output voltage VOUT. In other words, when the buck converter operates under light load conditions, the output voltage ripple can be effectively suppressed by the control circuit 200.

[0017] Referring back to Figure 1. The drive circuit 112 receives the error amplifier voltage VEA from the error amplifier 104, the modulation signal VMOD from the control circuit 110, and the decision signal VPKmin_Det. Based on the error amplifier voltage VEA, the modulation signal VMOD, and the decision signal VPKmin_Det, it performs multiple second logic operations to generate the high-side switch drive signal VHSG and the aforementioned low-side switch drive signal VLSG, for driving the high-side switch SWHS and the low-side switch SWLS, respectively.

[0018] Figure 3 is a schematic diagram of a drive circuit 300 according to an embodiment of the present invention, wherein the drive circuit 112 shown in Figure 1 can be implemented by the drive circuit 300. As shown in Figure 3, the drive circuit 300 may include multiple comparator circuits 302 and 304, a sample and hold circuit 306 (labeled as "S / H circuit" in Figure 3 for simplicity), a timer circuit 308, a gate circuit 310, a set-reset latch circuit 312, a logic circuit 314, and multiple buffer circuits 316 and 318. The comparator circuit 302 has a negative input terminal (labeled "-" in Figure 3) for receiving the reference voltage VREF2, a positive input terminal (labeled "+" in Figure 3) for receiving the error amplifier voltage VEA, and an output terminal for outputting the comparison result COM_3. Comparator circuit 304 has a negative input terminal (labeled "-" in Figure 3) for receiving ground voltage GND, a positive input terminal (labeled "+" in Figure 3) for receiving voltage VSW, and an output terminal for outputting zero-crossover detection voltage VZCD. Sample and hold circuit 306 can be used to sample and hold the comparison result COM_3 to generate the output level detection voltage VEAOK of error amplifier 104.

[0019] The timer circuit 308 receives a high-side switch drive signal VHSG and a control signal VCOS from the logic circuit 314, and switches between oscillator (OSC) mode and timer mode based on the control signal VCOS. For example, when the control signal VCOS has a high voltage level, the timer circuit 308 switches to oscillator mode. When the control signal VCOS has a low voltage level, the timer circuit 308 switches to timer mode. In oscillator mode, the timer circuit 308 provides an oscillation frequency FS. In timer mode, the timer circuit 308 only discharges an internal capacitor through a switch controlled by the pulse signal VHSG_P for timing operations.

[0020] Specifically, refer to Figure 4. Figure 4 is a schematic diagram of a timer circuit 400 according to an embodiment of the present invention, wherein the timer circuit 308 shown in Figure 3 can be implemented by the timer circuit 400. As shown in Figure 4, the timer circuit 400 may include an AND gate circuit 402, an OR gate circuit 404, a current source 406, a switch 408, a comparator circuit 410, multiple pulse generators 412 and 414, and a set-reset latch circuit 416. The AND gate circuit 402 can be used to perform an AND operation on the control signal VCOS and the pulse signal VTRD_P to generate an AND gate output AND_3. The OR gate circuit 404 can be used to perform an OR operation on the AND gate output AND_3 and the pulse signal VHSG_P corresponding to the high-side switch drive signal VHSG to generate an OR gate output OR_1, for triggering the switch 408. Current source 406 has a first terminal coupled to the supply voltage VDD and a second terminal coupled to node N2, and is used to provide current IT, wherein voltage VT is provided at node N2. Switch 408 is coupled between node N2 and ground voltage GND. Capacitor CT is connected in parallel with switch 408.

[0021] Comparator circuit 410 has a negative input (labeled "-" in Figure 4) for receiving the reference voltage VTREF, a positive input (labeled "+" in Figure 4) for receiving the voltage VT, and an output for outputting the comparison result VTRD. Pulse generator 412 can receive the high-side switch drive signal VHSG and generate a pulse signal VHSG_P based on the high-side switch drive signal VHSG. Pulse generator 414 can receive the comparison result VTRD and generate a pulse signal VTRD_P based on the comparison result VTRD. Set-reset latch circuit 416 has a reset input (labeled "R" in Figure 4), a set input (labeled "S" in Figure 4), and an output (labeled "Q" in Figure 4), wherein the reset input receives the pulse signal VHSG_P, the set input receives the pulse signal VTRD_P, and the timer voltage VTim is generated at the output. In this embodiment, the oscillation frequency FS can be equal to a value obtained by dividing the current IT by the product of the capacitance CT and the reference voltage VTREF (that is, ).

[0022] Referring back to Figure 3, the gate circuit 310 can perform an AND operation on an inverted signal VPKmin_Det, an output level detection voltage VEAOK, and a timer voltage VTim to generate the gate output AND_4. The set-reset latch circuit 312 has a reset input (labeled "R" in Figure 3), a set input (labeled "S" in Figure 3), and an output (labeled "Q" in Figure 3), wherein the reset input receives the modulation signal VMOD, the set input receives the gate output AND_4, and the set-reset latch output SR_1 is generated at the output. Logic circuit 314 can be used to receive the set-reset latch output SR_1, the output level detection voltage VEAOK, the timer voltage VTim, the pulse signal VTRD_P, the decision signal VPKmin_Det, and the zero-crossing detection voltage VZCD, and to perform multiple third logic operations on the received signals / voltages to generate a high-side switch drive signal VHSG, a low-side switch drive signal VLSG, and a control signal VCOS. Buffer circuit 316 can be coupled between logic circuit 314 and the high-side switch SWHS, and is used to buffer / drive and transmit the high-side switch drive signal VHSG to the high-side switch SWHS. Similarly, buffer circuit 318 can be coupled between logic circuit 314 and the low-side switch SWLS, and is used to buffer / drive and transmit the low-side switch drive signal VLSG to the low-side switch SWLS. Since the focus of this invention is on the control circuit 110 / 200 (which generates the modulation signal VMOD and the determination signal VPKmin_Det for dynamically setting the inductor peak current IPK), and the operation of the logic circuit 314 is well known to those skilled in the art, further details of the logic circuit 314 will not be described in detail here.

[0023] In summary, by applying the present invention to the power stage control circuit 100 of a buck converter (especially the control circuits 110 / 200 therein), when the inductor current IL of the buck converter operates in discontinuous conduction mode, the peak inductor current IPK can be set to be greater than or equal to the reference current IPK_min (i.e., IPK) through logic control. The peak inductor current IPK is not limited (or dominated) by certain parameters (such as input voltage VIN, output voltage VOUT, minimum turn-on time of high-side switch SWHS, and inductance value of inductor L), thus significantly improving the design flexibility of the buck converter. Furthermore, when the buck converter's inductor current IL operates in discontinuous conduction mode, and the peak inductor current IPK is substantially equal to the reference current IPK_min, the switching of high-side switch SWHS and low-side switch SWLS can be controlled by the modulation signal VMOD and the determination signal VPKmin_Det. This ensures that the next charging cycle of power stage 50 only begins after the inductor current IL of inductor L (i.e., the inductor current IL of the buck converter) has been discharged to zero, preventing large ripple in the output voltage VOUT. In other words, when the buck converter operates under light load conditions, output voltage ripple can be effectively suppressed by the control circuits 110 / 200. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the scope of the claims of the present invention shall be covered by the present invention.

[0024] 50: Power stage 100: Power stage control circuit 102: High-side current sensing circuit 104: Error Amplifier 106: Slope Compensation Circuit 108: Subtraction Circuit 110,200: Control circuit 112,300: Drive circuit VFB: Feedback Voltage V REF, V PKmin_ref, V REF2, V TREF: Reference voltage VEA: Error amplifier voltage VSC: Slope Compensation Voltage VCP: Compensation voltage V LSG: Low-side switch drive signal V ZCD: Zero Crossover Detection Voltage V HSEN: High-side sensing voltage V MOD: Modulation Signal V PKmin_Det: Decision signal V HSG: High-side switch drive signal VIN: Input voltage SW HS: High-side switch SW LS: Low-side switch V SW, VT: Voltage GND: Grounding voltage N1, N2: Nodes L: Inductance IL: Inductor current CO: Output capacitor R1, R2: Resistors NF: Feedback Node V OUT: Output voltage I LOAD: Load current R LOAD: Load resistance 202: Discontinuous conduction mode detection circuit 204: Modulation Circuit 206: Current setting circuit 208,412,414: Pulse generator 210, 220, 222, 310, 402: and gate circuits 212, 312, 416: Reset - Set latch circuit 214, 216, 302, 304, 410: Comparator circuits 218: Non-gate circuit 224: Delay Circuit 226: Inverter Circuit 228: Type D flip-flop circuit V LSG_P, VTRD_P, V HSG_P: Pulse signal AND_1, AND_2, AND_4: and gate outputs V PKmin_set_OK: Detection signal for discontinuous conduction mode. COM_1,COM_2,COM_3,V TRD: Comparison Results NAND_1: Non-gate output DCOM_1: Delayed Result IN_R: The result after inversion 306: Sample and Hold Circuit 308, 400: Timer circuit 314: Logic Circuits 316, 318: Buffer circuits V COS: Control Signal VEAOK: Output level detection voltage V Tim: Timer voltage SR_1: Settings - Reset Latch Output 404: OR gate circuit 406: Current Source 408: Switch OR_1: OR gate output VDD: Supply voltage IT: Current CT: Capacitor

Claims

1. A power stage control circuit for a voltage converter, wherein the voltage converter includes a power stage, the power stage including a first switch and a second switch, the first switch and the second switch being connected in series between an input voltage and a first reference voltage, the input voltage being higher than the first reference voltage, and the power stage control circuit including: a current sensing circuit for sensing a current associated with the first switch and converting the current into a sense voltage; A control circuit is configured to perform multiple first logic operations based on a sensed voltage, a second switch drive signal, a zero-crossover detection voltage, a compensation voltage, and a second reference voltage to generate a modulation signal and a decision signal, for controlling the opening and closing of the first switch and the second switch respectively and dynamically setting a peak inductor current of an inductor, wherein the inductor has a first terminal coupled between the first switch and the second switch, and a second terminal coupled to an output pin for providing an output voltage; and a drive circuit is configured to perform multiple second logic operations based on the modulation signal and the decision signal to generate a first switch drive signal and the second switch drive signal, for driving the first switch and the second switch respectively.

2. The power stage control circuit as described in claim 1 further comprises: an error amplifier for receiving a feedback voltage and a third reference voltage to generate an error amplifier voltage; and a subtraction circuit for subtracting a slope compensation voltage from the error amplifier voltage to generate the compensation voltage.

3. The power stage control circuit as described in claim 1, wherein the peak current of the inductor is dynamically set based on a reference current, the decision signal, and the compensation voltage; and the reference current is the product of the second reference voltage and one conductance of the current sensing circuit.

4. The power stage control circuit as described in claim 3, wherein when the first switch is turned on, a voltage level of the determination signal is switched from a first level to a second level, the peak current of the inductor is set to be equal to the reference current; and the first level is lower than the second level.

5. The power stage control circuit as described in claim 3, wherein when a voltage level of the decision signal is lower than a first level of a second level, and the compensation voltage is less than the second reference voltage at the end of an on-time of the first switch, the peak current of the inductor is set to be less than the reference current.

6. The power stage control circuit as described in claim 3, wherein when a voltage level of the decision signal is lower than a first level of a second level, and the compensation voltage is equal to the second reference voltage at the end of an on-time of the first switch, the peak current of the inductor is set to be equal to the reference current.

7. The power stage control circuit as described in claim 3, wherein when a voltage level of the decision signal is lower than a first level of a second level, and the compensation voltage is greater than the second reference voltage at the end of an on-time of the first switch, the peak current of the inductor is set to be greater than the reference current.

8. The power stage control circuit as described in claim 1, wherein the control circuit comprises: a discontinuous conduction mode detection circuit, comprising: a pulse generator for receiving the second switch drive signal from the drive circuit and generating a pulse signal based on the second switch drive signal; a first gate circuit for performing an AND operation between an inverted signal of the pulse signal and the zero-crossing detection voltage to generate a first gate output; and a set-reset latch circuit having a reset input, a set input, and an output, wherein the reset input receives the pulse signal, the set input receives the first gate output, and a discontinuous conduction mode detection signal is generated at the output to determine whether an inductor current of the voltage converter operates in a discontinuous conduction mode.

9. The power stage control circuit as described in claim 8, wherein the control circuit further comprises: a modulation circuit comprising: a first comparator circuit having a negative input terminal coupled to the second reference voltage and a positive input terminal coupled to the sensed voltage; a second comparator circuit having a negative input terminal coupled to the compensation voltage and a positive input terminal coupled to the sensed voltage; an inverting gate circuit for performing a NAND operation on the discontinuous conduction mode detection signal and an inverted signal output from one of the first comparator circuits to generate an inverting gate output; and a second gate circuit for performing an AND operation on the inverting gate output and an output from the second comparator circuit to generate the modulation signal.

10. The power stage control circuit as described in claim 9, wherein the control circuit further comprises: a current setting circuit, including: a third gate circuit for performing an AND operation between the discontinuous conduction mode detection signal and the output of the second comparator circuit to generate a third gate output; and a delay circuit for performing a delay operation on the output of the first comparator circuit to generate a delayed result; An inverter circuit is used to invert the zero-crossover detection voltage to produce an inverted result. And a D-type flip-flop, having an input terminal, a clock terminal, a clear terminal and an output terminal, wherein the input terminal receives the third gate output, the clock terminal receives the delayed result, the clear terminal receives the inverted result, and the decision signal is generated at the output terminal.

11. The power stage control circuit as described in claim 1, wherein a reference current is the product of the second reference voltage and a conductance of the current sensing circuit; and when an inductor current of the voltage converter operates in a discontinuous conduction mode, the peak inductor current of the inductor is set to be greater than or equal to the reference current.

12. The power stage control circuit as described in claim 1, wherein a reference current is the product of the second reference voltage and a conductance of the current sensing circuit; and when an inductor current of the voltage converter operates in a discontinuous conduction mode and the peak inductor current of the inductor is equal to the reference current, the next charging cycle of the power stage will only be performed after the inductor current has been discharged to zero.

13. The power stage control circuit as described in claim 1, wherein the voltage converter is a buck converter.

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