Current-voltage converting circuit
Patent Information
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- NAT SUN YAT SEN UNIV
- Filing Date
- 2025-01-21
- Publication Date
- 2026-08-01
AI Technical Summary
Existing current-to-voltage conversion circuits for photocurrent signals in optical neural networks face challenges in maintaining low power consumption and effectively converting weak photocurrents while minimizing noise and mismatch influences.
A current-to-voltage conversion circuit with a transimpedance amplifier, feedback circuit, adjustable voltage gain unit, and buffer, utilizing differential architecture and feedback mechanisms to reduce noise and mismatch, and adjust DC bias and amplitude.
The circuit achieves efficient conversion and amplification of photocurrent signals with reduced noise interference and improved bandwidth, allowing for stable operation and wider application range.
Smart Images
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Abstract
Description
[Technical Field]
[0001] This invention relates to a current-to-voltage conversion circuit, and more particularly to a current-to-voltage conversion circuit for a photocurrent signal. [Previous Technology]
[0002] Deep learning is an algorithm that uses neural network architecture to learn the features of data. One type of optical neural network (PNN) has high-speed computing capabilities and low energy consumption during the learning process. However, since the photocurrent signal generated by the optical neural network is quite weak, it must be converted into a voltage form suitable for the back-end circuit through a transimpedance amplifier before learning can be performed. In addition, the transimpedance amplifier must be kept at low power consumption to avoid excessive heat generation affecting other electronic systems. Therefore, the transimpedance amplifier is one of the key technologies in optical neural networks. [Summary of the Invention]
[0003] The main purpose of this invention is to provide a current-to-voltage conversion circuit, wherein the transimpedance amplifier has the advantages of simple structure and easy implementation, and the DC bias and amplitude of the output signal can be adjusted by external voltage.
[0004] A current-to-voltage conversion circuit of the present invention includes a transimpedance amplifier, a feedback circuit, an adjustable voltage gain unit, and a buffer. The transimpedance amplifier has a differential pair, a current adjustment unit, and an output unit. The differential pair receives a first input voltage and a second input voltage via a first differential input terminal and a second differential input terminal, and generates a first differential current and a second differential current. The current adjustment unit is electrically connected to the differential pair to receive the first differential current and the second differential current. The current adjustment unit also receives a feedback voltage via a feedback voltage input terminal. The output unit is electrically connected to the differential pair and outputs a first output voltage via a first differential output terminal and a second differential output terminal. The feedback circuit is electrically connected to the transimpedance amplifier to receive the first output voltage and the second output voltage from the first differential output terminal and the second differential output terminal, and the feedback circuit outputs the feedback voltage. The adjustable voltage gain unit has at least one voltage-controlled gain amplifier, which is electrically connected to the transimpedance amplifier to receive the first output voltage and the second output voltage, and the voltage-controlled gain amplifier outputs a first amplified output voltage and a second amplified output voltage. The buffer is electrically connected to the adjustable voltage gain unit to receive the first amplified output voltage and the second amplified output voltage, and the buffer outputs a first differential output voltage and a second differential output voltage.
[0005] The current-to-voltage conversion circuit of the present invention reduces the influence of mismatch and input noise by means of the differential architecture of the transimpedance amplifier, and can adjust the DC bias of the output signal of the transimpedance amplifier by means of the feedback of the feedback circuit. The current-to-voltage conversion circuit achieves the conversion of current signal by means of the adjustable voltage gain unit and the buffer outputting the amplified voltage signal.
Implementation Method
[0006] Please refer to Figure 1, which is a circuit diagram of a current-to-voltage conversion circuit 100 according to one embodiment of the present invention. The current-to-voltage conversion circuit 100 has a transimpedance amplifier 110, a feedback circuit 120, an adjustable voltage gain unit 130 and a buffer 140. The transimpedance amplifier 110 is electrically connected to an optical sensor PD (Photonic Detector) so that the optical sensor PD receives a first input voltage VIN and a second input voltage VIP. The first input voltage VIN and the second input voltage VIP are generated by the photocurrent output by the optical sensor PD through two load resistors RL1 and RL2. In addition to converting the photocurrent into voltage, the load resistors RL1 and RL2 can also provide voltage bias so that the optical sensor PD operates at a suitable potential.
[0007] Please refer to Figures 1 and 2. The transimpedance amplifier 110 receives the first input voltage VIN and the second input voltage VIP from the optical sensor PD and outputs a first output voltage VO1 and a second output voltage VO2. Figure 2 is a circuit diagram of the transimpedance amplifier 110. In this embodiment, the transimpedance amplifier 110 has a differential pair 111, a current adjustment unit 112, an output unit 113, a first differential load pair 114, a first bias transistor pair 115, and a second bias transistor pair 116. The first bias transistor pair 115 and the second bias transistor pair 116 are electrically connected to the differential pair 111 and the output unit 113, respectively. The first bias transistor pair 115 and the second bias transistor pair 116 receive a bias voltage VB through a bias input terminal b to provide stable operating current to the differential pair 111 and the output unit 113, respectively.
[0008] Please refer to Figure 2. The differential pair 111 receives the first input voltage VIN and the second input voltage VIP via a first differential input terminal i1 and a second differential input terminal i2. In this embodiment, the differential pair 111 has a first NMOS transistor MN01 and a second NMOS transistor MN02. The gate of the first NMOS transistor MN01 is electrically connected to the first differential input terminal i1 to receive the first input voltage VIN, and the gate of the second NMOS transistor MN02 is electrically connected to the second differential input terminal i2 to receive the second input voltage VIP. The differential pair 111 generates a first differential current ID1 and a second differential current ID2 in the first NMOS transistor MN01 and the second NMOS transistor MN02 respectively according to the voltage difference between the first input voltage VIN and the second input voltage VIP.
[0009] The current adjustment unit 112 is electrically connected to the differential pair 111 to receive the first differential current ID1 and the second differential current ID2. The current adjustment unit 112 also receives a feedback voltage VFB via a feedback voltage input terminal fb. In this embodiment, the current adjustment unit 112 has a third NMOS transistor MN03 and a fourth NMOS transistor MN04. The gates of the third NMOS transistor MN03 and the fourth NMOS transistor MN04 receive the feedback voltage VFB. The sources of the third NMOS transistor MN03 and the fourth NMOS transistor MN04 are grounded. The drain of the third NMOS transistor MN03 is electrically connected to the source of the first NMOS transistor MN01 to receive the first differential current ID1. The drain of the fourth NMOS transistor MN04 is electrically connected to the source of the second NMOS transistor MN02 to receive the second differential current ID2. Since the third NMOS transistor MN03 and the fourth NMOS transistor MN04 use the feedback voltage VFB as the gate bias, the magnitude of the current passing through the third NMOS transistor MN03 and the fourth NMOS transistor MN04 can be controlled by the potential of the feedback voltage VFB, thereby controlling the magnitude of the first differential current ID1 and the second differential current ID2.
[0010] The first differential load pair 114 is electrically connected to the differential pair 111 to receive the first differential current ID1 and the second differential current ID2. In this embodiment, the first differential load pair 114 has a first PMOS transistor MP01 and a second PMOS transistor MP02. The sources of the first PMOS transistor MP01 and the second PMOS transistor MP02 receive the power supply voltage. The gates of the first PMOS transistor MP01 and the second PMOS transistor MP02 are interconnected and grounded. The drain of the first PMOS transistor MP01 is electrically connected to the drain of the first NMOS transistor MN01, and the drain of the second PMOS transistor MP02 is electrically connected to the drain of the second NMOS transistor MN02. The first differential current ID1 passes through the first PMOS transistor MP01, and the second differential current ID2 passes through the second PMOS transistor MP02. P01 and the second PMOS transistor M P02 are used to convert the first differential current ID1 and the second differential current ID2 into a first differential voltage VD1 and a second differential voltage VD2, respectively.
[0011] The first bias transistor pair 115 has a fifth NMOS transistor MN05 and a sixth NMOS transistor MN06. The gates of the fifth NMOS transistor MN05 and the sixth NMOS transistor MN06 receive the bias voltage VB from the bias input terminal b. The sources of the fifth NMOS transistor MN05 and the sixth NMOS transistor MN06 are grounded. The drain of the fifth NMOS transistor MN05 is electrically connected to the source of the first NMOS transistor MN01 and the drain of the third NMOS transistor MN03. The drain of the sixth NMOS transistor MN06 is electrically connected to the source of the second NMOS transistor MN02 and the drain of the fourth NMOS transistor MN04. The fifth NMOS transistor MN05 and the sixth NMOS transistor MN06 are used to provide operating current to the first NMOS transistor MN01 and the second NMOS transistor MN02.
[0012] The output unit 113 is electrically connected to the differential pair 111 and outputs the first output voltage VO1 and the second output voltage VO2 through a first differential output terminal o1 and a second differential output terminal o2. In this embodiment, the output unit 113 has a current control transistor pair 113a and a second differential load pair 113b. The current control transistor pair 113a has a seventh NMOS transistor MN07 and an eighth NMOS transistor MN08. The gate of the seventh NMOS transistor MN07 is electrically connected to the drain of the first NMOS transistor MN01 and the first PMOS transistor MP01 to receive the first differential voltage VD1. The gate of the eighth NMOS transistor MN08 is electrically connected to the drain of the second NMOS transistor MN02 and the second PMOS transistor MP02 to receive the second differential voltage VD2. The current-controlled transistor 113a outputs a first gain current IG1 and a second gain current IG2 to the seventh NMOS transistor MN07 and the eighth NMOS transistor MN08. The sources of the seventh NMOS transistor MN07 and the eighth NMOS transistor MN08 respectively output the first output voltage VO1 and the second output voltage VO2 to the first differential output terminal o1 and the second differential output terminal o2. The seventh NMOS transistor MN07 and the eighth NMOS transistor MN08 are controlled by the first differential voltage VD1 and the second differential voltage VD2, respectively, which changes the magnitude of the first gain current IG1 and the second gain current IG2, thereby affecting the gains of the first output voltage VO1 and the second output voltage VO2.
[0013] The second differential load pair 113b has a third PMOS transistor MP03 and a fourth PMOS transistor MP04. The gates of the third PMOS transistor MP03 and the fourth PMOS transistor MP04 are both grounded. The sources of the third PMOS transistor MP03 and the fourth PMOS transistor MP04 receive the power supply voltage. The drains of the third PMOS transistor MP03 and the fourth PMOS transistor MP04 are electrically connected to the drains of the seventh NMOS transistor MN07 and the eighth NMOS transistor MN08, respectively. The second differential load pair 113b is used to provide gain to the first gain current IG1 and the second gain current IG2 to improve the gain of the output unit 113.
[0014] The second bias transistor pair 116 has a ninth NMOS transistor MN09 and a tenth NMOS transistor MN10. The gates of the ninth NMOS transistor MN09 and the tenth NMOS transistor MN10 receive the bias voltage VB through the bias input terminal b. The sources of the ninth NMOS transistor MN09 and the tenth NMOS transistor MN10 are grounded. The drain of the ninth NMOS transistor MN09 is electrically connected to the source of the seventh NMOS transistor MN07, and the drain of the tenth NMOS transistor MN10 is electrically connected to the source of the eighth NMOS transistor MN08. The ninth NMOS transistor MN09 and the tenth NMOS transistor MN10 are used to provide operating current to the seventh NMOS transistor MN07 and the eighth NMOS transistor MN09, respectively.
[0015] Referring to Figure 2, preferably, the transimpedance amplifier 110 has a first capacitor C1 and a second capacitor C2. The two ends of the first capacitor C1 are electrically connected to the first differential input terminal i1 and the first differential output terminal o1, respectively. The two ends of the second capacitor C2 are electrically connected to the second differential input terminal i2 and the second differential output terminal o2, respectively. The first capacitor C1 and the second capacitor C2 are used to provide a feedback path, which can feed back the output change to the input terminal to reduce the hysteresis of the frequency response, thereby increasing the effective bandwidth of the transimpedance amplifier 110.
[0016] The transimpedance amplifier 110 achieves the conversion and amplification of photocurrent signals through differential architecture, feedback mechanism and frequency compensation, and has the effect of suppressing noise interference and improving effective bandwidth.
[0017] Please refer to Figure 1. The feedback circuit 120 is electrically connected to the transimpedance amplifier 110 to receive the first output voltage VO1 and the second output voltage VO2 through the first differential output terminal o1 and the second differential output terminal o2. The feedback circuit 120 outputs the feedback voltage VFB to the transimpedance amplifier 110 to form a feedback path. Please refer to Figure 3, which is a circuit diagram of the feedback circuit 120. The feedback circuit 120 has a voltage divider resistor 121, a feedback differential pair 122, a feedback load pair 123, and a current transistor 124. The voltage divider resistor 121 is electrically connected to the transimpedance amplifier 110 to receive the first output voltage VO1 and the second output voltage VO2, and the voltage divider resistor 121 outputs a divided voltage Vd. In this embodiment, the voltage divider resistor 121 has a first voltage divider resistor R1 and a second voltage divider resistor R2. The first voltage divider resistor R1 and the second voltage divider resistor R2 respectively receive the first output voltage VO1 and the second output voltage VO2 and divide them into the divided voltage Vd before transmitting it to the feedback differential pair 122. In this embodiment, the divided voltage Vd generated by the voltage divider resistor 121 is the average value between the first output voltage VO1 and the second output voltage VO2.
[0018] The feedback differential pair 122 is electrically connected to the voltage divider resistor 121 to receive the divided voltage Vd. The feedback differential pair 122 also receives a reference voltage VREF1, and the feedback differential pair 122 outputs the feedback voltage VFB. The feedback load pair 123 and the current transistor 124 are electrically connected to the feedback differential pair 122. In this embodiment, the feedback differential pair 122 has an eleventh NMOS transistor MN11 and a twelfth NMOS transistor MN12. The gate of the eleventh NMOS transistor MN11 is electrically connected to the voltage divider resistor 121 to receive the divided voltage Vd. The gate of the twelfth NMOS transistor MN12 receives the reference voltage VREF1, and the drain of the twelfth NMOS transistor MN12 outputs the feedback voltage VFB. The feedback load pair 123 serves as the active load of the feedback differential pair 122. The feedback load pair 123 has a fifth PMOS transistor MP05 and a sixth PMOS transistor MP06. The sources of the fifth PMOS transistor MP05 and the sixth PMOS transistor MP06 receive the power supply voltage. The gate and drain of the fifth PMOS transistor MP05 are electrically connected to the drain of the eleventh NMOS transistor MN11, and the gate and drain of the sixth PMOS transistor MP06 are electrically connected to the drain of the twelfth NMOS transistor MN12. The current transistor 124 has a thirteenth NMOS transistor MN13. The drain of the thirteenth NMOS transistor MN13 is electrically connected to the source of the eleventh NMOS transistor MN11 and the twelfth NMOS transistor MN12. The gate of the thirteenth NMOS transistor MN13 receives the bias voltage VB, and the source of the thirteenth NMOS transistor MN13 is grounded. The thirteenth NMOS transistor MN13 is biased by the bias voltage VB to provide a stable bias current to the feedback differential pair 122.
[0019] Wherein, when the voltage divider voltage Vd is greater than the reference voltage VREF1, the drain current of the sixth PMOS transistor MP06 increases, causing the feedback voltage VFB to rise, and the gate voltage of the current adjustment unit 112 of the transimpedance amplifier 110 to increase, thereby increasing the output DC bias of the transimpedance amplifier 110. Conversely, when the voltage divider voltage Vd is less than the reference voltage VREF1, the drain current of the sixth PMOS transistor MP06 decreases, causing the feedback voltage VFB to fall, and the gate voltage of the current adjustment unit 112 of the transimpedance amplifier 110 to decrease, thereby decreasing the output DC bias of the transimpedance amplifier 110, thereby stabilizing the DC bias of the transimpedance amplifier 110.
[0020] Referring to Figure 1, the adjustable voltage gain unit 130 has a voltage-controlled gain amplifier 131, which is electrically connected to the transimpedance amplifier 110 to receive the first output voltage VO1 and the second output voltage VO2, and the voltage-controlled gain amplifier 131 outputs a first amplified output voltage VAN and a second amplified output voltage VAP. Referring to Figure 4, which is a circuit diagram of the voltage-controlled gain amplifier 131 in this embodiment, the voltage-controlled gain amplifier 131 has a voltage-controlled gain differential pair 131a, a voltage-controlled gain load pair 131b, a plurality of control transistors 131c and a current transistor 131d. The voltage-controlled gain differential pair 131a is electrically connected to the transimpedance amplifier 110 to receive the first output voltage VO1 and the second output voltage VO2 and output the first amplified output voltage VAN and the second amplified output voltage VAP. In this embodiment, the voltage-controlled gain differential pair 131a has a fourteenth NMOS transistor MN14 and a fifteenth NMOS transistor MN15. The gate of the fourteenth NMOS transistor MN14 receives the first output voltage VO1 and outputs the second amplified output voltage VAP from its drain. The gate of the fifteenth NMOS transistor MN15 receives the second output voltage VO2 and outputs the first amplified output voltage VAN from its drain. The differential input signal is amplified by the voltage-controlled gain differential pair 131a.
[0021] The voltage-controlled gain load pair 131b is electrically connected to the voltage-controlled gain differential pair 131a. The voltage-controlled gain load pair 131b serves as the active load of the voltage-controlled gain differential pair 131a. In this embodiment, the voltage-controlled gain load pair 131b has a seventh PMOS transistor MP07 and an eighth PMOS transistor MP08. The sources of the seventh PMOS transistor MP07 and the eighth PMOS transistor MP08 receive the power supply voltage. The gates of the seventh PMOS transistor MP07 and the eighth PMOS transistor MP08 are interconnected and grounded. The drain of the seventh PMOS transistor MP07 is electrically connected to the drain of the fourteenth NMOS transistor MN14, and the drain of the eighth PMOS transistor MP08 is electrically connected to the drain of the fifteenth NMOS transistor MN15.
[0022] The control transistors 131c are electrically connected to the voltage control gain differential pair 131a and the voltage control gain load pair 131b, and the control transistors 131c are controlled by a control voltage V C1. In this embodiment, the control transistors 131c have a ninth PMOS transistor MP09 and a tenth PMOS transistor MP10. The source of the ninth PMOS transistor MP09 and the tenth PMOS transistor MP10 is electrically connected to the drain of the fourteenth NMOS transistor MN14 and the seventh PMOS transistor MP07. The drain of the ninth PMOS transistor MP09 and the tenth PMOS transistor MP10 is electrically connected to the drain of the fifteenth NMOS transistor MN15 and the eighth PMOS transistor MP08. The control voltage VC1 controls the conduction state of the ninth PMOS transistor MP09 and the tenth PMOS transistor MP10, changing their impedance and thus altering the equivalent load and gain of the entire circuit. Specifically, when the control voltage VC1 increases, the conduction state of the ninth PMOS transistor MP09 and the tenth PMOS transistor MP10 decreases, increasing the equivalent impedance and thus increasing the gain of the adjustable voltage gain unit 130. Conversely, when the control voltage VC1 decreases, the conduction state of the ninth PMOS transistor MP09 and the tenth PMOS transistor MP10 increases, decreasing the equivalent impedance and thus decreasing the gain of the adjustable voltage gain unit 130.
[0023] The current transistor 131d is electrically connected to the voltage-controlled gain differential pair 131a. In this embodiment, the current transistor 131d has a sixteenth NMOS transistor MN16. The drain of the sixteenth NMOS transistor MN16 is electrically connected to the source of the fourteenth NMOS transistor MN14 and the fifteenth NMOS transistor MN15. The gate of the sixteenth NMOS transistor MN16 receives the bias voltage VB, and the source of the sixteenth NMOS transistor MN16 is grounded. The sixteenth NMOS transistor MN16 is biased by the bias voltage VB to provide a stable bias current to the voltage-controlled gain differential pair 131a.
[0024] Referring to Figure 1, the buffer 140 is electrically connected to the adjustable voltage gain unit 130 to receive the first amplified output voltage VAN and the second amplified output voltage VAP, and the buffer 140 outputs a first differential output voltage VON and a second differential output voltage VOP. The buffer 140 is used to reduce output impedance, thereby reducing the impact of noise on the circuit. In this embodiment, the buffer 140 also receives a reference signal VREF2, which is used to control the fine adjustment of the first differential output voltage VON and the second differential output voltage VOP.
[0025] Please refer to Figure 5, which is a second embodiment of the present invention. The difference between the second and first embodiments is that the adjustable voltage gain unit 130 has a plurality of voltage-controlled gain amplifiers 131. Each voltage-controlled gain amplifier 131 is controlled by a control voltage V C1, V C2, V C3, V C4 and can change the gain of the overall circuit with different control voltages V C1, V C2, V C3, V C4. The multiple voltage-controlled gain amplifiers 131 allow for a larger adjustment range of the output voltage and a wider range of applications.
[0026] The current-to-voltage conversion circuit 100 of the present invention reduces the influence of mismatch and input noise by means of the differential architecture of the transimpedance amplifier 110, and can adjust the DC bias of the output signal of the transimpedance amplifier 110 through the feedback of the feedback circuit 120. The current-to-voltage conversion circuit 100 also achieves the conversion of current signal by means of the amplified voltage signal output by the adjustable voltage gain unit 130 and the buffer 140.
[0027] The scope of protection of this invention shall be determined by the appended claims. Any changes and modifications made by those skilled in the art without departing from the spirit and scope of this invention shall fall within the scope of protection of this invention. [Simplified Explanation of the Diagram]
[0028] Figure 1: A circuit diagram of a current-to-voltage conversion circuit according to one embodiment of the present invention. Figure 2: A circuit diagram of a transimpedance amplifier according to one embodiment of the present invention. Figure 3: A circuit diagram of a feedback circuit according to one embodiment of the present invention. Figure 4: A circuit diagram of a buffer according to one embodiment of the present invention. Figure 5: A circuit diagram of a current-to-voltage conversion circuit according to another embodiment of the present invention.
Claims
1. A current-to-voltage conversion circuit, comprising: a transimpedance amplifier having a differential pair, a current adjustment unit, and an output unit, wherein the differential pair receives a first input voltage and a second input voltage via a first differential input terminal and a second differential input terminal, and generates a first differential current and a second differential current; the current adjustment unit is electrically connected to the differential pair to receive the first differential current and the second differential current, and the current adjustment unit receives a feedback voltage via a feedback voltage input terminal; the output unit is electrically connected to the differential pair and outputs a first output voltage and a second output voltage via a first differential output terminal and a second differential output terminal; and a feedback circuit electrically connected to the transimpedance amplifier to receive the first output voltage and the second output voltage via the first differential output terminal and the second differential output terminal, and the feedback circuit outputs the feedback voltage. An adjustable voltage gain unit includes at least one voltage-controlled gain amplifier electrically connected to the transimpedance amplifier to receive the first output voltage and the second output voltage, and the voltage-controlled gain amplifier outputs a first amplified output voltage and a second amplified output voltage; and a buffer electrically connected to the adjustable voltage gain unit to receive the first amplified output voltage and the second amplified output voltage, and the buffer outputs a first differential output voltage and a second differential output voltage, wherein the transimpedance amplifier further includes a first differential load pair electrically connected to the differential pair to receive the first differential current and the second differential current, and the first differential load pair is used to convert the first differential current and the second differential current into a first differential voltage and a second differential voltage.
2. The current-to-voltage conversion circuit of claim 1, wherein the output unit of the transimpedance amplifier has a current-controlled transistor pair electrically connected to the differential pair and the first differential load pair to receive the first differential voltage and the second differential voltage, and the current-controlled transistor pair outputs a first gain current and a second gain current.
3. The current-to-voltage conversion circuit of claim 2, wherein the output unit has a second differential load pair electrically connected to the current control transistor pair to provide gain to the first gain current and the second gain current.
4. The current-to-voltage conversion circuit as described in claim 3, wherein the output unit is a common-drain architecture.
5. The current-to-voltage conversion circuit of claim 2, wherein the transimpedance amplifier further comprises a first bias transistor pair and a second bias transistor pair, the first bias transistor pair being electrically connected to the differential pair, the second bias transistor pair being electrically connected to the current control transistor pair of the output unit, and the first bias transistor pair and the second bias transistor pair receiving a bias voltage via a bias input terminal.
6. The current-to-voltage conversion circuit of claim 1, wherein the transimpedance amplifier has a first capacitor and a second capacitor, the two ends of the first capacitor being electrically connected to the first differential input terminal and the second differential output terminal respectively, and the two ends of the second capacitor being electrically connected to the second differential input terminal and the second differential output terminal respectively.
7. The current-to-voltage conversion circuit of claim 1, wherein the feedback circuit has a voltage divider resistor, a feedback differential pair, a feedback load pair and a current transistor, the voltage divider resistor is electrically connected to the transducer amplifier to receive the first output voltage and the second output voltage, and the voltage divider resistor outputs a divided voltage, the feedback differential pair is electrically connected to the voltage divider resistor to receive the divided voltage, and the feedback differential pair also receives a reference voltage, the feedback differential pair outputs the feedback voltage, the feedback load pair is electrically connected to the feedback differential pair, and the current transistor is electrically connected to the feedback differential pair.
8. The current-to-voltage conversion circuit of claim 1, wherein the voltage-controlled gain amplifier has a voltage-controlled gain differential pair, a voltage-controlled gain load pair, a plurality of control transistors and a current transistor, the voltage-controlled gain differential pair being electrically connected to the transimpedance amplifier to receive the first output voltage and the second output voltage and output the first amplified output voltage and the second amplified output voltage, the voltage-controlled gain load pair being electrically connected to the voltage-controlled gain differential pair, the control transistors being electrically connected to the voltage-controlled gain differential pair and the voltage-controlled gain load pair, and the control transistors being controlled by a control voltage, and the current transistor being electrically connected to the voltage-controlled gain differential pair.
9. The current-to-voltage conversion circuit of claim 8, wherein the adjustable voltage gain unit has a plurality of voltage-controlled gain amplifiers, each of which is controlled by a control voltage.