High-speed comparator with dynamic threshold voltage adjustment function
Patent Information
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- NATIONAL YUNLIN UNIVERSITY OF SCIENCE AND TECHNOLOGY
- Filing Date
- 2025-01-22
- Publication Date
- 2026-08-01
AI Technical Summary
Existing comparators in high-speed applications, such as SAR ADCs, face challenges in achieving faster signal processing times.
A high-speed comparator with dynamic threshold voltage adjustment using a critical voltage adjustment circuit that generates feedback voltages to adjust the critical voltages of transistors in differential input stages, accelerating the signal processing speed without altering the original circuit architecture.
The comparator achieves significant improvements in signal processing time by dynamically adjusting transistor critical voltages, enhancing switching speed and reducing processing time without affecting the reset time or circuit architecture.
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Abstract
Description
Technical Field
[0001] This invention relates to a comparator technology, and more particularly to a high-speed comparator that dynamically adjusts the threshold voltage and improves signal processing time. Prior Technology
[0002] Existing comparators compare the voltages at the inverting input (–) and the non-inverting input (+). When the voltage at the non-inverting input is greater than the voltage at the inverting input (–), the comparator outputs a high level, representing logic 1; when the voltage at the non-inverting input is less than the voltage at the inverting input (–), the comparator outputs a low level, representing logic 0. Comparators can be used in analog integrated circuits such as analog-to-digital converters (ADCs). With the increasing prevalence of high-speed applications of successive-approximation ADCs (SAR ADCs), the speed of comparators is also required to be faster. Therefore, improving the signal processing time of high-speed comparators is a current research direction. Summary of the Invention
[0003] Therefore, the object of the present invention is to provide a high-speed comparator that dynamically adjusts the threshold voltage and improves signal processing time.
[0004] Therefore, the high-speed comparator of the present invention with dynamic adjustment of critical voltage includes a non-inverting input terminal, an inverting input terminal, a first output terminal, a second output terminal, a critical voltage adjustment circuit, a first differential input stage, a second differential input stage, and an output stage.
[0005] The non-inverting input terminal is used to receive a first input signal. The inverting input terminal is used to receive a second input signal. The first output terminal is used to output a first output signal, the phase change of which is related to the first input signal and the second input signal. The second output terminal is used to output a second output signal that is inverted at the position of the first output signal.
[0006] The critical voltage adjustment circuit is electrically connected to the first output terminal and the second output terminal to receive the first output signal and the second output signal respectively, and generates a first feedback voltage positively correlated with the first output signal based on the first output signal, and generates a second feedback voltage positively correlated with the second output signal based on the second output signal.
[0007] The first differential input stage is electrically connected to the non-inverting input terminal, the inverting input terminal, the second output terminal, and the critical voltage adjustment circuit to receive the first input signal, the second input signal, the second output signal, and the second feedback voltage, respectively. The first differential input stage has a plurality of transistors, each transistor having a base electrically connected to the critical voltage adjustment circuit to receive the second feedback voltage, so that the second feedback voltage is used to adjust the first critical voltage of each transistor of the first differential input stage. The first differential input stage generates a first comparison signal based on the first input signal, the second input signal, the second output signal, and each of the first critical voltages.
[0008] The second differential input stage is electrically connected to the non-inverting input terminal, the inverting input terminal, the first output terminal, and the critical voltage adjustment circuit to receive the first input signal, the second input signal, the first output signal, and the first feedback voltage, respectively. The second differential input stage has a plurality of transistors, each transistor having a base electrically connected to the critical voltage adjustment circuit to receive the first feedback voltage, so that the first feedback voltage is used to adjust the second critical voltage of each transistor of the second differential input stage. The second differential input stage generates a second comparison signal based on the first input signal, the second input signal, the second output signal, and each of the second critical voltages.
[0009] The output stage is electrically connected to the first output terminal, the second output terminal, the first differential input stage, and the second differential input stage to receive the first comparison signal and the second comparison signal respectively, and to generate the first output signal and the second output signal respectively based on the first comparison signal and the second comparison signal.
[0010] The advantages of this invention are: by using the first feedback voltage and the second feedback voltage output by the critical voltage adjustment circuit to dynamically adjust the critical voltage of the metal-oxide-semiconductor, the comparator is accelerated by adjusting the substrate electrode pins of the input transistor without affecting the original circuit architecture, and there is a significant improvement in signal processing time. Simple Explanation of the Diagram
[0011] Other features and effects of the present invention will be clearly presented in the embodiments with reference to the drawings, wherein: Figure 1 is a circuit diagram of an embodiment of the high-speed comparator with dynamic adjustment of critical voltage function according to the present invention; Figure 2 is a current-voltage curve of the NMOS substrate effect in this embodiment; Figure 3 is a current-voltage curve of the PMOS substrate effect in this embodiment; Figure 4 is a schematic diagram of the comparator's phase; and Figure 5 shows the simulation results of the comparator output in this case and the comparator in the previous case; and Figure 6 shows the output simulation results of comparing the comparator in this case with the comparator in the previous case when they are stacked together. Implementation
[0012] Before the present invention is described in detail, it should be noted that similar elements are represented by the same numbers in the following description.
[0013] Referring to Figure 1, an embodiment of the high-speed comparator with dynamic threshold voltage adjustment function of the present invention includes a non-inverting input terminal VIN+ for receiving a first input signal, an inverting input terminal VIN- for receiving a second input signal, a first output terminal X for outputting a first output signal, a second output terminal Y for outputting a second output signal inverted at the first output signal, a first differential input stage 1, a second differential input stage 2, an output stage 3, a threshold voltage adjustment circuit 4, and a seventh transistor M7.
[0014] The critical voltage adjustment circuit 4 is electrically connected to the first output terminal X and the second output terminal Y to receive the first output signal and the second output signal respectively, and generates a first feedback voltage X' positively correlated with the first output signal based on the first output signal, and generates a second feedback voltage Y' positively correlated with the second output signal based on the second output signal. The critical voltage adjustment circuit 4 includes a first auxiliary transistor F1, a second auxiliary transistor F2, a first load transistor L1, and a second load transistor L2.
[0015] The first auxiliary transistor F1 has a first terminal that receives an operating voltage VDD, a control terminal electrically connected to the first output terminal X to receive the first output signal, and a second terminal that outputs the first feedback voltage X'. The second auxiliary transistor F2 has a first terminal that receives the operating voltage VDD, a control terminal electrically connected to the first output terminal X to receive the second output signal, and a second terminal that outputs the second feedback voltage.
[0016] The first load transistor L1 has a first terminal electrically connected to the second terminal of the first auxiliary transistor F1, a control terminal electrically connected to the second terminal of the first auxiliary transistor F1, and a second terminal grounded. The second load transistor L2 has a first terminal electrically connected to the second terminal of the second auxiliary transistor F2, a control terminal electrically connected to the second terminal of the second auxiliary transistor F2, and a second terminal grounded (GND).
[0017] The first differential input stage 1 is electrically connected to the non-inverting input terminal VIN+, the inverting input terminal VIN-, the second output terminal Y, and the critical voltage adjustment circuit 4 to receive the first input signal, the second input signal, the second output signal, and the second feedback voltage Y', respectively. The first differential input stage 1 has a plurality of transistors, each transistor having a base electrically connected to the critical voltage adjustment circuit to receive the second feedback voltage, so that the second feedback voltage is used to adjust the first critical voltage of each transistor of the first differential input stage 1. The first differential input stage 1 generates a first comparison signal based on the first input signal, the second input signal, the second output signal, and each of the first critical voltages.
[0018] The first differential input stage 1 includes a first transistor M1, a second transistor M2, and a third transistor M3. The first transistor M1 has a first terminal electrically connected to a first common terminal CM1, a control terminal electrically connected to the non-inverting input terminal VIN+ to receive the first input signal, a second terminal electrically connected to a third common terminal CM3, and a base terminal electrically connected to the second auxiliary transistor F2 to receive the second feedback voltage Y'.
[0019] The second transistor M2 has a first terminal electrically connected to the first common terminal CM1, a control terminal electrically connected to the inverting input terminal VIN- to receive the second input signal, a second terminal electrically connected to the third common terminal CM3, and a base terminal electrically connected to the second auxiliary transistor F2 to receive the second feedback voltage Y'. The third transistor has a first terminal electrically connected to the first common terminal CM1, a control terminal electrically connected to the second output terminal Y to receive the second output signal, a second terminal electrically connected to the third common terminal CM3, and a base terminal electrically connected to the second auxiliary transistor F2 to receive the second feedback voltage Y'.
[0020] The second differential input stage 2 is electrically connected to the non-inverting input terminal VIN+, the inverting input terminal VIN-, the first output terminal X, and the critical voltage adjustment circuit 4 to receive the first input signal, the second input signal, the first output signal, and the first feedback voltage, respectively. The second differential input stage 2 has a plurality of transistors, each transistor having a base electrically connected to the critical voltage adjustment circuit 4 to receive the first feedback voltage X', so that the first feedback voltage X' is used to adjust the second critical voltage of each transistor of the second differential input stage 2. The second differential input stage 2 generates a second comparison signal based on the first input signal, the second input signal, the second output signal, and each of the second critical voltages.
[0021] The second differential input stage 2 includes a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6. The fourth transistor M4 has a first terminal electrically connected to a second common terminal CM2, a control terminal electrically connected to the inverting input terminal VIN- to receive the second input signal, a second terminal electrically connected to a third common terminal CM3, and a base terminal for receiving the first feedback voltage X'. The fifth transistor M5 has a first terminal electrically connected to the second common terminal CM2, a control terminal electrically connected to the non-inverting input terminal VIN+ to receive the first input signal, a second terminal electrically connected to the third common terminal CM3, and a base terminal for receiving the first feedback voltage X'. The sixth transistor M6 has a first terminal electrically connected to the second common terminal CM2, a control terminal electrically connected to the first output terminal X to receive the first output signal, a second terminal electrically connected to the third common terminal CM3, and a base terminal for receiving the first feedback voltage X'. The seventh transistor M7 has a first terminal electrically connected to the third common terminal CM3, a second terminal grounded, and a control terminal that receives a clock signal CLK.
[0022] To further explain, when the first input signal is at a high potential (hereinafter referred to as High, potential VDD) and the second input signal is at a low potential (hereinafter referred to as Low, potential GND), the first output signal potential will gradually decrease, and the second output signal potential will gradually increase. The first feedback voltage X' output from the second terminal of the first auxiliary transistor F1 will gradually decrease with the first output signal potential, and the second feedback voltage Y' output from the second terminal of the second auxiliary transistor F2 will gradually increase with the second output signal potential. Because the base terminal of the first transistor M1 that receives the first input signal receives the second feedback voltage Y', the current flowing through the first transistor M1... As the current gradually increases during the process (due to the first transistor being an NMOS, the base voltage Vb increases, the critical voltage Vthn decreases, and the current Id increases), it accelerates the rate at which the first output signal output from the first output terminal X becomes lower. In other words, a feedback mechanism can be used to dynamically adjust the critical voltage of the first transistor, thereby improving the signal processing speed. Conversely, as the potential of the second input signal gradually increases, the situation is completely reversed, thus accelerating the rate at which the second output signal output from the second output terminal Y becomes higher. This completes a positive feedback effect, resulting in an acceleration effect until the potentials of the second output signal and the first output signal reach VDD and GND, respectively.
[0023] Output stage 3 is electrically connected to the first output terminal X, the second output terminal Y, the first differential input stage 1, and the second differential input stage 2 to receive the first comparison signal and the second comparison signal, respectively, and to generate the first output signal and the second output signal based on the first comparison signal and the second comparison signal, respectively. The phase change of the first output signal is related to the voltage magnitude comparison of the first input signal and the second input signal. Output stage 3 includes a first output transistor MO1, a second output transistor MO2, a third output transistor MO3, a fourth output transistor MO4, a fifth output transistor MO5, a sixth output transistor MO6, a seventh output transistor MO7, and an eighth output transistor MO8.
[0024] The first output transistor MO1 has a first terminal electrically connected to the first output terminal X to output the first output signal, a second terminal receiving a working voltage VDD, and a control terminal electrically connected to the second output terminal Y to receive the second output signal.
[0025] The second output transistor MO2 has a first terminal electrically connected to the first output terminal X to output the first output signal, a second terminal electrically connected to a first common terminal CM1, and a control terminal electrically connected to the second output terminal Y to receive the second output signal.
[0026] The third output transistor MO3 has a first terminal electrically connected to the second output terminal Y, a second terminal receiving the operating voltage VDD, and a control terminal receiving a clock signal CLK. The fourth output transistor MO4 is electrically connected to the first terminal CM1, a second terminal receiving the operating voltage VDD, and a control terminal receiving the clock signal CLK.
[0027] The fifth output transistor MO5 has a first terminal electrically connected to the second output terminal Y to output the second output signal, a second terminal receiving a working voltage VDD, and a control terminal electrically connected to the first output terminal X to receive the first output signal.
[0028] The sixth output transistor MO6 has a first terminal electrically connected to the second output terminal Y to output the second output signal, a second terminal electrically connected to a second common terminal CM2, and a control terminal electrically connected to the first output terminal X to receive the first output signal.
[0029] The seventh output transistor MO7 has a first terminal electrically connected to the first output terminal X, a second terminal receiving the operating voltage VDD, and a control terminal receiving a clock signal CLK.
[0030] The eighth output transistor MO8 is electrically connected to the first terminal of the second common terminal CM2, a second terminal that receives the operating voltage VDD, and a control terminal that receives the clock signal CLK.
[0031] In this embodiment, the first transistor M1, the third transistor M3, the fourth transistor M4, the sixth transistor M6, the first auxiliary transistor F1, the second auxiliary transistor F2, the first load transistor L1, the second load transistor L2, the second output transistor MO2, and the sixth output transistor MO6 are N-type metal-oxide-semiconductor field-effect transistors (hereinafter referred to as NMOS). The second transistor M2, the fifth transistor M5, the first output transistor MO1, the third output transistor MO3, the fourth output transistor MO4, the fifth output transistor MO5, the seventh output transistor MO7, and the eighth output transistor MO8 are P-type metal-oxide-semiconductor field-effect transistors (hereinafter referred to as PMOS). Each of the first terminals of all transistors is a drain, each of the second terminals is a source, and each of the control terminals is a gate.
[0032] The following explains how adjusting the transistor's critical voltage Vth can improve signal processing speed. By adjusting the transistor's Vth according to the changes in the base potential with the first and second feedback voltages, the transistor can be turned on and off earlier, thus accelerating the overall operating speed. Figures 2 and 3 show the current and voltage curves of the body effect for NMOS and PMOS, respectively. The parameter Vb is the transistor's base voltage. For NMOS, the body effect with respect to Vth is as follows: Vbs increases, Vthn decreases, and Id increases. For PMOS, the body effect with respect to Vth is as follows: Vbs increases, |Vthp| increases, and Id decreases. This embodiment utilizes this characteristic to dynamically adjust the turn-on and turn-off speeds of some transistors in the comparator.
[0033] Referring to Figure 4, the amplification phase, regeneration phase, and reset phase of the comparator are explained. The amplification phase is defined as starting from the positive edge of the clock signal (CLK) and ending when the comparator output reaches close to the input common-mode voltage (Vcm). The regeneration phase is defined as starting from the bifurcation of the comparator output and ending when the two outputs reach close to VDD and GND, respectively. The reset phase starts from the negative edge of the clock signal and ends when the next positive edge of the clock signal arrives.
[0034] Referring to Figure 5, which shows the output simulation results of the comparator in this design and the existing comparator, it can be seen that the improved comparator in this design has a faster switching speed than the existing comparator, effectively improving (shortening) the amplification phase and the regeneration phase. Referring to Figure 6, which shows the output simulation results of the comparator in this design and the existing comparator stacked together, the difference between the improved and unimproved comparators is more obvious.
[0035] In summary, the above embodiments utilize the first feedback voltage X' and the second feedback voltage Y' output by the critical voltage adjustment circuit to dynamically adjust the critical voltage of the metal-oxide-semiconductor (MOSFET). By adjusting the substrate electrode pins of the input MOSFET, the comparator is accelerated. Its greatest advantage is that the additional components do not significantly affect the original circuit architecture, and it significantly improves signal processing time without affecting reset time. Therefore, it can indeed achieve the purpose of this invention.
[0036] However, the above description is merely an embodiment of the present invention and should not be construed as limiting the scope of the present invention. Any simple equivalent changes and modifications made in accordance with the scope of the patent application and the contents of the patent specification of the present invention shall still fall within the scope of the patent of the present invention.
[0037] 1: First differential input stage M1: First transistor M2: Second transistor M3: Third transistor 2: Second differential input stage M4: Fourth Transistor M5: Fifth Transistor M6: Sixth Transistor M7: Seventh Transistor 3: Output stage MO1: First output transistor MO2: Second output transistor MO3: Third output transistor MO4: Fourth output transistor MO5: Fifth output transistor MO6: Sixth Output Transistor MO7: Seventh Output Transistor MO8: Eighth Output Transistor CM1: First common terminal CM2: Second common terminal CM3: Third Common Terminal 4: Critical Voltage Adjustment Circuit F1: First auxiliary transistor F2: Second auxiliary transistor L1: First load transistor L2: Second load transistor VIN+: Non-inverting input terminal VIN-: Inverting input terminal X: First output terminal Y: Second output terminal VDD: Operating voltage X': First feedback voltage Y': Second feedback voltage
Claims
1. A high-speed comparator with dynamic threshold voltage adjustment function, comprising: a non-inverting input terminal for receiving a first input signal; an inverting input terminal for receiving a second input signal; a first output terminal for outputting a first output signal, the phase change of the first output signal being related to the first input signal and the second input signal; a second output terminal for outputting a second output signal inverted from the first output signal; and a threshold voltage adjustment circuit electrically connected to the first output terminal and the second output terminal to receive the first output signal and the second output signal respectively, and to generate a first feedback voltage positively correlated with the first output signal based on the first output signal, and a second feedback voltage positively correlated with the second output signal based on the second output signal. A first differential input stage is electrically connected to the non-inverting input terminal, the inverting input terminal, the second output terminal, and the critical voltage adjustment circuit to receive the first input signal, the second input signal, the second output signal, and the second feedback voltage, respectively. The first differential input stage has a plurality of transistors, each transistor having a base electrically connected to the critical voltage adjustment circuit to receive the second feedback voltage, such that the second feedback voltage is used to adjust the first critical voltage of each transistor of the first differential input stage. The first differential input stage generates a first comparison signal based on the first input signal, the second input signal, the second output signal, and each of the first critical voltages. A second differential input stage is electrically connected to the non-inverting input terminal, the inverting input terminal, the first output terminal, and the critical voltage adjustment circuit to receive the first input signal, the second input signal, the first output signal, and the first feedback voltage, respectively. The second differential input stage has a plurality of transistors, each transistor having a base electrically connected to the critical voltage adjustment circuit to receive the first feedback voltage, such that the first feedback voltage is used to adjust the second critical voltage of each transistor of the second differential input stage. The second differential input stage generates a second comparison signal based on the first input signal, the second input signal, the second output signal, and each of the second critical voltages. An output stage is electrically connected to the first output terminal, the second output terminal, the first differential input stage, and the second differential input stage to receive the first comparison signal and the second comparison signal, respectively, and generate the first output signal and the second output signal based on the first comparison signal and the second comparison signal, respectively.
2. The high-speed comparator with dynamic threshold voltage adjustment function as described in claim 1, wherein the threshold voltage adjustment circuit includes a first auxiliary transistor, a second auxiliary transistor, a first load transistor, and a second load transistor. The first auxiliary transistor has a first terminal for receiving an operating voltage, a control terminal electrically connected to the first output terminal to receive the first output signal, and a second terminal for outputting the first feedback voltage. The second auxiliary transistor has a first terminal for receiving the operating voltage, a control terminal electrically connected to the first output terminal to receive the second output signal, and a second terminal for outputting the second feedback voltage. The first load transistor has a first terminal electrically connected to the second terminal of the first auxiliary transistor, a control terminal electrically connected to the second terminal of the first auxiliary transistor, and a second terminal grounded. The second load transistor has a first terminal electrically connected to the second terminal of the second auxiliary transistor, a control terminal electrically connected to the second terminal of the second auxiliary transistor, and a second terminal grounded.
3. The high-speed comparator with dynamic threshold voltage adjustment function as described in claim 1, wherein the first differential input stage includes a first transistor, a second transistor, and a third transistor; the first transistor has a first terminal electrically connected to a first common terminal, a control terminal electrically connected to the non-inverting input terminal to receive the first input signal, a second terminal electrically connected to a third common terminal, and a base terminal for receiving the second feedback voltage; the second transistor has a first terminal electrically connected to the first common terminal, a control terminal electrically connected to the inverting input terminal to receive the second input signal, a second terminal electrically connected to the third common terminal, and a base terminal for receiving the second feedback voltage; the third transistor has a first terminal electrically connected to the first common terminal, a control terminal electrically connected to the second output terminal to receive the second output signal, a second terminal electrically connected to the third common terminal, and a base terminal for receiving the second feedback voltage.
4. The high-speed comparator with dynamic threshold voltage adjustment function as described in claim 1, wherein the second differential input stage includes a fourth transistor, a fifth transistor, and a sixth transistor; the fourth transistor has a first terminal electrically connected to a second common terminal, a control terminal electrically connected to the inverting input terminal to receive the second input signal, a second terminal electrically connected to a third common terminal, and a base terminal for receiving the first feedback voltage; the fifth transistor has a first terminal electrically connected to the second common terminal, a control terminal electrically connected to the non-inverting input terminal to receive the first input signal, a second terminal electrically connected to the third common terminal, and a base terminal for receiving the first feedback voltage; the sixth transistor has a first terminal electrically connected to the second common terminal, a control terminal electrically connected to the first output terminal to receive the first output signal, a second terminal electrically connected to the third common terminal, and a base terminal for receiving the first feedback voltage.
5. The high-speed comparator with dynamic adjustment threshold voltage function as described in claim 4 further includes a seventh transistor having a first terminal electrically connected to the third common terminal, a second terminal grounded, and a control terminal for receiving a clock signal.
6. The high-speed comparator with dynamic threshold voltage adjustment function as described in claim 1, wherein the output stage includes a first output transistor, a second output transistor, a third output transistor, and a fourth output transistor; the first output transistor has a first terminal electrically connected to the first output terminal to output the first output signal, a second terminal to receive an operating voltage, and a control terminal electrically connected to the second output terminal to receive the second output signal; the second output transistor has a first terminal electrically connected to the first output terminal to output the first output signal, a second terminal electrically connected to a first common terminal, and a control terminal electrically connected to the second output terminal to receive the second output signal; the third output transistor has a first terminal electrically connected to the second output terminal, a second terminal to receive the operating voltage, and a control terminal to receive a clock signal; and the fourth output transistor is electrically connected to the first terminal of the first common terminal, a second terminal to receive the operating voltage, and a control terminal to receive the clock signal.
7. The high-speed comparator with dynamic threshold voltage adjustment function as described in claim 1, wherein the output stage further comprises a fifth output transistor, a sixth output transistor, a seventh output transistor, and an eighth output transistor. The fifth output transistor has a first terminal electrically connected to the second output terminal to output the second output signal, a second terminal to receive an operating voltage, and a control terminal electrically connected to the first output terminal to receive the first output signal. The sixth output transistor has a first terminal electrically connected to the second output terminal to output the second output signal, a second terminal electrically connected to a second common terminal, and a control terminal electrically connected to the first output terminal to receive the first output signal. The seventh output transistor has a first terminal electrically connected to the first output terminal, a second terminal to receive the operating voltage, and a control terminal to receive a clock signal. The eighth output transistor has a first terminal electrically connected to the second common terminal, a second terminal to receive the operating voltage, and a control terminal to receive the clock signal.
8. The high-speed comparator with dynamic threshold voltage adjustment function as described in claims 2 to 7, wherein each of the first terminals is a drain, each of the second terminals is a source, and each of the control terminals is a gate.