Input hold for dual power rail memories

Abstract

A data capture circuit has a first latch provided in a first voltage domain and a gating circuit also provided in the first voltage domain. The gating circuit may be configured to couple an input signal to an input of the first latch when a first clock signal is in a first signaling state and a second clock signal is in a second signaling state. The gating circuit may be disabled when the first clock signal is in a third signaling state or the second clock signal is in a fourth signaling state. The first clock signal may be configured to control timing of circuits in the first voltage domain and the second clock signal may be configured to control timing of circuits in a second voltage domain.

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