Isolation integrated circuit and common mode transient detection circuit thereof

Abstract

The present disclosure provides an isolation integrated circuit and a common mode transient detection circuit. A receiver circuit of the isolation integrated circuit includes the common mode transient (CMT) detection circuit. The receiver circuit generates an output voltage according to an input voltage at its input node. The common mode transient detection circuit includes a current generation circuit, a bias circuit, an alert circuit and a control circuit. The bias circuit is coupled to the input node and the current generation circuit, and enables the current generation circuit in response to a change of the input voltage due to a CMT event, to generate detection current. The alert circuit is coupled to the bias circuit, and generates an alert signal according to the detection current. The control circuit is coupled to the alert circuit, and selectively masks the output voltage according to a voltage level of the alert signal, to generate a receiver output signal at an output node of the receiver circuit.

Description

[Technical Field]

[0001] This disclosure relates to a common-mode transient detection circuit, and more particularly to a common-mode transient detection circuit applied to isolated integrated circuits. [Previous Technology]

[0002] In the field of isolated gate drivers, events such as common-mode transients (CMTs) frequently occur. CMT events cause voltage surges at at least one input node. These voltage surges may cause current to be generated in the isolated gate driver, damaging it, or may affect its operation, resulting in erroneous output. Therefore, it is necessary to improve isolated gate drivers to address these problems. [Summary of the Invention]

[0003] One embodiment of this disclosure is a common-mode transient detection circuit. This common-mode transient detection circuit is applicable to a receiver circuit of an isolated integrated circuit and includes a first current generation circuit, a first bias circuit, a first alarm circuit, and a control circuit. The first current generation circuit receives a reference voltage and generates one of a first transient current and a second transient current in response to a level change in a first input voltage at a first input node of the receiver circuit due to a common-mode transient event. The first bias circuit is coupled to the first input node and the first current generation circuit, receives the first input voltage, and enables the first current generation circuit in response to the level change of the first input voltage to generate one of a first detection current and a second detection current based on the first transient current and the second transient current. The first warning circuit and the first bias circuit are coupled to a first node and a second node, for receiving the first detection current and the second detection current, and for generating a first warning signal based on the first detection current and the second detection current. The control circuit is coupled to a first output node of the first warning circuit and the receiver circuit, for receiving the first warning signal and a first output voltage generated by the receiver circuit based on the first input voltage, and for selectively blocking the first output voltage based on a voltage level of the first warning signal, so as to generate a first receiver output signal at the first output node.

[0004] Another aspect of this disclosure is an isolated integrated circuit. This isolated integrated circuit includes a receiver circuit. The receiver circuit includes a signal processing circuit and a common-mode transient detection circuit. The signal processing circuit is coupled to a first input node of the receiver circuit and is used to generate a first output voltage based on a first input voltage of the first input node. The common-mode transient detection circuit is coupled to the first input node, the signal processing circuit, and a first output node of the receiver circuit, and is used to detect a common-mode transient event based on the first input voltage, and to block the first output voltage when the common-mode transient event occurs, thereby generating a first receiver output signal at the first output node. The common-mode transient detection circuit includes a first current generation circuit, a first bias circuit, a first warning circuit, and a control circuit. The first current generation circuit receives a reference voltage and, in response to a quasi-change in the first input voltage due to the common-mode transient event, generates one of a first transient current and a second transient current. The first bias circuit is coupled to the first input node and the first current generating circuit to receive the first input voltage and, in response to a level change in the first input voltage, enable the first current generating circuit to generate one of a first detection current and a second detection current based on one of a first transient current and a second transient current. The first warning circuit is coupled to the first bias circuit at a first node and a second node to receive one of the first detection current and the second detection current and to generate a first warning signal based on one of the first detection current and the second detection current. The control circuit is coupled to the first warning circuit, the signal processing circuit, and the first output node to receive the first warning signal and the first output voltage and, based on a voltage level of the first warning signal, selectively block the first output voltage to generate the first receiver output signal at the first output node.

[0005] In summary, by using a common-mode transient detection circuit, the isolated integrated circuit of this disclosure can shield the output voltage that may be affected by a common-mode transient event when such an event occurs. This achieves the technical effect of preventing the receiver circuit from outputting signals with suboptimal voltage levels and / or waveforms to the subsequent circuitry of the isolated integrated circuit. Therefore, the isolated integrated circuit of this disclosure has the advantage of high reliability.

Implementation Method

[0006] The following is a detailed description of the embodiments in conjunction with the accompanying drawings. However, the specific embodiments described are only used to explain this case and are not intended to limit this case. The description of the structural operation is not intended to limit the order of its execution. Any structure that is recombined from the components and produces a device with equivalent function is within the scope of this disclosure.

[0007] Unless otherwise specified, the terms used throughout the specification and the scope of the patent application generally have the ordinary meaning of each term in the context of the field, the content disclosed herein, and the specific content.

[0008] The term “coupled” or “connected” as used herein can refer to two or more components making direct physical or electrical contact with each other, or making indirect physical or electrical contact with each other, or two or more components operating or moving with each other.

[0009] Please refer to Figure 1, which is a circuit block diagram illustrating an isolated integrated circuit 100 according to some embodiments of the present disclosure. As shown in Figure 1, the isolated integrated circuit 100 includes a transmitter circuit 11, an isolation circuit 13, and a receiver circuit 15. Specifically, the isolated integrated circuit 100 may be implemented by an isolated gate driver.

[0010] In some embodiments, the isolation circuit 13 is coupled to a signal output terminal (not shown) of the transmitter circuit 11 and to an input node NIN of the receiver circuit 15, serving as an electrical isolation barrier between the transmitter circuit 11 and the receiver circuit 15. Specifically, the isolation circuit 13 may be implemented by means of a capacitor or other insulating element (e.g., a transformer).

[0011] Through the isolation circuit 13, the transmitter circuit 11 and the receiver circuit 15 can operate in two different voltage domains. For example, as shown in Figure 1, the transmitter circuit 11 can be biased by a power supply voltage VDD1 and a ground voltage VSS1, while the receiver circuit 15 can be biased by a power supply voltage VDD2 and a ground voltage VSS2. It should be understood that the power supply voltages VDD1 and VDD2 can be different from each other. Similarly, the ground voltages VSS1 and VSS2 can be different from each other.

[0012] In some embodiments, the transmitter circuit 11 can be implemented using various circuits such as logic circuits, oscillators, modulators, and transmitters to convert an input signal (not shown) received by the isolated integrated circuit 100 into a modulated signal (not shown). While serving as an electrical isolation barrier between the transmitter circuit 11 and the receiver circuit 15, the isolation circuit 13 also converts the modulated signal output by the transmitter circuit 11 through, for example, voltage coupling, to generate an input voltage VIN at the input node NIN. Therefore, the receiver circuit 15 can receive the input voltage VIN through the input node NIN.

[0013] Furthermore, as shown in Figure 1, the receiver circuit 15 includes a signal processing circuit 151. The signal processing circuit 151 of the receiver circuit 15 can be implemented by various circuits such as logic circuits, demodulators, and receivers. With this configuration, the receiver circuit 15 can demodulate the input voltage VIN through the signal processing circuit 151 to generate an output voltage VOUT. Thus, it can be seen that the signal processing circuit 151 generates the output voltage VOUT based on the input voltage VIN.

[0014] In some embodiments, common-mode transient (CMT) events may occur in the isolated integrated circuit 100. When a CMT event occurs, the voltage level of the input voltage VIN at the input node NIN may increase or decrease sharply. In some practical applications, the drastic change in the input voltage VIN due to the CMT event may affect the operation of the signal processing circuit 151 in generating the output voltage VOUT, resulting in the output voltage VOUT having an undesirable voltage level and / or waveform. Therefore, the isolated integrated circuit 100 of Figure 1 employs a common-mode transient detection circuit 200 to deal with these situations.

[0015] In some embodiments, the common-mode transient detection circuit 200 is configured in the receiver circuit 15 of the isolated integrated circuit 100. As shown in Figure 1, the common-mode transient detection circuit 200 is coupled to an input node NIN, a signal processing circuit 151, and an output node NOUT of the receiver circuit 15. The common-mode transient detection circuit 200 is used to detect CMT events based on the input voltage VIN and to mask the output voltage VOUT when a CMT event occurs. For example, the common-mode transient detection circuit 200 can maintain the voltage level of the output voltage VOUT at the state before the CMT event. In another example, the common-mode transient detection circuit 200 can use a blank signal (not shown) instead of the output voltage VOUT at the time of the CMT event as the output of the receiver circuit 15. In this way, receiver circuit 15 can avoid transmitting the output voltage VOUT, which has an undesirable voltage level and / or waveform due to CMT events, to the subsequent circuitry (not shown) of isolated integrated circuit 100. It should be understood that the output node NOUT of receiver circuit 15 can also be regarded as the signal output terminal of isolated integrated circuit 100 used to couple to the subsequent circuitry.

[0016] The common-mode transient detection circuit 200 will now be further described with reference to Figures 2 and 3A-3B. Figure 2 is a circuit block diagram illustrating the common-mode transient detection circuit 200 according to some embodiments of the present disclosure. In some embodiments, the common-mode transient detection circuit 200 includes a bias circuit 21, a current generation circuit 23, an alarm circuit 25, and a control circuit 27. The bias circuit 21 is coupled to the input node NIN of the receiver circuit 15. The current generation circuit 23 is coupled to the bias circuit 21 and is used to receive a reference voltage VREF. The alarm circuit 25 is coupled to the bias circuit 21, for example, coupled to the bias circuit 21 at nodes NA and NB. The control circuit 27 is coupled to the alarm circuit 25 and the output node NOUT, and is coupled to the signal processing circuit 151 to receive the output voltage VOUT.

[0017] Figures 3A and 3B are circuit diagrams illustrating a common-mode transient detection circuit 200 during a CMT event, according to some embodiments of this disclosure. In some embodiments, the bias circuit 21 includes current mirror circuits 211 and 212. The current mirror circuit 211 consists of transistors MPU1 and MPU2. A first terminal (e.g., source terminal) of transistor MPU1 is coupled to a current generating circuit 23 at a node N1, while a second terminal (e.g., drain terminal) of transistor MPU1 is coupled to an input node NIN and a control terminal (e.g., gate terminal) of transistor MPU2. A first terminal of transistor MPU2 is coupled to the current generating circuit 23 at a node N2, a second terminal of transistor MPU2 is coupled to an alarm circuit 25 at a node NA, and a control terminal of transistor MPU2 is coupled to the control terminal of transistor MPU1, the second terminal of transistor MPU1, and the input node NIN. Therefore, the current mirror circuit 211 is coupled to the input node NIN, the current generation circuit 23 is coupled to nodes N1 and N2, and the alarm circuit 25 is coupled to node NA.

[0018] As described above, the current mirror circuit 212 is composed of transistors MNL1 and MNL2. A first terminal of transistor MNL1 is coupled to the current generating circuit 23 at node N3, while a second terminal of transistor MNL1 is coupled to the input node NIN and a control terminal of transistor MNL1. A first terminal of transistor MNL2 is coupled to the current generating circuit 23 at node N4, a second terminal of transistor MNL2 is coupled to the warning circuit 25 at node NB, and a control terminal of transistor MNL2 is coupled to the control terminal of transistor MNL1, the second terminal of transistor MNL1, and the input node NIN. Therefore, the current mirror circuit 212 is coupled to the input node NIN, coupled to the current generating circuit 23 at nodes N3 and N4, and coupled to the warning circuit 25 at node NB.

[0019] In the above embodiments, the transistors MPU1 and MPU2 in the bias circuit 21 can each be implemented by a P-type metal-oxide-semiconductor transistor, and the transistors MNL1 and MNL2 in the bias circuit 21 can each be implemented by an N-type metal-oxide-semiconductor transistor. However, this disclosure is not limited thereto.

[0020] In some embodiments, the current generating circuit 23 includes a transistor pair 231 and another transistor pair 232. Transistor pair 231 includes transistors MNU1 and MNU2. A first terminal of transistor MNU1 is coupled to node N1, a second terminal of transistor MNU1 is coupled to a power supply voltage (e.g., power supply voltage VDD2 in Figure 1), and a control terminal of transistor MNU1 is coupled to a reference voltage VREF. A first terminal of transistor MNU2 is coupled to node N2, a second terminal of transistor MNU2 is coupled to the aforementioned power supply voltage, and a control terminal of transistor MNU2 is coupled to the reference voltage VREF. Thus, transistor pair 231 is coupled between the reference voltage VREF and the current mirror circuit 211, wherein transistor pair 231 and current mirror circuit 211 are coupled to nodes N1 and N2.

[0021] As described above, transistor pair 232 includes transistors MPL1 and MPL2. A first terminal of transistor MPL1 is coupled to node N3, a second terminal of transistor MPL1 is coupled to a ground voltage (e.g., ground voltage VSS2 in Figure 1), and a control terminal of transistor MPL1 is coupled to a reference voltage VREF. A first terminal of transistor MPL2 is coupled to node N4, a second terminal of transistor MPL2 is coupled to the aforementioned ground voltage, and a control terminal of transistor MPL2 is coupled to the reference voltage VREF. Therefore, transistor pair 232 is coupled between the reference voltage VREF and the current mirror circuit 212, wherein transistor pair 232 and current mirror circuit 212 are coupled to nodes N3 and N4.

[0022] In the above embodiments, the transistors MNU1 and MNU2 in the current generating circuit 23 can each be implemented by an N-type metal-oxide-semiconductor transistor, and the transistors MPL1 and MPL2 in the current generating circuit 23 can each be implemented by a P-type metal-oxide-semiconductor transistor. However, this disclosure is not limited thereto.

[0023] In some embodiments, the warning circuit 25 includes resistors RA and RB, comparator circuits 251 and 252, and a logic gate 253. Resistor RA is coupled to node NA and the aforementioned ground voltage, while resistor RB is coupled to node NB and the aforementioned power supply voltage. An input terminal of comparator circuit 251 is coupled to node NA, and an output terminal of comparator circuit 251 is coupled to a first input terminal of logic gate 253. An input terminal of comparator circuit 252 is coupled to node NB, and an output terminal of comparator circuit 252 is coupled to a second input terminal of logic gate 253. The output terminal of logic gate 253 is coupled to control circuit 27.

[0024] In the above embodiments, the comparator circuit 251 can be implemented by a non-inverting Schmitt trigger, the comparator circuit 252 can be implemented by an inverting Schmitt trigger, and the logic gate 253 can be implemented by an inverse OR (NOR) gate. However, this disclosure is not limited thereto.

[0025] In some embodiments, the control circuit 27 includes a latch circuit 271. A data input terminal D of the latch circuit 271 is coupled to the signal processing circuit 151 in Figure 1 to receive the output voltage VOUT. A gate terminal of the latch circuit 271 (indicated by the symbol ">" in Figures 3A and 3B) is coupled to the output terminal of the logic gate 253. A data output terminal Q of the latch circuit 271 is coupled to the output node NOUT. Specifically, the latch circuit 271 can be implemented by circuits such as an SR latch circuit, a gated D latch circuit, etc.

[0026] In the embodiment shown in Figure 3A, it is assumed that the voltage level of the input voltage VIN at the input node NIN drops sharply due to the occurrence of a CMT event. In this case, both transistors MPU1 and MPU2 switch to the on state, while transistors MNL1 and MNL2 remain in the off state. Furthermore, transistor MPU1 biases node N1 according to the voltage level of the input voltage VIN and the gate-source voltage of transistor MPU1, causing transistor MNU1 to switch to the on state; simultaneously, transistor MPU2 biases node N2 according to the voltage level of the input voltage VIN and the gate-source voltage of transistor MPU2, causing transistor MNU2 to switch to the on state. Based on the conduction of transistors MPU1 and MNU1, transistor MNU1 generates a transient current I1, which flows sequentially through transistor MNU1, node N1, transistor MPU1, and input node NIN. In other words, transistor 231 is biased by current mirror circuit 211, causing transient current I1 to be generated. Then, current mirror circuit 211 replicates transient current I1 to generate a detection current IA that flows sequentially through transistor MNU2, node N2, transistor MPU2, and node NA.

[0027] As described above, the detected current IA flows from node NA into resistor RA, causing an increase in the voltage at one input terminal of comparator circuit 251 (not shown in the figure). When the voltage at the input terminal of comparator circuit 251 increases to a value greater than an upper limit voltage threshold (not shown in the figure) of comparator circuit 251, comparator circuit 251 outputs a comparator signal SC1 that enables the level (e.g., logic "1"). Logic gate 253 performs an inverse OR operation on the comparator signal SC1 that enables the level and outputs a warning signal SOC that disables the level (e.g., logic "0"). Then, since the warning signal SOC that disables the level is input to the gate terminal of latch circuit 271, latch circuit 271 keeps the voltage at data output terminal Q unchanged. For example, if the latch circuit 271 outputs an enable voltage VOUT as the receiver output signal SOUT just before the CMT event occurs, then the receiver output signal SOUT output by the latch circuit 271 at the time the CMT event occurs will still be at the enable level (even if the output voltage VOUT has switched to the disable level at this time). It should be understood that the input voltage of the comparator circuit 251 can also be regarded as the voltage at node NA.

[0028] In the embodiment of Figure 3B, it is assumed that the voltage level of the input voltage VIN at the input node NIN increases sharply due to the occurrence of the CMT event. In this case, transistors MNL1 and MNL2 both switch to the on state, while transistors MPU1 and MPU2 remain in the off state. Furthermore, transistor MNL1 biases node N3 according to the voltage level of the input voltage VIN and the gate-source voltage of transistor MNL1, so that transistor MPL1 switches to the on state; at the same time, transistor MNL2 biases node N4 according to the voltage level of the input voltage VIN and the gate-source voltage of transistor MNL2, so that transistor MPL2 switches to the on state. Based on the conduction of transistors MNL1 and MPL1, transistor MPL1 generates a transient current I2, which flows sequentially through the input node NIN, transistor MNL1, node N3, and transistor MPL1. In other words, transistor 232 is biased by current mirror circuit 212, causing transient current I2 to be generated. Then, current mirror circuit 212 replicates transient current I2 to generate a detection current IB that flows sequentially through node NB, transistor MNL2, node N4 and transistor MPL2.

[0029] As described above, the detection current IB flows out of resistor RB and into node NB, causing a decrease in the voltage at one input terminal of comparator circuit 252 (not shown in the figure). When the voltage at the input terminal of comparator circuit 252 decreases to less than a lower limit voltage threshold (not shown in the figure) of comparator circuit 252, comparator circuit 252 outputs a comparator signal SC2 to enable the level. Logic gate 253 performs an inverse OR operation based on the comparator signal SC2 to output a warning signal SOC to disable the level. Then, since the warning signal SOC to disable the level is input to the gate terminal of latch circuit 271, latch circuit 271 keeps the voltage at data output terminal Q unchanged, similar to the description of latch circuit 271 in the embodiment of Figure 3A. It should be understood that the voltage at the input terminal of comparator circuit 252 can also be considered as the voltage at node NB.

[0030] In some embodiments, no CMT event occurs in the isolated integrated circuit 100. The common-mode transient detection circuit 200 of Figures 3A and 3B ensures that transistors MNU1, MNU2, MPL1, and MPL2 are all in the off state through the configuration of the reference voltage VREF and the bias circuit 21, that is, the current generation circuit 23 is disabled. This further ensures that the bias circuit 21 will not output the detection current IA (or detection current IB). Therefore, the input voltage of the comparator circuit 251 (which is equivalent to the ground voltage VSS2) will be less than the lower limit voltage threshold of the comparator circuit 251 (not shown in the figure), causing the comparator circuit 251 to output a comparator signal SC1 at the disabled level. It should be understood that the upper limit voltage threshold of the comparator circuit 251 is greater than the lower limit voltage threshold of the comparator circuit 251. Furthermore, the input voltage of comparator circuit 252 (which is equivalent to the power supply voltage VDD2) will be greater than an upper voltage threshold (not shown in the figure) of comparator circuit 252, causing comparator circuit 252 to output a comparison signal SC2 indicating the disable level. It should be understood that the upper voltage threshold of comparator circuit 252 is greater than the lower voltage threshold of comparator circuit 252. Next, logic gate 253 performs an inverse OR operation based on the comparison signals SC1 and SC2 indicating the disable level to output a warning signal SOC indicating the enable level.

[0031] As described above, since the alarm signal SOC of the enable level is input to the gate terminal of the latch circuit 271, the latch circuit 271 directly outputs the output voltage VOUT generated by the signal processing circuit 151 from the data output terminal Q. In other words, when no CMT event occurs in the isolated integrated circuit 100, the control circuit 27 does not perform any processing on the output voltage VOUT (e.g., masking), and directly transmits the output voltage VOUT to the output node NOUT as the output of the receiver circuit 15, i.e., as the receiver output signal SOUT. In short, when no CMT event occurs in the isolated integrated circuit 100, the common-mode transient detection circuit 200 does not change or affect the normal operation of the receiver circuit 15 in the isolated integrated circuit 100 (i.e., the operation of the signal processing circuit 151).

[0032] As can be seen from the description of the above embodiments, in some embodiments, the bias circuit 21 is used to enable the current generating circuit 23 in response to the level change of the input voltage VIN due to the CMT event, that is, to switch the transistors MNU1 and MNU2 (or transistors MPL1 and MPL2) to the on state, so as to generate a transient current I1 (or transient current I2). The current generating circuit 23 is used to generate a transient current I1 (or transient current I2) in response to the level change of the input voltage VIN due to the CMT event, so as to generate a detection current IA (or detection current IB) in the bias circuit 21. The warning circuit 25 is used to generate a warning signal SOC based on the detection current IA (or detection current IB). The control circuit 27 is used to selectively block the output voltage VOUT based on the voltage level (i.e., the disable level or the enable level) of the warning signal SOC, so as to generate a receiver output signal SOUT at the output node NOUT.

[0033] As further explained above, when the warning signal SOC is at the enable level (indicating that no CMT event has occurred in the isolated integrated circuit 100), the voltage level of the receiver output signal SOUT and the voltage level of the output voltage VOUT may be the same in real time. When the warning signal SOC is at the disable level (indicating that a CMT event has occurred in the isolated integrated circuit 100), the voltage level of the receiver output signal SOUT and the voltage level of the output voltage VOUT may not be the same in real time.

[0034] In the above embodiments, as shown in Figures 3A and 3B, the warning circuit 25 performs current-to-voltage conversion on the detected current IA (or detected current IB) through resistor RA (or resistor RB) to generate a warning signal SOC. It should be understood that the warning circuit 25 of this disclosure is not limited to the circuit architecture shown in the embodiments of Figures 3A and 3B. For example, in some embodiments, resistors RA and RB are omitted, and the comparison circuits 251 and 252 in the warning circuit 25 can each be implemented by a current comparator. With this configuration, the warning circuit 25 can compare the detected current IA with a current threshold (not shown) through comparison circuit 251 to generate a comparison signal SC1, and can compare the detected current IB with another current threshold (not shown) through comparison circuit 252 to generate a comparison signal SC2. Furthermore, the warning circuit 25 can output the warning signal SOC based on the comparison signals SC1 and SC2 through logic gate 253.

[0035] Furthermore, in the above embodiments, as shown in Figure 1, the receiver circuit 15 is a single-ended input architecture. Also, the common-mode transient detection circuit 200 in Figure 2 is applicable to the single-ended input architecture receiver circuit 15. It should be understood that the receiver circuit in the isolated integrated circuit 100 of this disclosure is not limited to the single-ended input architecture shown in the embodiments of Figures 1 and 2.

[0036] Please refer to Figure 4, which is a circuit block diagram illustrating a common-mode transient detection circuit 400 of a receiver circuit 45 suitable for a differential input architecture, according to some embodiments of the present disclosure. In some embodiments, a signal processing circuit 451 of the receiver circuit 45 is coupled to an input node NINP and another input node NINN, and generates output voltages VOUTP and VOUTN based on an input voltage VINP at input node NINP and another input voltage VINN at input node NINN, wherein the input voltages VINP and VINN form a differential input signal, and the output voltages VOUTP and VOUTN form a differential output signal. Specifically, the signal processing circuit 451 of the receiver circuit 45 can be implemented by various circuits such as logic circuits, demodulators, and receivers.

[0037] In the embodiment of Figure 4, the common-mode transient detection circuit 400 is coupled to the input node NINP, the input node NINN, the signal processing circuit 451, and the output nodes NOUTP and NOUTN of the receiver circuit 45. As shown in Figures 2 and 4, compared to the circuit configuration of the common-mode transient detection circuit 200 in Figure 2, the common-mode transient detection circuit 400 in Figure 4 also includes another bias circuit 31, another current generation circuit 33, and another warning circuit 35. Furthermore, a control circuit 37 in the common-mode transient detection circuit 400 is slightly different from the control circuit 27 in the common-mode transient detection circuit 200.

[0038] Bias circuit 21 is coupled to input node NINP. Current generation circuit 23 is coupled to bias circuit 21 and receives reference voltage VREF. Alarm circuit 25 is coupled to bias circuit 21 at nodes NA and NB. Bias circuit 31 is coupled to input node NINN. Current generation circuit 33 is coupled to bias circuit 31 and receives reference voltage VREF. Alarm circuit 35 is coupled to bias circuit 31 at nodes NC and ND. Furthermore, control circuit 37 is coupled to alarm circuit 25, alarm circuit 35, and output nodes NOUTP and NOUTN, and receives output voltages VOUTP and VOUTN generated by signal processing circuit 451.

[0039] The circuit architecture of bias circuits 21 and 31 in Figure 4 is similar to that of bias circuit 21 in Figures 3A and 3B. The circuit architecture of current generating circuits 23 and 33 in Figure 4 is similar to that of current generating circuit 23 in Figures 3A and 3B. Furthermore, the circuit architecture of warning circuits 25 and 35 in Figure 4 is similar to that of warning circuit 25 in Figures 3A and 3B. The operation of bias circuits 21 and 31, current generating circuits 23 and 33, and warning circuits 25 and 35 in Figure 4 can be found in the relevant descriptions in Figures 3A and 3B.

[0040] As described above, referring to Figure 5, the control circuit 37 may include an AND gate 371 and latching circuits 373 and 375. The two input terminals of the AND gate 371 may be coupled to the output terminals of the alarm circuit 25 and the alarm circuit 35, respectively, while one output terminal of the AND gate 371 may be coupled to the gate control terminals of the latching circuits 373 and 375. The data input terminal D of the latching circuit 373 receives the output voltage VOUTP generated by the signal processing circuit 451, and the data output terminal Q of the latching circuit 373 is coupled to the output node NOUTP. The data input terminal D of the latching circuit 375 receives the output voltage VOUTN generated by the signal processing circuit 451, and the data output terminal Q of the latching circuit 375 is coupled to the output node NOUTN.

[0041] Similar to the description in the embodiments of Figures 2, 3A, and 3B, the bias circuit 21, in response to a level change in the input voltage VINP due to a CMT event, enables the current generating circuit 23 to generate a detection current IA flowing into node NA (or a detection current IB flowing out of node NB) based on the transient current I1 (or transient current I2) generated by the current generating circuit 23. The warning circuit 25 generates a warning signal SOCP based on the detection current IA flowing into node NA (or the detection current IB flowing out of node NB). The bias circuit 31, in response to a level change in the input voltage VINN due to a CMT event, enables the current generating circuit 33 to generate a detection current flowing into node NC (or another detection current flowing out of node ND) based on a transient current from the current generating circuit 33 to the bias circuit 31 (or another transient current from the bias circuit 31 to the current generating circuit 33). The warning circuit 35 generates another warning signal SOCN based on the detection current flowing into node NC (or the detection current flowing out of node ND).

[0042] Through the circuit configuration of the control circuit 37 described above, when at least one of the input voltages VINP and VINN changes drastically due to a CMT event, gate 371 can perform an AND operation based on at least one of the warning signals SOCP and SOCN of the disable level and output a logic signal (not shown in the figure) of the disable level to the gate control terminals of latching circuits 373 and 375. Accordingly, latching circuits 373 and 375 of control circuit 37 keep the voltage of the data output terminal Q unchanged, that is, keep the voltage levels of the receiver output signals SOUTP and SOUTN generated at the output nodes NOUTP and NOUTN respectively.

[0043] Furthermore, in the absence of a CMT event, the alarm circuit 25 outputs an alarm signal SOCP for the enable level, and the alarm circuit 35 outputs an alarm signal SOCN for the enable level. The gate 371 can perform AND operations based on the alarm signals SOCP and SOCN for the enable level and output the aforementioned logic signal for the enable level to the gate terminals of the latch circuits 373 and 375. Accordingly, the latch circuits 373 and 375 of the control circuit 37 directly output the output voltages VOUTP and VOUTN generated by the signal processing circuit 451 from the data output terminal Q, respectively, as receiver output signals SOUTP and SOUTN.

[0044] As explained above, the control circuit 37 selectively masks the output voltages VOUTP and VOUTN based on the voltage levels of the warning signals SOCP and SOCN, thereby generating receiver output signals SOUTP and SOUTN at the output nodes NOUTP and NOUTN. Further explanation: when both warning signals SOCP and SOCN are enabled (indicating that a CMT event has not occurred), the voltage levels of the receiver output signals SOUTP and SOUTN may be the same as the voltage levels of the output voltages VOUTP and VOUTN in real time. When at least one of the warning signals SOCP and SOCN is disabled (indicating that a CMT event has occurred), the voltage levels of the receiver output signals SOUTP and SOUTN may not be the same as the voltage levels of the output voltages VOUTP and VOUTN in real time.

[0045] It should be understood that the common-mode transient detection circuit 400 for the receiver circuit 45 of the differential input architecture is not limited to the circuit configuration shown in the embodiment of Figure 4. For example, referring to Figure 6, in some embodiments, the common-mode transient detection circuit 600 is adapted for the receiver circuit 45 of the differential input architecture. The common-mode transient detection circuit 600 of Figure 6 includes bias circuits 21 and 31, current generation circuits 23 and 33, an alarm circuit 25, and a control circuit 47. That is, the alarm circuit 35 in Figure 4 can be omitted, and the bias circuit 31 can be coupled to the alarm circuit 25 at nodes NA and NB. Referring to Figure 7, the control circuit 47 may include latching circuits 471 and 473. The gate terminals of latching circuits 471 and 473 are both coupled to the output terminal of the alarm circuit 25. The data input terminal D of latch circuit 471 receives the output voltage VOUTP generated by signal processing circuit 451, while the data output terminal Q of latch circuit 471 is coupled to output node NOUTP. The data input terminal D of latch circuit 473 receives the output voltage VOUTN generated by signal processing circuit 451, while the data output terminal Q of latch circuit 473 is coupled to output node NOUTN. With this configuration, when at least one of bias circuits 21 and 31 generates at least one detection current due to a CMT event (e.g., detection current IA, detection current IB, a detection current generated by bias circuit 31 and flowing into node NA from bias circuit 31, another detection current generated by bias circuit 31 and flowing into bias circuit 31 from node NB, etc.), the warning circuit 25 can generate a warning signal SOCP based on at least one detection current. The control circuit 47 receives the warning signal SOCP and can selectively block the output voltages VOUTP and VOUTN according to the voltage level of the warning signal SOCP, so as to generate receiver output signals SOUTP and SOUTN at the output nodes NOUTP and NOUTN.

[0046] As can be seen from the above-described embodiments of the present disclosure, by means of the common-mode transient detection circuit 200 (or common-mode transient detection circuit 400, common-mode transient detection circuit 600, etc.), the isolated integrated circuit 100 of the present disclosure can shield the output voltage VOUT (or output voltages VOUTP and VOUTN) that may be affected by the common-mode transient event when it occurs, thereby achieving the technical effect of preventing the receiver circuit 15 (or receiver circuit 45) from outputting an output voltage VOUT with an undesirable voltage level and / or waveform to the subsequent circuits of the isolated integrated circuit 100. Therefore, the isolated integrated circuit 100 of the present disclosure has the advantage of high reliability.

[0047] Although the present disclosure has been disclosed above with reference to embodiments, it is not intended to limit the present disclosure. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0048] Figure 1 is a circuit block diagram of an isolated integrated circuit according to some embodiments of the present disclosure. Figure 2 is a circuit block diagram of a common-mode transient detection circuit according to some embodiments of the present disclosure. Figure 3A is a circuit schematic diagram of a common-mode transient detection circuit according to some embodiments of the present disclosure. Figure 3B is a circuit schematic diagram of a common-mode transient detection circuit according to some embodiments of the present disclosure. Figure 4 is a circuit block diagram of another common-mode transient detection circuit according to some embodiments of the present disclosure. Figure 5 is a circuit schematic diagram of the control circuit in Figure 4 according to some embodiments of the present disclosure. Figure 6 is a circuit block diagram of yet another common-mode transient detection circuit according to some embodiments of the present disclosure. Figure 7 is a circuit schematic diagram of the control circuit in Figure 6 according to some embodiments of the present disclosure. [Biomaterial Storage]

[0050] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A common-mode transient detection circuit, applicable to a receiver circuit of an isolated integrated circuit, comprising: a first current generating circuit for receiving a reference voltage and for generating one of a first transient current and a second transient current in response to a level change of a first input voltage at a first input node of the receiver circuit due to a common-mode transient event; a first bias circuit coupled to the first input node and the first current generating circuit for receiving the first input voltage and for biasing the first current generating circuit in response to the level change of the first input voltage such that the first current generating circuit generates one of the first transient current and the second transient current, and further for generating one of a first detection current and a second detection current based on the first transient current and the second transient current; A first warning circuit, coupled to the first bias circuit and connected to a first node and a second node, is used to receive one of the first detection current and the second detection current, and to generate a first warning signal based on the one of the first detection current and the second detection current; and a control circuit, coupled to the first warning circuit and a first output node of the receiver circuit, is used to receive the first warning signal and a first output voltage generated by the receiver circuit based on the first input voltage, and to selectively block the first output voltage based on a voltage level of the first warning signal, so as to generate a first receiver output signal at the first output node.

2. The common-mode transient detection circuit as described in claim 1, wherein the first bias circuit comprises: a first current mirror circuit, comprising a first transistor and a second transistor, wherein a first terminal of the first transistor and a first terminal of the second transistor are respectively coupled to a first current generating circuit at a third node and a fourth node; a second terminal and a control terminal of the first transistor and a control terminal of the second transistor are both coupled to the first input node; a second terminal of the second transistor is coupled to the first warning circuit at the first node; and the first current mirror circuit is used to replicate the first transient current to generate the first detection current sequentially flowing through the fourth node and the first node, wherein the first transient current sequentially flows through the third node and the first input node; A second current mirror circuit includes a third transistor and a fourth transistor, wherein a first terminal of the third transistor and a first terminal of the fourth transistor are respectively coupled to a fifth node and a sixth node of the first current generating circuit. A second terminal and a control terminal of the third transistor and a control terminal of the fourth transistor are both coupled to the first input node. A second terminal of the fourth transistor is coupled to the first warning circuit and the second node. The second current mirror circuit is used to replicate the second transient current to generate the second detection current that flows sequentially through the second node and the sixth node, wherein the second transient current flows sequentially through the first input node and the fifth node.

3. The common-mode transient detection circuit as described in claim 2, wherein the first current generating circuit comprises: a first transistor pair coupled to the reference voltage, coupled between a power supply voltage and the first current mirror circuit, coupled to the first current mirror circuit at the third node and the fourth node, and biased by the first current mirror circuit to generate the first transient current; and a second transistor pair coupled to the reference voltage, coupled between a ground voltage and the second current mirror circuit, coupled to the second current mirror circuit at the fifth node and the sixth node, and biased by the second current mirror circuit to generate the second transient current; wherein one of the first transistor pair and the second transistor pair is biased by a corresponding one of the first current mirror circuit and the second current mirror circuit in response to the level change of the first input voltage.

4. The common-mode transient detection circuit as described in claim 2, wherein the first warning circuit comprises: a first comparison circuit coupled to the first current mirror circuit at the first node, and used to compare the first detected current with a first current threshold to generate a first comparison signal; a second comparison circuit coupled to the second current mirror circuit at the second node, and used to compare the second detected current with a second current threshold to generate a second comparison signal; and a logic gate coupled to the first comparison circuit and the second comparison circuit, and used to output the first warning signal based on the first comparison signal and the second comparison signal, wherein when at least one of the first comparison signal and the second comparison signal is a matching level, the first warning signal is a disabled level, and wherein the control circuit, based on the first warning signal at the disabled level, blocks the first output voltage so that a voltage level of the first receiver output signal is not the same as a voltage level of the first output voltage in real time.

5. The common-mode transient detection circuit as described in claim 2, wherein the first warning circuit comprises: a first resistor coupled to the first current mirror circuit at the first node; a second resistor coupled to the second current mirror circuit at the second node; and a first comparison circuit coupled to the first current mirror circuit at the first node, for comparing a voltage at the first node with a first voltage threshold to generate a first comparison signal; A second comparison circuit, coupled to the second current mirror circuit at the second node, is used to compare a voltage at the second node with a second voltage threshold to generate a second comparison signal; and a logic gate, coupled to the first comparison circuit and the second comparison circuit, is used to output a first warning signal based on the first comparison signal and the second comparison signal, wherein the first warning signal is a disabled level when at least one of the first comparison signal and the second comparison signal is a consistent level, and wherein the control circuit blocks the first output voltage based on the first warning signal at the disabled level, so that a voltage level of the first receiver output signal is not the same as a voltage level of the first output voltage in real time.

6. The common-mode transient detection circuit as described in claim 1, wherein the control circuit comprises: a latching circuit, wherein a gate terminal of the latching circuit is coupled to the first warning circuit to receive the first warning signal, a data input terminal of the latching circuit receives the first output voltage, and a data output terminal of the latching circuit is coupled to the first output node to output the first receiver output signal, wherein when the first warning signal at a disabled level is input to the gate terminal of the latching circuit, the latching circuit keeps a voltage at the data output terminal unchanged, such that a voltage level of the first receiver output signal is not immediately the same as a voltage level of the first output voltage, and wherein when the first warning signal at a disabled level is input to the gate terminal of the latching circuit, the latching circuit directly outputs the first output voltage from the data output terminal, such that the voltage level of the first receiver output signal is immediately the same as the voltage level of the first output voltage.

7. The common-mode transient detection circuit as claimed in claim 1, further comprising: a second current generating circuit for receiving the reference voltage and for generating one of a third transient current and a fourth transient current in response to a level change of a second input voltage at a second input node of the receiver circuit due to the common-mode transient event; and a second bias circuit coupled to the second input node and the second current generating circuit for receiving the second input voltage and for enabling the second current generating circuit in response to the level change of the second input voltage to generate one of a third detection current and a fourth detection current.

8. The common-mode transient detection circuit as described in claim 7, wherein the second bias circuit is coupled to the first warning circuit at the first node and the second node; wherein the first warning circuit is configured to generate the first warning signal based on at least one of the first detection current, the second detection current, the third detection current, and the fourth detection current, wherein the first detection current flows from the first bias circuit into the first node, the second detection current flows from the second node into the first bias circuit, the third detection current flows from the second bias circuit into the first node, and the fourth detection current flows from the second node into the second bias circuit.

9. The common-mode transient detection circuit as described in claim 7, further comprising: a second warning circuit coupled to the second bias circuit at a third node and a fourth node, for receiving one of the third detection current and the fourth detection current, and for generating a second warning signal based on the third detection current and the fourth detection current; wherein the control circuit is coupled to a second output node of the second warning circuit and the receiver circuit, for receiving the second warning signal and a second output voltage generated by the receiver circuit based on the second input voltage, and for selectively blocking the first output voltage and the second output voltage based on the voltage level of the first warning signal and the voltage level of the second warning signal, so as to generate the first receiver output signal and the second receiver output signal at the first output node and the second output node, respectively.

10. An isolated integrated circuit, comprising: a receiver circuit, comprising: a signal processing circuit coupled to a first input node of the receiver circuit, and configured to generate a first output voltage based on a first input voltage of the first input node; A common-mode transient detection circuit is coupled to a first output node of the first input node, the signal processing circuit, and the receiver circuit. This circuit detects a common-mode transient event based on the first input voltage and blocks the first output voltage when the common-mode transient event occurs, thereby generating a first receiver output signal at the first output node. The common-mode transient detection circuit includes: a first current generation circuit for receiving a reference voltage and generating one of a first transient current and a second transient current in response to a level change in the first input voltage due to the common-mode transient event; and a first bias circuit coupled to the first input node and the first current generation circuit for receiving the first input voltage and enabling the first current generation circuit in response to the level change of the first input voltage, generating one of a first detection current and a second detection current based on the first transient current and the second transient current. The first current generation circuit is coupled to the first input node through the first bias circuit. A first warning circuit, coupled to the first bias circuit to a first node and a second node, is used to receive one of the first detection current and the second detection current, and to generate a first warning signal based on the one of the first detection current and the second detection current. A control circuit, coupled to the first warning circuit, the signal processing circuit and the first output node, is used to receive the first warning signal and the first output voltage, and to selectively block the first output voltage according to a voltage level of the first warning signal, so as to generate the first receiver output signal at the first output node.

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