Isolation gate driver

Abstract

The present disclosure provides an isolation integrated circuit and a compensation circuit thereof. The isolation integrated circuit includes an isolation capacitor and a signal processing circuit. The compensation circuit is coupled to the isolation capacitor and the signal processing circuit. The compensation circuit includes a compensation resistor and a compensation capacitor. The compensation resistor is coupled to the isolation capacitor at a first node, and is coupled to a ground terminal. The compensation capacitor is coupled to the isolation capacitor and the compensation resistor at the first node, and is coupled to the signal processing circuit, wherein the compensation capacitor and the isolation capacitor share a metal plate.

Description

Technical Field

[0001] This disclosure relates to a compensation circuit, and more particularly to a compensation circuit applied to isolated integrated circuits. Prior Technology

[0002] In the field of isolated gate drivers, events such as common-mode transients (CMTs) frequently occur. Some related technologies incorporate additional circuitry within the isolated gate driver to handle the sharp voltage spikes or drops caused by CMTs. However, the addition of this additional circuitry leads to excessive parasitic capacitance within the isolated gate driver, affecting the signal transmitted by the driver. Therefore, it is necessary to propose new methods to address these issues. Summary of the Invention

[0003] One embodiment of this disclosure is a compensation circuit. This compensation circuit is coupled to an isolation capacitor and a signal processing circuit. The compensation circuit includes a compensation resistor and a compensation capacitor. The compensation resistor and the isolation capacitor are coupled to a first node and to a ground terminal. The compensation capacitor, the isolation capacitor, and the compensation resistor are coupled to the first node and to the signal processing circuit, wherein the compensation capacitor and the isolation capacitor share a metal plate.

[0004] Another embodiment of this disclosure is a compensation circuit. This compensation circuit is coupled to an isolation capacitor and a signal processing circuit. The compensation circuit includes a compensation capacitor and a compensation resistor. The compensation capacitor includes a first metal plate and a second metal plate, wherein the first metal plate is coupled to the signal processing circuit, and the compensation capacitor and the isolation capacitor share the second metal plate. The compensation resistor is coupled to the second metal plate at a first node and to a ground terminal.

[0005] Another embodiment of this disclosure is an isolated integrated circuit. This isolated integrated circuit includes a signal processing circuit, an isolation capacitor, and a compensation circuit. The signal processing circuit is coupled to a first input / output terminal. The isolation capacitor includes a first metal plate and a second metal plate, wherein the first metal plate is coupled to a second input / output terminal. The compensation circuit is coupled to the isolation capacitor and the signal processing circuit, and includes a compensation capacitor and a compensation resistor. The compensation capacitor includes the second metal plate and a third metal plate, wherein the third metal plate is coupled to the signal processing circuit. The compensation resistor is coupled to the second metal plate at a first node and to a ground terminal.

[0006] In summary, by incorporating a compensation circuit between the isolation capacitor and the signal processing circuit, the isolated integrated circuit disclosed herein can effectively compensate for the current of the first node during common-mode transient events. Furthermore, compared to some related technologies that do not allow a capacitor used as an electrical isolation barrier to share a metal plate with another capacitor in the circuit providing current compensation, the isolated integrated circuit disclosed herein offers advantages such as lower parasitic capacitance, higher reliability, and more efficient transmission. Simple Explanation of the Diagram

[0007] Figure 1 is a block diagram of a compensation circuit illustrated according to some embodiments of the present disclosure. Figure 2 is a circuit block diagram illustrating an application of a compensation circuit in an isolated integrated circuit according to some embodiments of the present disclosure. Figure 3 is a circuit block diagram illustrating another application of the compensation circuit in an isolated integrated circuit, based on some embodiments of the present disclosure. Figure 4 is a circuit block diagram illustrating another application of the compensation circuit in an isolated integrated circuit, based on some embodiments of the present disclosure. Figure 5 is a structural schematic diagram of a compensation capacitor and an isolation capacitor according to some embodiments of the present disclosure. Implementation

[0008] The following detailed description uses examples and accompanying drawings. However, the specific embodiments described are only for explaining this case and are not intended to limit this case. The description of the structural operation is not intended to limit the order of its execution. Any structure that is recombined from the components and produces a device with equivalent function is within the scope of this disclosure.

[0009] Unless otherwise specified, the terms used throughout the specification and the scope of the patent application generally have their ordinary meaning in the context of the field, the content disclosed herein, and the specific content.

[0010] The terms "coupled" or "connected" as used in this article can refer to two or more components making direct physical or electrical contact with each other, or making indirect physical or electrical contact with each other, or to two or more components operating or moving together.

[0011] Please refer to Figure 1, which is a block diagram illustrating a compensation circuit 100 according to some embodiments of the present disclosure. As shown in Figure 1, the compensation circuit 100 is coupled to an isolation capacitor 11 and a signal processing circuit 13.

[0012] In some embodiments, the voltage level of a first terminal T1 of the isolation capacitor 11 may need to be increased or decreased due to some non-ideal factors (e.g., a sharp increase or decrease in the voltage level at the ground terminal). Changes in the voltage level of the first terminal T1 may not respond promptly to changes in the voltage level at the ground terminal, thus creating an unexpected voltage difference between the first terminal T1 and the ground terminal. This voltage difference may affect a second terminal T2 of the isolation capacitor 11 (through coupling) and / or the signal processing circuit 13. For example, to eliminate the voltage difference, a charging current or a discharging current may be generated between the first terminal T1 and the ground terminal, and the power supply to the signal processing circuit 13 coupled to the ground terminal may be affected by the charging current or discharging current. In the embodiment of Figure 1, the compensation circuit 100 can perform current compensation on the first terminal T1 of the isolation capacitor 11 when the voltage level at the ground terminal increases or decreases sharply.

[0013] Please refer to Figure 2, which is a circuit block diagram illustrating an isolated integrated circuit 400 according to some embodiments of this disclosure. In some embodiments, the isolated integrated circuit 400 includes a transmitter circuit 20 and a receiver circuit 30. Specifically, the isolated integrated circuit 400 may be implemented by an isolated gate driver.

[0014] In some embodiments, an electrical isolation barrier is provided between the transmitter circuit 20 and the receiver circuit 30. Therefore, the transmitter circuit 20 and the receiver circuit 30 can operate in two different voltage domains. For example, as shown in Figure 2, the transmitter circuit 20 can be biased by a power supply terminal VDD1 and a ground terminal VSS1, while the receiver circuit 30 can be biased by a power supply terminal VDD2 and a ground terminal VSS2. Furthermore, the voltages at power supply terminals VDD1 and VDD2 can be different from each other, and the voltages at ground terminals VSS1 and VSS2 can also be different from each other.

[0015] In some embodiments, the compensation circuit 100 and the isolation capacitor 11 of Figure 1 may be disposed in the transmitter circuit 20 or the receiver circuit 30, or may be disposed in both the transmitter circuit 20 and the receiver circuit 30, as will be described in detail in the following paragraphs with reference to Figures 2 to 4.

[0016] In the embodiment shown in Figure 2, the transmitter circuit 20 may include a signal processing circuit 23, a compensation circuit 200, and an isolation capacitor 21. The signal processing circuit 23 may be an example of the signal processing circuit 13 in Figure 1, the compensation circuit 200 may be an example of the compensation circuit 100 in Figure 1, and the isolation capacitor 21 may be an example of the isolation capacitor 11 in Figure 1. Specifically, the compensation circuit 200 includes a compensation resistor 202 and a compensation capacitor 204. The compensation resistor 202 may be coupled to a node NA and a ground terminal VSS1, along with the first terminal T1 of the isolation capacitor 21 and the compensation resistor 202. The compensation capacitor 204 is coupled to node NA and the signal processing circuit 23, along with the first terminal T1 of the isolation capacitor 21 and the compensation resistor 202. Furthermore, the second terminal T2 of the isolation capacitor 21 may be coupled to an input / output terminal IO1 of the transmitter circuit 20, while the signal processing circuit 23 may be coupled to another input / output terminal IO2 of the transmitter circuit 20.

[0017] In some embodiments, the signal processing circuit 23 of the transmitter circuit 20 can be implemented using various circuits such as logic circuits, oscillators, modulators, and transmitters. With this configuration, the transmitter circuit 20 can modulate a signal (not shown) received from the input / output terminal IO2 via the signal processing circuit 23, and transmit the modulated signal from the input / output terminal IO1 to the receiver circuit 30 via the compensation circuit 200 and the isolation capacitor 21. Furthermore, the isolation capacitor 21 of the transmitter circuit 20 can serve as the aforementioned electrical isolation barrier.

[0018] In some embodiments, a common-mode transient (CMT) event may occur in the isolated integrated circuit 400. When a CMT event occurs, the voltage level at ground VSS1 may surge to a positive voltage VCMT (denoted as +VCMT in Figure 2, where the voltage VCMT can range from several volts (V) to several kilovolts). At this time, the voltage difference between the voltage level at ground VSS1 and the voltage level of a voltage signal VA at node NA (i.e., the voltage difference between ground VSS1 and node NA) may be greater than expected, thus causing a charging current I20 from ground VSS1 to the first terminal T1 (or to node NA). The charging current I20 is used to change the voltage level of the voltage signal VA toward the positive voltage VCMT. It should be understood that the charging current I20 may flow from ground VSS1 to the first terminal T1 through some circuitry (e.g., signal processing circuitry 23) in the transmitter circuitry 20 coupled to ground VSS1, thus affecting some circuitry coupled to ground VSS1.

[0019] As described above, the compensation circuit 200 also generates a compensation current ICP1 through the compensation resistor 202 based on the voltage difference between the voltage level of the voltage signal VA and the voltage level of the ground terminal VSS1, to provide additional compensation for the charging current I20. As the voltage level of the voltage signal VA gradually approaches the positive voltage VCMT, the compensation current ICP1 eventually approaches zero. As shown in Figure 2, the compensation current ICP1 flows out from the ground terminal VSS1, through the compensation resistor 202, and into node NA. By allowing the compensation current ICP1 to flow into node NA, the current flowing through some circuits in the transmitter circuit 20 (e.g., signal processing circuit 23) is reduced, thereby mitigating the impact on some circuits in the transmitter circuit 20. In short, when the voltage level of the ground terminal VSS1 increases sharply, the transmitter circuit 20 can gradually increase the voltage level of the voltage signal VA through the charging current I20 compensated by the compensation current ICP1, thereby eliminating the voltage difference between the voltage level of the voltage signal VA and the voltage level of the ground terminal VSS1. Furthermore, thanks to the isolation provided by the compensation capacitor 204, the signal processing circuit 23 is also unaffected by changes in the voltage signal VA.

[0020] Please refer to Figure 3, which is another circuit block diagram of an isolated integrated circuit 400 illustrated in accordance with some embodiments of this disclosure.

[0021] In the embodiment shown in Figure 3, the receiver circuit 30 may include a signal processing circuit 33, a compensation circuit 300, and an isolation capacitor 31. The signal processing circuit 33 may be an example of the signal processing circuit 13 in Figure 1, the compensation circuit 300 may be an example of the compensation circuit 100 in Figure 1, and the isolation capacitor 31 may be an example of the isolation capacitor 11 in Figure 1. Specifically, the compensation circuit 300 includes a compensation resistor 302 and a compensation capacitor 304. The compensation resistor 302 may be coupled to a node NB and grounded at a ground terminal VSS2, along with the first terminal T1 of the isolation capacitor 31 and the compensation resistor 302. The compensation capacitor 304 may be coupled to the node NB and the signal processing circuit 33, along with the first terminal T1 of the isolation capacitor 31 and the compensation resistor 302. Furthermore, the second terminal T2 of the isolation capacitor 31 may be coupled to an input / output terminal IO3 of the receiver circuit 30, while the signal processing circuit 33 may be coupled to another input / output terminal IO4 of the receiver circuit 30.

[0022] In some embodiments, the signal processing circuit 33 of the receiver circuit 30 can be implemented by various circuits such as logic circuits, demodulators, and receivers. With this configuration, the receiver circuit 30 can receive a signal (not shown) from the transmitter circuit 20 via input / output IO3, transmit the signal via the compensation circuit 300, and demodulate the signal transmitted by the compensation circuit 300 via the signal processing circuit 33 to output the demodulated signal from input / output IO4. Furthermore, the isolation capacitor 31 of the receiver circuit 30 can serve as the aforementioned electrical isolation barrier.

[0023] When a common-mode transient event occurs, the voltage level at ground terminal VSS2 may drop sharply to a negative voltage VCMT (denoted as -VCMT in Figure 3). At this time, the voltage difference between the voltage level at ground terminal VSS2 and the voltage level of a voltage signal VB at node NB (i.e., the voltage difference between ground terminal VSS2 and node NB) may exceed expectations, thus causing a discharge current I30 from the first terminal T1 (or from node NB) to ground terminal VSS2. The discharge current I30 is used to change the voltage level of the voltage signal VB toward the negative voltage VCMT. It should be understood that the discharge current I30 may flow from the first terminal T1 into ground terminal VSS2 through some circuits in receiver circuit 30 coupled to ground terminal VSS2 (e.g., signal processing circuit 33), thus affecting some circuits coupled to ground terminal VSS2.

[0024] As described above, the compensation circuit 300 also generates a compensation current ICP2 through the compensation resistor 302 based on the voltage difference between the voltage level of the voltage signal VB and the voltage level of the ground terminal VSS2, to provide additional compensation for the discharge current I30. As the voltage level of the voltage signal VB gradually approaches the positive voltage VCMT, the compensation current ICP2 eventually approaches zero. As shown in Figure 3, the compensation current ICP2 flows out from node NB, through the compensation resistor 302, and into the ground terminal VSS2. By allowing the compensation current ICP2 to flow out from node NB, the current flowing through some circuits in the receiver circuit 30 (e.g., the signal processing circuit 33) is reduced, thereby mitigating the impact on some circuits in the receiver circuit 30. In short, when the voltage level of the ground terminal VSS2 drops sharply, the receiver circuit 30 can gradually reduce the voltage level of the voltage signal VB through the discharge current I30 compensated by the compensation current ICP2, thereby eliminating the voltage difference between the voltage level of the voltage signal VB and the voltage level of the ground terminal VSS2. Furthermore, thanks to the isolation provided by the compensation capacitor 304, the signal processing circuit 33 is also unaffected by changes in the voltage signal VB.

[0025] As can be seen from the description of the embodiments in Figures 2 and 3 above, when a common-mode transient event occurs, the compensation circuit 100 is used to respond to the voltage difference between node NA and ground terminal VSS1 (or the voltage difference between node NB and ground terminal VSS2) caused by the change in the voltage level of ground terminal VSS1 (or the voltage level of ground terminal VSS2), and generate a compensation current ICP1 to node NA (or generate a compensation current ICP2 to flow out of node NB) through compensation resistor 202 (or compensation resistor 302) to achieve current compensation for node NA (or node NB). Through the charging current I20 compensated by the compensation current ICP1 (or the discharging current I30 compensated by the compensation current ICP2), the voltage signal VA at node NA (or the voltage signal VB at node NB) also changes in response to the change in the voltage level of ground terminal VSS1 (or the voltage level of ground terminal VSS2), thereby eliminating the voltage difference between the voltage level of voltage signal VA and the voltage level of ground terminal VSS1 (or the voltage difference between the voltage level of voltage signal VB and the voltage level of ground terminal VSS2). Furthermore, the compensation circuit 100 isolates the signal processing circuit 13 from node NA (or node NB) through the compensation capacitor 204 (or compensation capacitor 304) when the voltage signal VA (or voltage signal VB) changes, to prevent the signal processing circuit 13 from being affected by the change in voltage signal VA (or voltage signal VB).

[0026] Please refer to Figure 4, which is another circuit block diagram illustrating an isolated integrated circuit 400 according to some embodiments of this disclosure. In the embodiment of Figure 4, the transmitter circuit 20 includes a signal processing circuit 23, a compensation circuit 200, and an isolation capacitor 21, and the receiver circuit 30 includes a signal processing circuit 33, a compensation circuit 300, and an isolation capacitor 31. That is, when a common-mode transient event occurs, the transmitter circuit 20 can perform current compensation through the compensation circuit 200, and the receiver circuit 30 can perform current compensation through the compensation circuit 300. The configuration and operation of the transmitter circuit 20 and the receiver circuit 30 in Figure 4 can be referred to the embodiments in Figures 2 and 3, and will not be repeated here.

[0027] It should be understood that the transmitter circuit 20 and receiver circuit 30 of the isolated integrated circuit 400 are not limited to the single-ended transmission architecture shown in Figures 2-4. In some embodiments, both the transmitter circuit 20 and receiver circuit 30 can be implemented using a differential transmission architecture. That is, the transmitter circuit 20 may include the two input / output terminals IO1 and IO2 shown in Figure 2, as well as two other input / output terminals (not shown in the figures), and these two other input / output terminals also have a circuit structure similar to the isolation capacitor 21, compensation circuit 200, and signal processing circuit 23 shown in Figure 2. Similarly, the receiver circuit 30 may include the two input / output terminals IO3 and IO4 shown in Figure 3, as well as two other input / output terminals (not shown in the figures), and these two other input / output terminals also have a circuit structure similar to the isolation capacitor 31, compensation circuit 300, and signal processing circuit 33 shown in Figure 3.

[0028] Please refer to Figure 5, which is a schematic diagram illustrating the structure of the compensation circuit 100 and the isolation capacitor 11 according to some embodiments of this disclosure. In some embodiments, the compensation circuit 100 includes a compensation resistor 102 and a compensation capacitor 104. The isolation capacitor 11 is formed by a metal plate M1 and a metal plate M2 arranged in parallel, for example, in a metal-insulator-metal (MIM) capacitor structure. The metal plate M1 serves as the second terminal T2 of the isolation capacitor 11, and the metal plate M2 serves as the first terminal T1 of the isolation capacitor 11. The compensation capacitor 104 is formed by a metal plate M2 and a metal plate M3 arranged in parallel. As can be seen from the above description, the isolation capacitor 11 and the compensation capacitor 104 share the metal plate M2.

[0029] In some further embodiments, isolation capacitor 11 is used as isolation capacitor 21 of transmitter circuit 20 in Figure 2, isolation capacitor 31 of receiver circuit 30 in Figure 3, or isolation capacitor 21 of transmitter circuit 20 and isolation capacitor 31 of receiver circuit 30 in Figure 4, to provide an electrical isolation barrier between transmitter circuit 20 and receiver circuit 30. There is a K-layer difference between metal plates M1 and M2 of isolation capacitor 11, where K is a positive integer greater than 0. In other words, the isolated integrated circuit 400 further includes at least one metal plate (not shown), and at least one metal plate is disposed between metal plates M1 and M2. Metal plates M2 and M3 are two adjacent layers; for example, metal plate M2 is the layer above or below metal plate M3, that is, metal plates M2 and M3 are continuously arranged. It should be understood that this disclosure does not limit the arrangement of metal plates M1, M2, and M3 to this.

[0030] In the embodiment shown in Figure 5, the metal plate M1 can be coupled to the input / output terminal IO1 of Figure 2 (or the input / output terminal IO3 of Figure 3). The compensation resistor 102 is coupled to the metal plate M2 at node NA of Figure 2 (or node NB of Figure 3), and the metal plate M2 is coupled to a ground terminal (e.g., ground terminal VSS1 of Figure 2 or ground terminal VSS2 of Figure 3) through the compensation resistor 102. The signal processing circuit 13 is coupled to the metal plate M3 and to the input / output terminal IO2 of Figure 2 (or the input / output terminal IO4 of Figure 3).

[0031] Furthermore, in the structure shown in Figure 5, a parasitic capacitance 40 will be generated due to the metal plate M3. Specifically, a first end of the parasitic capacitance 40 can be coupled to the metal plate M3 and the signal processing circuit 13, while a second end of the parasitic capacitance 40 can be coupled to the ground terminal. It should be understood that there may be other parasitic capacitances in the embodiment of Figure 5, but the capacitance values ​​of these parasitic capacitances are much smaller than that of the parasitic capacitance 40 and can therefore be ignored.

[0032] As mentioned above, in some related technologies, a capacitor used as an electrical isolation barrier and another capacitor in the circuit used for current compensation do not share a metal plate, which leads to a relatively large amount of parasitic capacitance after the aforementioned circuit is implemented. Compared to related technologies, this disclosure significantly reduces the generation of parasitic capacitance by having the isolation capacitor 11 and the compensation capacitor 104 share the metal plate M2. For example, the equivalent parasitic capacitance value of the isolation capacitor 11 in the isolated integrated circuit 400 using the compensation circuit 100 is reduced by about 80% compared to the equivalent parasitic capacitance value of the isolation capacitor in related technologies. Furthermore, by reducing the equivalent parasitic capacitance value, the signal amplitude transmitted by the isolated integrated circuit 400 can also be increased by about 20%, that is, the signal transmission loss is reduced.

[0033] As can be seen from the above-described embodiments of this disclosure, by providing a compensation circuit 100 between the isolation capacitor 11 and the signal processing circuit 13, the isolated integrated circuit 400 of this disclosure can effectively compensate for the current of node NA (or node NB) when a common-mode transient event occurs. Furthermore, the isolated integrated circuit 400 of this disclosure has advantages such as low parasitic capacitance, high reliability, and efficient transmission.

[0034] Although the present disclosure has been described above with reference to embodiments, it is not intended to limit the present disclosure. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the appended claims.

[0035] 11, 21, 31: Isolation capacitors 13, 23, 33: Signal processing circuits 20: Transmitter Circuit 30: Receiver circuit 40: Parasitic capacitance 100, 200, 300: Compensation circuit 102, 202, 302: Compensation resistors 104, 204, 304: Compensation capacitors 400: Isolated Integrated Circuit I20: Charging current I30: Discharge Current ICP1, ICP2: Compensation current IO1, IO2, IO3, IO4: Input / output terminals M1, M2, M3: Metal Plates NA, NB: Nodes T1: First end T2: Second end VA, VB: Voltage signals VCMT: Voltage VDD1, VDD2: Power supply terminals VSS1, VSS2: Grounding terminals

[0036] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. An isolated gate driver, comprising: an isolation capacitor including a first metal plate and a second metal plate, wherein the first metal plate is coupled to a first input / output terminal of the isolated gate driver; a compensation capacitor sharing the second metal plate with the isolation capacitor, and further including a third metal plate, wherein the first metal plate, the second metal plate, and the third metal plate are sequentially arranged; a compensation resistor directly connected to the second metal plate shared by the compensation capacitor and the isolation capacitor at a first node; and a signal processing circuit coupled to the third metal plate, receiving a first signal from the first input / output terminal through the isolation capacitor and the compensation capacitor, demodulating the first signal to generate a demodulated signal, and outputting the demodulated signal through a second input / output terminal of the isolated gate driver; wherein the second metal plate shared by the compensation capacitor and the isolation capacitor is directly connected to the compensation resistor and coupled to a ground terminal through the compensation resistor.

2. The isolated gate driver as claimed in claim 1, wherein the isolated gate driver is configured to generate a compensation current to or out of the first node through the compensation resistor in response to a voltage difference between the first node and the ground terminal caused by a steep increase or decrease in the ground terminal.

3. The isolated gate driver as claimed in claim 2, wherein when the voltage difference is caused by a steep drop at the ground terminal, the compensation current flows out from the first node, through the compensation resistor, and into the ground terminal, and wherein when the voltage difference is caused by a steep increase at the ground terminal, the compensation current flows out from the ground terminal, through the compensation resistor, and into the first node.

4. The isolated gate driver as claimed in claim 1, wherein at least one metal plate is disposed between the second metal plate and the first metal plate.

5. The isolated gate driver as described in claim 1, wherein the compensation capacitor, the compensation resistor, the isolation capacitor and the signal processing circuit are all configured in a receiver circuit of the isolated gate driver.

6. The isolated gate driver as described in claim 5 further includes a transmitter circuit, wherein the transmitter circuit is coupled to the first input / output terminal and is used to generate a modulated signal and transmit the modulated signal to the first input / output terminal as the first signal.

7. The isolated gate driver as described in claim 1, wherein: The third metal plate and the second metal plate are formed in a parallel arrangement, and the second metal plate and the first metal plate are formed in a metal-insulator-metal (MIM) capacitor structure.

8. The isolated gate driver as described in claim 1, wherein the first metal plate, the second metal plate, and the third metal plate are arranged sequentially.

9. An isolated gate driver, comprising: a signal processing circuit that receives a first signal through a first input / output terminal of the isolated gate driver and modulates the first signal to generate a modulated signal; a compensation capacitor comprising a first metal plate and a second metal plate, wherein the first metal plate is coupled to the signal processing circuit; an isolation capacitor sharing the second metal plate with the compensation capacitor and further comprising a third metal plate, wherein the third metal plate, the second metal plate, and the first metal plate are sequentially arranged; and a compensation resistor directly connected to the second metal plate shared by the compensation capacitor and the isolation capacitor; wherein the second metal plate shared by the compensation capacitor and the isolation capacitor is coupled to a ground terminal through the compensation resistor; and wherein the third metal plate is coupled to a second input / output terminal of the isolated gate driver, and the modulated signal is transmitted to the second input / output terminal through the compensation capacitor and the isolation capacitor.

10. An isolated gate driver, comprising: a transmitter circuit biased by a first voltage domain, and including: a first signal processing circuit that receives a first signal through a first input / output terminal of the transmitter circuit and modulates the first signal to generate a second signal; a first compensation capacitor including a first metal plate and a second metal plate, wherein the first metal plate is coupled to the first signal processing circuit; a first isolation capacitor sharing the second metal plate with the first compensation capacitor, and further including a third metal plate, wherein the third metal plate, the second metal plate, and the first metal plate are sequentially arranged; and a first compensation resistor directly connected to the second metal plate shared by the first compensation capacitor and the first isolation capacitor; The second metal plate shared by the first compensation capacitor and the first isolation capacitor is coupled to a first ground terminal through the first compensation resistor; and the third metal plate is coupled to a second input / output terminal of the transmitter circuit, and the second signal is transmitted to the second input / output terminal through the first compensation capacitor and the first isolation capacitor; and a receiver circuit biased by a second voltage domain different from the first voltage domain, wherein a third input / output terminal of the receiver circuit is coupled to the second input / output terminal of the transmitter circuit to receive the second signal, and includes: a second signal processing circuit that demodulates the second signal to generate a third signal, and outputs the third signal through a fourth input / output terminal of the receiver circuit; and a second compensation capacitor that includes a fourth metal plate and a fifth metal plate, wherein the fourth metal plate is coupled to the second signal processing circuit; A second isolation capacitor shares the fifth metal plate with the second compensation capacitor, and further includes a sixth metal plate, wherein the sixth metal plate, the fifth metal plate, and the fourth metal plate are arranged sequentially; and a second compensation resistor is directly connected to the fifth metal plate shared by the second compensation capacitor and the second isolation capacitor; wherein the fifth metal plate shared by the second compensation capacitor and the second isolation capacitor is coupled to a second ground terminal through the second compensation resistor; and wherein the sixth metal plate is coupled to the third input / output terminal, and the second signal is transmitted from the third input / output terminal to the second signal processing circuit through the second compensation capacitor and the second isolation capacitor.

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