Auto-optimized delay control for die-to-die receiver sampling

Abstract

A delay optimizer includes circuits for detecting delay between the received data and the received clock, such as in an integrated circuit having separate dies coupled to communication via an interconnect that includes a clock channel and a data channel. The electrical characteristics of the clock channel and the data channel (including on-chip buffers) may introduce significant differences in the delay between the received clock and the received data coupled with the effects of clock jitter, inter-symbol interference, and duty-cycle distortion that may introduce significant sampling errors in the sampled data. The delay optimizer operates to detect the delay and optimize a sampling clock in real-time and on a continuous basis using the difference between the data edge of the received data and the received clock edge to determine an optimal delay value to sample the received data to produce the sampled data with the desired very-low bit-error-rate (BER).

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