Semiconductor device and operation method thereof

Abstract

Provided are a semiconductor device and an operation method thereof to transmit data signals and clock signals between different dies. The semiconductor device includes a first die and a second die. The second die includes a first controllable delay line, a clock tree circuit, a second controllable delay line, and a data channel. The first controllable delay line receives a source clock signal of the first die through a clock interconnection. An input terminal of the clock tree circuit receives a first delayed clock signal of the first controllable delay line. The clock tree circuit provides a gain clock signal to the second controllable delay line and the data channel. The second controllable delay line provides a second delayed clock signal to the data channel. The data channel receives the data signal of the first die through a data interconnection.

Description

[Technical Field]

[0001] This invention relates to an integrated circuit, and more particularly to a semiconductor device and its operation method. [Previous Technology]

[0002] In the physical layer of integrated circuits, clock tree circuits are often required to generate clock signals for sampling data signals. In 2.5D packaging, data transmission between different dies is based on the triggering timing of clock signals. Generally, the phase of the clock signal used by the receiver die should match the phase of the clock signal used by the transmitter die in order to correctly sample the data signal. How to efficiently transmit data between different dies is one of the many technical issues in the field of integrated circuit technology. [Summary of the Invention]

[0003] The present invention provides a semiconductor device and a method of operating the same for transmitting data signals and clock signals between different dies.

[0004] In one embodiment of the present invention, the semiconductor device includes a first die, an in-package interconnect portion, and a second die. The first die and the second die are arranged in the same package. The first die includes a first clock tree circuit and a first data channel. The output terminal of the first clock tree circuit is coupled to the trigger terminal of the first data channel. The first clock tree circuit generates a first amplified clock signal to the first data channel based on a first source clock signal. The in-package interconnect portion includes a first clock interconnect and a first data interconnect. A first terminal of the first clock interconnect is coupled to the first die to receive the first source clock signal. A first terminal of the first data interconnect is coupled to the output terminal of the first data channel of the first die. The second die includes a first controllable delay line, a second controllable delay line, a second clock tree circuit, and a second data channel. The input terminal of the first controllable delay line is coupled to the second terminal of the first clock interconnect to receive the first source clock signal of the first die. The input terminal of the second clock tree circuit is coupled to the first controllable delay line to receive the first delayed clock signal. The output of the second clock tree circuit is coupled to the input of the second controllable delay line and the first trigger terminal of the second data channel to provide a second gained clock signal. The output of the second controllable delay line is coupled to the second trigger terminal of the second data channel to provide a second delayed clock signal. The input of the second data channel is coupled to the second terminal of the first data interconnect.

[0005] In one embodiment of the present invention, the above-described operation method includes: a first clock tree circuit of a first die of a semiconductor device generating a first gained clock signal to a first data channel of the first die based on a first source clock signal; the first data channel outputting a first data signal to a first data interconnect of the package interconnect portion of the semiconductor device based on the triggering of the first gained clock signal; a first controllable delay line of a second die of the semiconductor device delaying the first source clock signal from the first clock interconnect to generate a first delayed clock signal; a second clock tree circuit of the second die generating a second gained clock signal to a second data channel of the second die based on the first delayed clock signal; a second controllable delay line generating a second delayed clock signal to the second data channel based on the second gained clock signal; and the second data channel sampling the first data signal from the first data interconnect based on the triggering of the second gained clock signal and the second delayed clock signal.

[0006] Based on the above, in the embodiments of the present invention, a second controllable delay line is arranged at the trigger terminal of the data channel of the second die. The clock tree circuit of the second die generates a second gained clock signal for the data channel of the second die and the second controllable delay line. The second controllable delay line converts the second gained clock signal of the clock tree circuit of the second die into a second delayed clock signal for the data channel of the second die. The data channel samples the double data rate (DDR) data signal from the first die based on the second gained clock signal and the second delayed clock signal. Therefore, the transmission latency of the data signal can be effectively shortened.

[0007] In order to make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below, and detailed descriptions are given in conjunction with the accompanying drawings.

Implementation Method

[0008] The term "coupled (or connected)" as used throughout the entire specification (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or some means of connection. The terms "first," "second," etc., used throughout the entire specification (including the claims) are used to name elements or distinguish different embodiments or scopes, and are not intended to limit the upper or lower limit of the number of elements, nor to limit the order of elements. Furthermore, wherever possible, elements / components / steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Elements / components / steps using the same reference numerals or the same terms in different embodiments may be referred to mutually in the relevant descriptions.

[0009] This invention relates to data transmission between two dies arranged in the same package. Several embodiments are provided below to illustrate the invention, but the implementation of the invention is not limited to the embodiments described.

[0010] FIG1A is a schematic cross-sectional view of a three-dimensional structure of a semiconductor device 10A according to an embodiment. The semiconductor device 10A may include dies 24 and dies 34. In addition to being horizontally distributed, dies 24 and dies 34 may also be stacked vertically together. Dies 24 and dies 34 are electrically connected to each other and stacked to form a three-dimensional structure, forming a three-dimensional semiconductor element. The stacked structure of the semiconductor device 10A can employ any three-dimensional packaging technology, such as system-on-integrated-chips (SoIC) packaging, wafer-on-wafer (WoW) packaging, chip-on-wafer-on-substrate (CoWoS) packaging, or other three-dimensional packaging technologies.

[0011] In some practical applications (but not limited to), die 34 can be a slave device, while die 24 can be a master device. Die 24 typically includes a substrate 20 and a circuit layer 22. Die 34 is stacked on top of die 24. At least one bump 26 (e.g., a microbump or hybrid-bump) is formed between die 24 and die 34. Die 34 includes a substrate 30 and a circuit layer 32. Through-hole structures of the packaging process, such as through-silicon vias (TSVs) 36 with connection pads 38, are formed at corresponding locations on die 34. Connection pads 38 are formed on the outermost surface corresponding to the through-silicon via 36.

[0012] FIG1B is a cross-sectional schematic diagram of a three-dimensional structure of a semiconductor device 10B according to another embodiment. The semiconductor device 10B may include dies 44 and dies 54. In addition to being horizontally distributed, dies 44 and dies 54 may also be stacked vertically together. Dies 44 and dies 54 are electrically connected to each other and stacked to form a three-dimensional structure, forming a three-dimensional semiconductor element. The stacked structure of the semiconductor device 10B can employ any three-dimensional packaging technology, such as SoIC packaging, WoW packaging, CoWoS packaging, or other three-dimensional packaging technologies. In some practical applications (but not limited to), die 54 may be a slave device, while die 44 may be a master device. Die 44 typically includes a substrate 40 and a circuit layer 42. Through-hole structures of the packaging process, such as silicon through-holes 46, are formed between dies 44 and dies 54. Die 54 includes a substrate 50 and a circuit layer 52. Silicon through-holes 56 with connection pads 58 are formed at corresponding positions on die 54. The connecting pad 58 is formed on the outermost surface corresponding to the silicon perforation 56.

[0013] FIG1C is a schematic cross-sectional view of a 2.5-dimensional package structure of a semiconductor device 10C according to another embodiment. The semiconductor device 10C shown in FIG1C may include a die 60 and a die 70. In the embodiment shown in FIG1C, the die 70 is a three-dimensional semiconductor element formed by vertically stacking a plurality of dies together. Dies 60 and 70 are disposed on an interposer 11, and the interposer 11 is disposed on a package substrate 12. Dies 60 and 70 are electrically connected to each other through interconnects (wires) in the interposer 11. In some practical applications (but not limited to), the die 70 may be a slave device (e.g., a memory cell die and a controller die), while the die 60 may be a master device (e.g., a central processing unit).

[0014] FIG1D is a schematic cross-sectional view of a 2.5-dimensional package structure of a semiconductor device 10D according to another embodiment. The semiconductor device 10D shown in FIG1D may include dies 80 and dies 90. In the embodiment shown in FIG1D, die 90 is a three-dimensional semiconductor element formed by vertically stacking a plurality of dies together. Dies 80 and dies 90 are arranged on a bridge chip 13, which is arranged on a package substrate 14. Dies 80 and dies 90 are electrically connected to each other through interconnects of the bridge chip 13. In some practical applications (but not limited to), die 90 may be a slave device (e.g., a memory cell die and a controller die), while die 80 may be a master device (e.g., a central processing unit).

[0015] FIG2 is a schematic diagram of a circuit block of a semiconductor device 200 according to an embodiment. The semiconductor device 200 shown in FIG2 includes a die 210 and a die 220. The die 210, the die 220, and the in-package interconnect 230 are arranged in the same package. For example (but not limited to), the die 210 and the die 220 are arranged in the same package in a three-dimensional structure as shown in FIG1A or FIG1B. Therefore, the die 210 and the die 220 shown in FIG2 can be deduced by analogy with the relevant description of the die 24 and the die 34 shown in FIG1A, or by analogy with the relevant description of the die 44 and the die 54 shown in FIG1B. Alternatively, the die 210 and the die 220 are arranged in the same package in a 2.5-dimensional structure as shown in FIG1C or FIG1D. Therefore, the descriptions of grains 210 and 220 shown in Figure 2 can be drawn by analogy with the descriptions of grains 60 and 70 shown in Figure 1C, or by analogy with the descriptions of grains 80 and 90 shown in Figure 1D.

[0016] Dies 210 and 220 can be electrically connected to each other via package interconnects 230. In some applications, package interconnects 230 include an interposer or bridging chip in a 2.5D package. In the embodiment shown in FIG. 2, package interconnects 230 include data interconnects CONN 21, clock interconnects CONN 22, clock interconnects CONN 23, and data interconnects CONN 24. Dies 210 and 220 can be electrically connected to each other via different interconnects CONN 21, CONN 22, CONN 23, and CONN 24 of package interconnects 230. Depending on the actual design, dies 210 and 220 can be stacked into a three-dimensional structure or a 2.5D structure. For example, the interconnects CONN21 to CONN24 shown in Figure 2 can be implemented using bumps; that is, the interconnects CONN21 to CONN24 shown in Figure 2 can be described with reference to the relevant explanation of bump 26 shown in Figure 1A and by analogy. In other application examples, the interconnects CONN21 to CONN24 shown in Figure 2 can be implemented using silicon vias; that is, the interconnects CONN21 to CONN24 shown in Figure 2 can be described with reference to the relevant explanation of silicon via 46 shown in Figure 1B and by analogy. In still other application examples, the interconnects CONN21 to CONN24 shown in Figure 2 can be implemented using an interposer layer; that is, the interconnects CONN21 to CONN24 shown in Figure 2 can be described with reference to the relevant explanation of the interconnects (wires) of interposer layer 11 shown in Figure 1C and by analogy. In some other applications, the interconnects CONN21 to CONN24 shown in Figure 2 can be implemented using a bridging chip. That is, the interconnects CONN21 to CONN24 shown in Figure 2 can be deduced from the relevant description of the interconnects of the bridging chip 13 shown in Figure 1D.

[0017] Die 210 includes a core circuit CORE 21 and an interface device IF 21, and die 220 includes a core circuit CORE 22 and an interface device IF 22. Depending on the design, in some embodiments, the aforementioned core circuit CORE 21 and / or CORE 22 may be implemented as hardware circuits. In other embodiments, the core circuit CORE 21 and / or CORE 22 may be implemented as a combination of hardware and firmware.

[0018] In hardware form, the aforementioned core circuits CORE21 and / or CORE22 can be implemented as logic circuits on integrated circuits. For example, the related functions of core circuits CORE21 and / or CORE22 can be implemented in various logic blocks, modules, and circuits within one or more controllers, microcontrollers, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), central processing units (CPUs), and / or other processing units. The related functions of core circuits CORE21 and / or CORE22 can be implemented as hardware circuits, such as various logic blocks, modules, and circuits in integrated circuits, using hardware description languages ​​(such as Verilog HDL or VHDL) or other suitable programming languages.

[0019] In firmware form, the functions of the aforementioned core circuits CORE21 and / or CORE22 can be implemented as programming codes. For example, the core circuits CORE21 and / or CORE22 can be implemented using general programming languages ​​(such as C, C++, or assembly languages) or other suitable programming languages. The programming code can be recorded / stored in a non-transitory machine-readable storage medium. In some embodiments, the non-transitory machine-readable storage medium includes, for example, semiconductor memory and / or storage devices. Electronic devices (e.g., CPUs, controllers, microcontrollers, or microprocessors) can read and execute the programming code from the non-transitory machine-readable storage medium to implement the functions of the core circuits CORE21 and / or CORE22.

[0020] The interface device IF21 of the die 210 includes a controllable delay line TX1_DL21, a clock tree circuit TX1_CT21, and a data channel TX1_CH21. The controllable delay line TX1_DL21 receives the source clock signal TX1_CK21 from the core circuit CORE21. The controllable delay line TX1_DL21 adjusts the delay of the source clock signal TX1_CK21, thereby delaying the source clock signal TX1_CK21 to generate a source clock signal TX1_CK22 (delayed clock signal) to the clock tree circuit TX1_CT21 and the clock interconnect CONN23. This embodiment does not limit the specific implementation of the controllable delay line TX1_DL21. For example, based on actual design, the controllable delay line TX1_DL21 may include a digital controlled delay line (DCDL) or other delay circuits.

[0021] The clock tree circuit TX1_CT21 is coupled to the controllable delay line TX1_DL21 to receive the source clock signal TX1_CK22. The output of the clock tree circuit TX1_CT21 is coupled to the trigger terminal of the data channel TX1_CH21. The clock tree circuit TX1_CT21 generates a boosted clock signal TX1_CK23 based on the source clock signal TX1_CK22 and sends it to the data channel TX1_CH21. The clock tree circuit TX1_CT21 can boost the fan-out of the source clock signal TX1_CK22. The input terminal I0 of the data channel TX1_CH21 is coupled to the core circuit CORE21 to receive the data signal TX1_DI21. The input terminal I1 of the data channel TX1_CH21 is coupled to the core circuit CORE21 to receive the data signal TX1_DI22. Data channel TX1_CH21 can sample the Single Data Rate (SDR) data signals TX1_DI21 and TX1_DI22 based on the triggering of the gain clock signal TX1_CK23 to generate the Double Data Rate (DDR) data signal TX1_DO21. The output terminal of data channel TX1_CH21 is Z-coupled to data interconnect CONN21 to provide the data signal TX1_DO21.

[0022] Figure 3 is a timing diagram of data signals and clock signals according to an embodiment. The horizontal axis of Figure 3 represents time. The data signals TX1_DI21, TX1_DI22, TX1_CK23, TX1_DO21, RX2_DI21, RX2_CK24, RX2_DO21, and RX2_DO22 shown in Figure 3 can be referred to the relevant description in Figure 2. The data D0, D1, D2, D3, D4, D5, D6, and D7 shown in Figure 3 represent the data content (e.g., data, commands, and / or addresses) output by the die 210 to the die 220.

[0023] Referring to Figures 2 and 3, the data channel TX1_CH21 can sample data signals TX1_DI21 and TX1_DI22 from the core circuit CORE21 based on the triggering of the gain clock signal TX1_CK23. The data channel TX1_CH21 may include a multiplexer or other data channel circuits. In the embodiment shown in Figure 3, the data channel TX1_CH21 samples the data signal TX1_DI21 based on the falling edge of the gain clock signal TX1_CK23, and the data channel TX1_CH21 samples the data signal TX1_DI22 based on the rising edge of the gain clock signal TX1_CK23, thereby generating the DDR data signal TX1_DO21. The data channel TX1_CH21 can output the data signal TX1_DO21 to the die 220 through the data interconnect CONN21 of the package interconnect 230. The data signal TX1_DO21 is transmitted through the data interconnect CONN21 and becomes the data signal RX2_DI21. In addition, the interface device IF21 can output the source clock signal TX1_CK22 to the chip 220 through the clock interconnect CONN23 of the package interconnect 230.

[0024] The interface device IF22 of the die 220 includes a phase detector RX2_PD21, a controllable delay line RX2_DL21, a clock tree circuit RX2_CT21, and a data channel RX2_CH21. A first terminal of the clock interconnect CONN22 is coupled to the die 210 to receive the amplified clock signal TX1_CK23. A first terminal of the clock interconnect CONN23 is coupled to the die 210 to receive the source clock signal TX1_CK22. An input terminal of the controllable delay line RX2_DL21 is coupled to a second terminal of the clock interconnect CONN23 to receive the source clock signal TX1_CK22 from the die 210. Depending on the actual design, the controllable delay line RX2_DL21 may include a digitally controlled delay line or other delay circuitry. The input of the clock tree circuit RX2_CT21 is coupled to the controllable delay line RX2_DL21 to receive the delayed clock signal RX2_CK23. Based on the delayed clock signal RX2_CK23, the clock tree circuit RX2_CT21 generates a gain clock signal RX2_CK24 and sends it to the first and second trigger terminals of the data channel RX2_CH21.

[0025] The first input terminal of the phase detector RX2_PD21 is coupled to the second terminal of the clock interconnect CONN22 to receive the gained clock signal TX1_CK23 from the die 210. The second input terminal of the phase detector RX2_PD21 is coupled to the output terminal of the clock tree circuit RX2_CT21 to receive the gained clock signal RX2_CK24. The phase detector RX2_PD21 detects the phase difference between the gained clock signals TX1_CK23 and RX2_CK24, and provides phase relationship information corresponding to the phase difference to the core circuit CORE22. For example (but not limited to), the phase relationship information may indicate whether the gained clock signal RX2_CK24 lags behind or leads the gained clock signal TX1_CK23. The core circuit CORE22 adjusts the delay amount of the controllable delay line RX2_DL21 according to the phase relationship information.

[0026] The first terminal of the data interconnect CONN21 is coupled to the output terminal of the data channel TX1_CH21 of the die 210 to receive the data signal TX1_DO21. The data signal TX1_DO21 becomes the data signal RX2_DI21 through the transmission of the data interconnect CONN21. The input terminal of the data channel RX2_CH21 of the die 220 is coupled to the second terminal of the data interconnect CONN21 to receive the data signal RX2_DI21. The data channel RX2_CH21 can sample the data signal RX2_DI21 from the data interconnect CONN21 based on the triggering of the gain clock signal RX2_CK24 to generate data signals RX2_DO21 and RX2_DO22 for the core circuit CORE22.

[0027] In the embodiment shown in Figure 3, data channel RX2_CH21 samples data signal RX2_DI21 based on the rising edge of the gain clock signal RX2_CK24 to generate data signal RX2_DO21 for core circuit CORE22. Data channel RX2_CH21 samples data signal RX2_DI21 based on the falling edge of the gain clock signal RX2_CK24 to generate data signal RX2_DO22 for core circuit CORE22. The transmission latency between data signal TX1_DI21 sent by core circuit CORE21 and data signal RX2_DO21 received by core circuit CORE22 is LT32.

[0028] In the embodiment shown in FIG. 2, the data channel RX2_CH21 includes flip-flops RX2_FF21 and RX2_FF22. The input terminals D of flip-flops RX2_FF21 and RX2_FF22 are coupled to the input terminals of the data channel RX2_CH21. The trigger terminal of flip-flops RX2_FF21 is coupled to the first trigger terminal of the data channel RX2_CH21. The trigger terminal of flip-flops RX2_FF22 is coupled to the second trigger terminal of the data channel RX2_CH21. The output terminal Q of flip-flops RX2_FF21 is coupled to the core circuit CORE22 to provide the data signal RX2_DO21. The output terminal Q of flip-flops RX2_FF22 is coupled to the core circuit CORE22 to provide the data signal RX2_DO22.

[0029] The interface device IF22 of die 220 also includes a clock tree circuit TX2_CT21 and a data channel TX2_CH21, and the interface device IF21 of die 210 also includes a clock tree circuit RX1_CT21 and a data channel RX1_CH21. Die 220 can output the data signal TX2_DO21 to the data channel RX1_CH21 of die 210 through the data interconnect CONN24 of the package interconnect 230, thus becoming the data signal RX1_DI21.

[0030] In detail, the clock tree circuit TX2_CT21 receives the delayed clock signal RX2_CK23 from the controllable delay line RX2_DL21. The clock tree circuit TX2_CT21 can amplify the fan-out of the delayed clock signal RX2_CK23. Based on the delayed clock signal RX2_CK23, the clock tree circuit TX2_CT21 generates an amplified clock signal TX2_CK24 and sends it to the trigger terminal of the data channel TX2_CH21. The input terminal I0 of the data channel TX2_CH21 is coupled to the core circuit CORE22 to receive the data signal TX2_DI21. The input terminal I1 of the data channel TX2_CH21 is coupled to the core circuit CORE22 to receive the data signal TX2_DI22. Data channel TX2_CH21 can sample the single data rate (SDR) data signals TX2_DI21 and TX2_DI22 of die 220 based on the triggering of the gain clock signal TX2_CK24 to generate the double data rate (DDR) data signal TX2_DO21. The output terminal of data channel TX2_CH21 is Z-coupled to the data interconnect CONN24 of the package interconnect 230 to output the data signal TX2_DO21 to die 210 through the data interconnect CONN24.

[0031] The gain source clock signal TX1_CK22 of the clock tree circuit RX1_CT21 is fanned out to generate a gain clock signal RX1_CK23, which is then sent to the first and second trigger terminals of the data channel RX1_CH21. The data channel RX1_CH21 can sample the data signal RX1_DI21 from the data interconnect CONN24 based on the triggering of the gain clock signal RX1_CK23, to generate data signals RX1_DO21 and RX1_DO22 for the core circuit CORE21. In detail, the data channel RX1_CH21 samples the data signal RX1_DI21 based on the rising edge of the gain clock signal RX1_CK23 to generate the data signal RX1_DO21 for the core circuit CORE21. Data channel RX1_CH21 samples data signal RX1_DI21 based on the falling edge of the gain clock signal RX1_CK23 to generate data signal RX1_DO22 for the core circuit CORE21. The description of data channel RX1_CH21 can be referenced from that of data channel RX2_CH21 and is therefore not repeated here.

[0032] FIG4 is a circuit block diagram of a semiconductor device 400 according to an embodiment of the present invention. The semiconductor device 400 shown in FIG4 includes a die 410 and a die 420. The die 410 and the die 420 can transmit data signals and clock signals to each other through an in-package interconnect 430. The die 410, the die 420 and the in-package interconnect 430 are arranged in the same package. For example (but not limited to), the die 410 and the die 420 are arranged in the same package in a three-dimensional structure as shown in FIG1A or FIG1B. That is, the die 410 and the die 420 shown in FIG4 can be deduced by analogy with the relevant description of the die 24 and the die 34 shown in FIG1A, or by analogy with the relevant description of the die 44 and the die 54 shown in FIG1B. Alternatively, the die 410 and the die 420 are arranged in the same package in a 2.5-dimensional structure as shown in FIG1C or FIG1D. That is, the descriptions of grains 410 and 420 shown in Figure 4 can be deduced by referring to the descriptions of grains 60 and 70 shown in Figure 1C, or by referring to the descriptions of grains 80 and 90 shown in Figure 1D.

[0033] In the embodiment shown in FIG4, die 410 and die 420 can be electrically connected to each other through different interconnects CONN41, CONN42, CONN43 and CONN44 of the package interconnect portion 430. According to actual design, in some application examples, the interconnects CONN41 to CONN44 shown in FIG4 can be implemented using bumps; that is, the interconnects CONN41 to CONN44 shown in FIG4 can be deduced from the relevant description of bump 26 shown in FIG1A. In other application examples, the interconnects CONN41 to CONN44 shown in FIG4 can be implemented using silicon vias; that is, the interconnects CONN41 to CONN44 shown in FIG4 can be deduced from the relevant description of silicon via 46 shown in FIG1B. In some other applications, the interconnects CONN41 to CONN44 shown in Figure 4 can be implemented using an interposer layer. That is, the interconnects CONN41 to CONN44 shown in Figure 4 can be deduced by referring to the relevant description of the interconnects (wires) of the interposer layer 11 shown in Figure 1C. In still other applications, the interconnects CONN41 to CONN44 shown in Figure 4 can be implemented using a bridging chip. That is, the interconnects CONN41 to CONN44 shown in Figure 4 can be deduced by referring to the relevant description of the interconnects of the bridging chip 13 shown in Figure 1D.

[0034] The die 410 includes a core circuit CORE41 and an interface device IF41. The interface device IF41 of the die 410 includes a controllable delay line TX1_DL41, a clock tree circuit TX1_CT41, a data channel TX1_CH41, a clock tree circuit RX1_CT41, a controllable delay line RX1_DL41, a phase detector RX1_PD41, and a data channel RX1_CH41. The die 410, core circuit CORE41, interface device IF41, controllable delay line TX1_DL41, clock tree circuit TX1_CT41, data channel TX1_CH41, clock tree circuit RX1_CT41, and data channel RX1_CH41 shown in Figure 4 can be deduced by referring to the relevant descriptions of the die 210, core circuit CORE21, interface device IF21, controllable delay line TX1_DL21, clock tree circuit TX1_CT21, data channel TX1_CH21, clock tree circuit RX1_CT21, and data channel RX1_CH21 shown in Figure 2.

[0035] This embodiment does not limit the specific implementation of the controllable delay line TX1_DL41. For example, based on actual design, the controllable delay line TX1_DL41 may include a digitally controlled delay line (DCDL) or other delay circuits. The controllable delay line TX1_DL41 receives the source clock signal TX1_CK41 from the core circuit CORE41. The controllable delay line TX1_DL41 adjusts the delay amount of the source clock signal TX1_CK41, thereby delaying the source clock signal TX1_CK41 to generate a source clock signal TX1_CK42 (delayed clock signal) to the clock tree circuit TX1_CT41 and the clock interconnect CONN43. The source clock signal TX1_CK42 is output to the die 420 through the clock interconnect CONN43 of the package interconnect 430.

[0036] The output of the clock tree circuit TX1_CT41 is coupled to the trigger terminal of the data channel TX1_CH41. The clock tree circuit TX1_CT41 generates a boosted clock signal TX1_CK43 based on the source clock signal TX1_CK42 of the controllable delay line TX1_DL41 and sends it to the data channel TX1_CH41 and the clock interconnect CONN42. The boosted clock signal TX1_CK43 is output to the chip 420 through the clock interconnect CONN42 of the package interconnect 430. The data channel TX1_CH41 samples the SDR data signals TX1_DI41 and TX1_DI42 based on the trigger of the boosted clock signal TX1_CK43 to generate the DDR data signal TX1_DO41 and send it to the data interconnect CONN41.

[0037] The clock tree circuit RX1_CT41 generates a gained clock signal RX1_CK43 from the gained clock signal TX1_CK42. The output of the clock tree circuit RX1_CT41 is coupled to the input of the controllable delay line RX1_DL41, the first input of the phase detector RX1_PD41, and the second trigger of the data channel RX1_CH41. The output of the controllable delay line RX1_DL41 is coupled to the second input of the phase detector RX1_PD41 and the first trigger of the data channel RX1_CH41. The controllable delay line RX1_DL41 generates a delayed clock signal RX1_CK44 based on the gained clock signal RX1_CK43 and sends it to the first trigger of the data channel RX1_CH41. Data channel RX1_CH41 samples the DDR data signal RX1_DI41 from data interconnect CONN44 based on the gain clock signal RX1_CK43 and the delay clock signal RX1_CK44 to generate SDR data signals RX1_DO41 and RX1_DO42 for the core circuit CORE41.

[0038] In detail, the data channel RX1_CH41 samples the data signal RX1_DI41 based on the rising edge of the gain clock signal RX1_CK43 to generate the data signal RX1_DO41 for the core circuit CORE41. The data channel RX1_CH41 samples the data signal RX1_DI41 based on the falling edge of the delay clock signal RX1_CK44 to generate the data signal RX1_DO42 for the core circuit CORE41. The clock tree circuit RX1_CT41, the controllable delay line RX1_DL41, the phase detector RX1_PD41, and the data channel RX1_CH41 can be referred to the relevant descriptions of the clock tree circuit RX2_CT41, the controllable delay line RX2_DL42, the phase detector RX2_PD42, and the data channel RX2_CH41 (detailed later) and deduced by analogy, so they will not be repeated here.

[0039] The die 420 includes a core circuit CORE42 and an interface device IF42. The interface device IF42 of the die 420 includes a phase detector RX2_PD41, a phase detector RX2_PD42, a controllable delay line RX2_DL41, a controllable delay line RX2_DL42, a clock tree circuit RX2_CT41, a data channel RX2_CH41, a clock tree circuit TX2_CT41, and a data channel TX2_CH41. The clock tree circuit TX2_CT41 generates a gain clock signal TX2_CK44 based on the delayed clock signal RX2_CK43 of the controllable delay line RX2_DL41 and sends it to the trigger terminal of the data channel TX2_CH41. Data channel TX2_CH41 samples data signals TX2_DI41 and TX2_DI42 from chip 420 based on the gain clock signal TX2_CK44, generating data signal TX2_DO41 to the first terminal of data interconnect CONN44. Data interconnect CONN44 transmits data signal TX2_DO41 to chip 410, which then becomes data signal RX1_DI41. The components shown in Figure 4, including die 420, core circuit CORE42, interface device IF42, phase detector RX2_PD41, controllable delay line RX2_DL41, clock tree circuit RX2_CT41, data channel RX2_CH41, clock tree circuit TX2_CT41, and data channel TX2_CH41, can be deduced from the descriptions of die 220, core circuit CORE22, interface device IF22, phase detector RX2_PD21, controllable delay line RX2_DL21, clock tree circuit RX2_CT21, data channel RX2_CH21, clock tree circuit TX2_CT21, and data channel TX2_CH21 shown in Figure 2. Therefore, they will not be described in detail here.

[0040] The input terminal of the controllable delay line RX2_DL41 is coupled to the second terminal of the clock interconnect CONN43 to receive the source clock signal TX1_CK42 from the die 410. Depending on the actual design, the controllable delay line RX2_DL41 may include a digitally controlled delay line or other delay circuits. The input terminal of the clock tree circuit RX2_CT41 is coupled to the controllable delay line RX2_DL41 to receive the delayed clock signal RX2_CK43. The output terminal of the clock tree circuit RX2_CT41 is coupled to the second input terminal of the phase detector RX2_PD41, the first input terminal of the phase detector RX2_PD42, the input terminal of the controllable delay line RX2_DL42, and the first trigger terminal of the data channel RX2_CH41. The clock tree circuit RX2_CT41 generates a gain clock signal RX2_CK44 based on the delayed clock signal RX2_CK43, which is then fed to the controllable delay line RX2_DL42 and the data channel RX2_CH41.

[0041] The output of the controllable delay line RX2_DL42 is coupled to the second trigger terminal of the data channel RX2_CH41 to provide a delayed clock signal RX2_CK45. The second input terminal of the phase detector RX2_PD42 is coupled to the output of the controllable delay line RX2_DL42 to receive the delayed clock signal RX2_CK45. The phase detector RX2_PD42 detects the phase difference between the gained clock signal RX2_CK44 and the delayed clock signal RX2_CK45. The controllable delay line RX2_DL42 adjusts the delay of the delayed clock signal RX2_CK45 in response to the phase difference between the clock signals RX2_CK44 and RX2_CK45. For example, the phase detector RX2_PD42 detects the phase difference between the gained clock signal RX2_CK44 and the delayed clock signal RX2_CK45, and provides the phase relationship information corresponding to the phase difference to the core circuit CORE42. The core circuit CORE42 adjusts the delay of the controllable delay line RX2_DL42 according to the phase relationship information.

[0042] The input terminal of data channel RX2_CH41 is coupled to the second terminal of data interconnect CONN41 to receive data signal RX2_DI41. Data channel RX2_CH41 samples the data signal RX2_DI41 from data interconnect CONN41 based on the triggering of gain clock signal RX2_CK44 to generate data signal RX2_DO41 to the core circuit CORE42. Data channel RX2_CH41 samples the data signal RX2_DI41 from data interconnect CONN41 based on the triggering of delay clock signal RX2_CK45 to generate data signal RX2_DO42 to the core circuit CORE42.

[0043] In the embodiment shown in FIG. 4, the data channel RX2_CH41 includes flip-flops RX2_FF41 and RX2_FF42. The input terminals D of flip-flops RX2_FF41 and RX2_FF42 are coupled to the input terminals of the data channel RX2_CH41. The trigger terminal of flip-flops RX2_FF41 is coupled to the first trigger terminal of the data channel RX2_CH41. The trigger terminal of flip-flops RX2_FF42 is coupled to the second trigger terminal of the data channel RX2_CH41. The output terminal Q of flip-flops RX2_FF41 is coupled to the core circuit CORE42 to provide the data signal RX2_DO41. The output terminal Q of flip-flops RX2_FF42 is coupled to the core circuit CORE42 to provide the data signal RX2_DO42.

[0044] Figure 5 is a timing diagram of data signals and clock signals according to another embodiment of the present invention. The horizontal axis of Figure 5 represents time. The data signals TX1_DI41, TX1_DI42, TX1_CK43, TX1_DO41, RX2_DI41, RX2_CK44, RX2_CK45, RX2_DO41, and RX2_DO42 shown in Figure 5 can be referred to the relevant description in Figure 4. The data D0, D1, D2, D3, D4, D5, D6, and D7 shown in Figure 5 represent the data content (e.g., data, commands, and / or addresses) output by the die 410 to the die 420.

[0045] Referring to Figures 4 and 5, the data channel TX1_CH41 can sample the SDR data signals TX1_DI41 and TX1_DI42 from the core circuit CORE41 based on the triggering of the gain clock signal TX1_CK43. In the embodiment shown in Figure 5, the data channel TX1_CH41 samples the data signal TX1_DI41 based on the falling edge of the gain clock signal TX1_CK43, and the data channel TX1_CH41 samples the data signal TX1_DI42 based on the rising edge of the gain clock signal TX1_CK43, thereby generating the DDR data signal TX1_DO41 to the data interconnect CONN41. The data signal TX1_DO41 becomes the data signal RX2_DI41 through the transmission of the data interconnect CONN41. In addition, the interface device IF41 can output the source clock signal TX1_CK42 to the die 420 through the clock interconnect CONN43 of the package interconnect 430.

[0046] The clock tree circuit RX2_CT41 generates a gained clock signal RX2_CK44 based on the delayed clock signal RX2_CK43 from the controllable delay line RX2_DL41, which is then fed to the first trigger terminal of the data channel RX2_CH41 and the input terminal of the controllable delay line RX2_DL42. The controllable delay line RX2_DL42 converts the gained clock signal RX2_CK44 into a delayed clock signal RX2_CK45, which is then fed to the second trigger terminal of the data channel RX2_CH41. In the embodiment shown in FIG5, the data channel RX2_CH41 samples the data signal RX2_DI41 based on the rising edge of the gained clock signal RX2_CK44 to generate the data signal RX2_DO41 for the core circuit CORE42. Data channel RX2_CH41 desamples data signal RX2_DI41 based on the falling edge of delayed clock signal RX2_CK45 to generate data signal RX2_DO42 for core circuit CORE42. The transmission latency between the data signals TX1_DI41 and TX1_DI42 sent by core circuit CORE41 and the data signals RX2_DO41 and RX2_DO42 received by core circuit CORE42 is LT52.

[0047] In summary, a controllable delay line RX2_DL42 is arranged at the trigger terminal of the data channel RX2_CH41 of the die 420. The controllable delay line RX2_DL42 converts the gained clock signal RX2_CK44 of the clock tree circuit RX2_CT41 of the die 420 into a delayed clock signal RX2_CK45 for the data channel RX2_CH41 of the die 420. The data channel RX2_CH41 samples the DDR data signal RX2_DI41 from the die 410 based on the gained clock signal RX2_CK44 and the delayed clock signal RX2_CK45 to generate SDR data signals RX2_DO41 and RX2_DO42 for the core circuit CORE42. Therefore, compared to the transmission delay time LT32 shown in FIG3, the transmission delay time LT52 of the data signal of the semiconductor device 400 can be effectively shortened in the embodiments shown in FIG4 and FIG5.

[0048] FIG6 is a schematic flowchart of an operation method of a semiconductor device according to an embodiment of the present invention. In step S610, the clock tree circuit TX1_CT41 of the die 410 (first die) of the semiconductor device 400 generates a data channel TX1_CH41 of the die 410 through a gain clock signal TX1_CK43 (first gain clock signal) based on the source clock signal TX1_CK42. In step S620, the data channel TX1_CH41 of the die 410 outputs a data signal TX1_DO41 (first data signal) to the data interconnect CONN41 of the package interconnect portion 430 of the semiconductor device 400 based on the triggering of the gain clock signal TX1_CK43. In step S630, the controllable delay line RX2_DL41 of the die 420 (second die) of the semiconductor device 400 delays the source clock signal TX1_CK42 from the clock interconnect CONN43 to generate the delayed clock signal RX2_CK43.

[0049] In step S640, the clock tree circuit RX2_CT41 of the die 420 of the semiconductor device 400 generates a gain clock signal RX2_CK44 (a second gain clock signal) based on the delayed clock signal RX2_CK43 of the controllable delay line RX2_DL41 and sends it to the data channel RX2_CH41 of the die 420. In step S650, the controllable delay line RX2_DL42 of the die 420 generates a delayed clock signal RX2_CK45 based on the gain clock signal RX2_CK44 and sends it to the data channel RX2_CH41 of the die 420. In step S660, the data channel RX2_CH41 of the die 420 samples the DDR data signal RX2_DI41 from the data interconnect CONN41 based on the triggering of the gain clock signal RX2_CK44 and the delay clock signal RX2_CK45, so as to output the SDR data signals RX2_DO41 and RX2_DO42 to the core circuit CORE42.

[0050] In some embodiments, the operation method further includes: generating a gain clock signal TX2_CK44 from the clock tree circuit TX2_CT41 of the die 420 based on the delayed clock signal RX2_CK43 and sending it to the data channel TX2_CH41 of the die 420; and outputting a data signal TX2_DO41 from the data channel TX2_CH41 to the data interconnect CONN44 of the package interconnect portion 430 based on the triggering of the gain clock signal TX2_CK44.

[0051] In some embodiments, the operation method further includes: generating a gain clock signal RX1_CK43 from the clock tree circuit RX1_CT41 of the die 410 based on the source clock signal TX1_CK42 and providing it to the data channel RX1_CH41 of the die 410; and generating a delay clock signal RX1_CK44 from the controllable delay line RX1_DL41 based on the gain clock signal RX1_CK43 and providing it to the data channel RX1_CH41.

[0052] In some embodiments, the operation method further includes: detecting the phase difference between the gained clock signal TX1_CK43 and the gained clock signal RX2_CK44 by the phase detector RX2_PD41 of the die 420; and adjusting the delay amount of the delayed clock signal RX2_CK43 by the controllable delay line RX2_DL41 in response to the phase difference.

[0053] In some embodiments, the operation method further includes: detecting a second phase difference between the gained clock signal RX2_CK44 and the delayed clock signal RX2_CK45 by the phase detector RX2_PD42; and adjusting the delay amount of the delayed clock signal RX2_CK45 by the controllable delay line RX2_DL42 in response to the second phase difference.

[0054] In some embodiments, the operation method further includes: delaying the source clock signal TX1_CK41 by the controllable delay line TX1_DL41 of the die 410 to generate a source clock signal TX1_CK42 and feeding it to the clock tree circuit TX1_CT41 and the clock interconnect CONN43.

[0055] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0056] Figure 1A is a cross-sectional schematic diagram of a three-dimensional structure of a semiconductor device according to one embodiment. Figure 1B is a cross-sectional schematic diagram of a three-dimensional structure of a semiconductor device according to another embodiment. Figure 1C is a cross-sectional schematic diagram of a 2.5-dimensional package structure of a semiconductor device according to yet another embodiment. Figure 1D is a cross-sectional schematic diagram of a 2.5-dimensional package structure of a semiconductor device according to yet another embodiment. Figure 2 is a circuit block schematic diagram of a semiconductor device according to one embodiment. Figure 3 is a timing diagram of data signals and clock signals according to one embodiment. Figure 4 is a circuit block schematic diagram of a semiconductor device according to one embodiment of the present invention. Figure 5 is a timing diagram of data signals and clock signals according to another embodiment of the present invention. Figure 6 is a flowchart illustrating an operation method of a semiconductor device according to one embodiment of the present invention.

Claims

1. A semiconductor device, comprising: A first die includes a first clock tree circuit and a first data channel, wherein an output terminal of the first clock tree circuit is coupled to a trigger terminal of the first data channel, and the first clock tree circuit generates a first amplified clock signal to the first data channel based on a first source clock signal; an internal interconnect portion includes a first clock interconnect and a first data interconnect, wherein a first terminal of the first clock interconnect is coupled to the first die to receive the first source clock signal, and a first terminal of the first data interconnect is coupled to an output terminal of the first data channel of the first die; The first and second chips are arranged in the same package. An input terminal of the first controllable delay line is coupled to a second terminal of the first clock interconnect to receive the first source clock signal of the first chip. An input terminal of the second clock tree circuit is coupled to the first controllable delay line to receive a first delayed clock signal. An output terminal of the second clock tree circuit is coupled to an input terminal of the second controllable delay line and a first trigger terminal of the second data channel to provide a second gained clock signal. An output terminal of the second controllable delay line is coupled to a second trigger terminal of the second data channel to provide a second delayed clock signal. An input terminal of the second data channel is coupled to a second terminal of the first data interconnect.

2. The semiconductor device as claimed in claim 1, wherein the in-package interconnects include an interposer or a bridging chip in a 2.5D package.

3. The semiconductor device of claim 1, wherein the interconnect portion of the package includes a silicon through-hole or a bump in a three-dimensional structure.

4. The semiconductor device as claimed in claim 1, wherein the package interconnect further includes a second data interconnect, and the second die further includes: A third clock tree circuit, wherein an input terminal of the third clock tree circuit is coupled to the first controllable delay line to receive the first delayed clock signal; And a third data channel, wherein an output terminal of the third clock tree circuit is coupled to a trigger terminal of the third data channel, the third clock tree circuit generates a third gain clock signal to the third data channel, and an output terminal of the third data channel is coupled to a first terminal of the second data interconnect.

5. The semiconductor device as claimed in claim 4, wherein the first die further comprises: A fourth clock tree circuit, wherein the fourth clock tree circuit generates a fourth amplified clock signal based on the first source clock signal; a third controllable delay line, wherein an input of the third controllable delay line is coupled to an output of the fourth clock tree circuit to receive the fourth amplified clock signal; And a fourth data channel, wherein a first trigger terminal of the fourth data channel is coupled to an output terminal of the third controllable delay line to receive a third delayed clock signal, a second trigger terminal of the fourth data channel is coupled to the output terminal of the fourth clock tree circuit to receive the fourth gained clock signal, and an input terminal of the fourth data channel is coupled to a second terminal of the second data interconnect.

6. The semiconductor device as claimed in claim 5, wherein the fourth data channel comprises: A first flip-flop, wherein an input terminal of the first flip-flop is coupled to the input terminal of the fourth data channel, and a trigger terminal of the first flip-flop is coupled to the first trigger terminal of the fourth data channel; And a second flip-flop, wherein an input terminal of the second flip-flop is coupled to the input terminal of the fourth data channel, and a trigger terminal of the second flip-flop is coupled to the second trigger terminal of the fourth data channel.

7. The semiconductor device of claim 1, wherein the in-package interconnect further includes a second clock interconnect, a first end of the second clock interconnect being coupled to the first die to receive the first gain-adjusted clock signal, and the second die further includes: A first phase detector, wherein a first input terminal of the first phase detector is coupled to a second terminal of the second clock interconnect to receive the first gained clock signal of the first die, and a second input terminal of the first phase detector is coupled to the second clock tree circuit to receive the second gained clock signal. The first phase detector detects a first phase difference between the first gained clock signal and the second gained clock signal, and a first controllable delay line adjusts a delay amount of the first delayed clock signal in response to the first phase difference.

8. The semiconductor device as claimed in claim 7, wherein the second die further comprises: A second phase detector, wherein a first input of the second phase detector is coupled to the output of the second clock tree circuit to receive the second gained clock signal, and a second input of the second phase detector is coupled to the output of the second controllable delay line to receive the second delayed clock signal, the second phase detector detects a second phase difference between the second gained clock signal and the second delayed clock signal, and the second controllable delay line adjusts a delay amount of the second delayed clock signal in response to the second phase difference.

9. The semiconductor device as claimed in claim 1, wherein the first die further comprises: A third controllable delay line, wherein an input terminal of the third controllable delay line receives a second source clock signal from the first die, and the third controllable delay line delays the second source clock signal to generate the first source clock signal for the first clock tree circuit and the first clock interconnect.

10. The semiconductor device of claim 1, wherein the second data channel comprises: A first flip-flop, wherein an input terminal of the first flip-flop is coupled to the input terminal of the second data channel, and a trigger terminal of the first flip-flop is coupled to the first trigger terminal of the second data channel; And a second flip-flop, wherein an input terminal of the second flip-flop is coupled to the input terminal of the second data channel, and a trigger terminal of the second flip-flop is coupled to the second trigger terminal of the second data channel.

11. A method of operating a semiconductor device, comprising: A first clock tree circuit of a first die in the semiconductor device generates a first amplified clock signal based on a first source clock signal and sends it to a first data channel of the first die. An output terminal of the first clock tree circuit is coupled to a trigger terminal of the first data channel. The first data channel, triggered by the first amplified clock signal, outputs a first data signal to a first data interconnect in a package interconnect portion of the semiconductor device. A first terminal of the first data interconnect is coupled to the first die's first data interconnect. An output terminal of a data channel and a first terminal of a first clock interconnect in the package interconnect are coupled to the first die to receive the first source clock signal; the first source clock signal from the first clock interconnect is delayed by a first controllable delay line of a second die of the semiconductor device to generate a first delayed clock signal, wherein the first die and the second die are arranged in the same package, and an input terminal of the first controllable delay line is coupled to a second terminal of the first clock interconnect to receive the first source clock signal. The first source clock signal of the second die; a second clock tree circuit of the second die generates a second gain clock signal based on the first delayed clock signal and provides it to a second data channel of the second die, wherein an input terminal of the second clock tree circuit is coupled to the first controllable delay line to receive the first delayed clock signal, and an output terminal of the second clock tree circuit is coupled to an input terminal of the second controllable delay line of the second die and a first trigger terminal of the second data channel to provide the second gain clock signal; The second controllable delay line generates a second delayed clock signal to the second data channel based on the second gained clock signal, wherein an output terminal of the second controllable delay line is coupled to a second trigger terminal of the second data channel to provide the second delayed clock signal; and the second data channel samples the first data signal from the first data interconnect based on the triggering of the second gained clock signal and the second delayed clock signal, wherein an input terminal of the second data channel is coupled to a second terminal of the first data interconnect.

12. The method of operation as described in claim 11, wherein the interconnect portion of the package includes an interposer or a bridging chip in a 2.5D package.

13. The method of operation as described in claim 11, wherein the internal interconnect portion of the package includes a silicon through-hole or a bump in a three-dimensional structure.

14. The operating method as described in claim 11 further includes: A third clock tree circuit of the second die generates a third gain clock signal based on the first delayed clock signal and sends it to a third data channel of the second die. An input terminal of the third clock tree circuit is coupled to the first controllable delay line to receive the first delayed clock signal, and an output terminal of the third clock tree circuit is coupled to a trigger terminal of the third data channel. And a second data signal is output by the third data channel based on the triggering of the third gain clock signal to a second data interconnect in the package interconnect, wherein an output terminal of the third data channel is coupled to a first terminal of the second data interconnect.

15. The operating method as described in claim 14 further includes: A fourth clock tree circuit of the first die generates a fourth amplified clock signal based on the first source clock signal and sends it to a fourth data channel of the first die. An input terminal of a third controllable delay line of the first die is coupled to an output terminal of the fourth clock tree circuit to receive the fourth amplified clock signal. The third controllable delay line generates a third delayed clock signal based on the fourth amplified clock signal and sends it to the fourth data channel. A first trigger terminal of the fourth data channel is coupled to an output terminal of the third controllable delay line to receive the third delayed clock signal. A second trigger terminal of the fourth data channel is coupled to the output terminal of the fourth clock tree circuit to receive the fourth amplified clock signal. An input terminal of the fourth data channel is coupled to a second terminal of the second data interconnect.

16. The operating method as described in claim 11 further includes: A first phase detector of the second die detects a first phase difference between the first gained clock signal and the second gained clock signal, wherein a first end of a second clock interconnect in the package interconnect is coupled to the first die to receive the first gained clock signal, a first input of the first phase detector is coupled to a second end of the second clock interconnect to receive the first gained clock signal of the first die, and a second input of the first phase detector is coupled to the second clock tree circuit to receive the second gained clock signal; and a first controllable delay line adjusts a delay amount of the first delayed clock signal in response to the first phase difference.

17. The operating method as described in claim 16 further includes: A second phase detector of the second die detects a second phase difference between the second gained clock signal and the second delayed clock signal, wherein a first input of the second phase detector is coupled to the output of the second clock tree circuit to receive the second gained clock signal, and a second input of the second phase detector is coupled to the output of the second controllable delay line to receive the second delayed clock signal; and the second controllable delay line adjusts a delay amount of the second delayed clock signal in response to the second phase difference.

18. The operating method as described in claim 11 further includes: A second source clock signal is delayed by a third controllable delay line of the first die to generate the first source clock signal, which is then fed to the first clock tree circuit and the first clock interconnect.

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