Signal sampling device and signal sampling method
Patent Information
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- REALTEK SEMICON CORP
- Filing Date
- 2025-01-23
- Publication Date
- 2026-08-01
AI Technical Summary
Analog-to-digital converters (ADCs) face challenges in reducing backlash noise and circuit costs due to the use of high-performance switches and series-coupled buffer circuits, which degrade performance and increase circuit area and cost.
Implementing a signal sampling device with parallel buffer circuits, where a high-specification buffer circuit generates a primary signal path and a lower-specification buffer circuit generates a secondary path, using a bootstrap switch circuit to maintain a fixed voltage difference and reduce noise impact.
This approach improves signal sampling accuracy and reduces circuit costs by maintaining a stable voltage difference and minimizing noise interference, while reducing circuit area and cost.
Smart Images
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Abstract
Description
[Technical Field]
[0001] This case relates to signal sampling devices, and in particular to signal sampling devices and methods that can reduce noise effects and reduce circuit costs. [Previous Technology]
[0002] Analog-to-digital converters (ADCs) require sampling circuits to sample the analog signal to be quantized. Therefore, the performance of the sampling circuit directly affects the signal quality generated by the ADC. To improve the performance of the sampling circuit, some related technologies use high-performance switches to implement the sampling circuit. However, the auxiliary circuitry of this switch may generate backlash noise during signal sampling. To reduce the impact of backlash noise, these related technologies use high-specification buffer circuits or several series-coupled buffer circuits, resulting in a significant increase in circuit area or cost. Furthermore, using several series-coupled buffer circuits may also reduce the performance of the switch. [Summary of the Invention]
[0003] In some embodiments, one of the objectives of this invention is (but not limited to) to provide a signal sampling device and signal sampling method that can reduce noise impact and reduce circuit costs, thereby improving the shortcomings of the prior art.
[0004] In some embodiments, the signal sampling device includes a first buffer circuit, a second buffer circuit, and a first bootie switch circuit. The first buffer circuit is used to generate a first buffer signal based on an input signal. The second buffer circuit is used to generate a second buffer signal based on the input signal, wherein the specifications of the second buffer circuit are lower than those of the first buffer circuit. The first bootie switch circuit is used to generate a control voltage based on the second buffer signal and to sample the first buffer signal based on the control voltage to generate a first sampled signal.
[0005] In some embodiments, the signal sampling method includes the following operations: generating a first buffer signal by means of a first buffer circuit based on an input signal; generating a second buffer signal by means of a second buffer circuit based on the input signal, wherein the specifications of the second buffer circuit are lower than those of the first buffer circuit; and generating a control voltage by means of a first bootie switch circuit based on the second buffer signal, and sampling the first buffer signal based on the control voltage to generate a first sampling signal.
[0006] Regarding the features, implementation and effects of this case, the preferred embodiments are described in detail below with reference to the drawings.
Implementation Method
[0007] All terms used herein have their common meanings. The definitions of the above terms in commonly used dictionaries, and any examples of the use of any term discussed herein, are merely illustrative and should not limit the scope or meaning of this application. Similarly, this application is not limited to the various embodiments shown in this specification.
[0008] The terms "coupled" or "connected" as used herein can refer to two or more components making direct physical or electrical contact with each other, or making indirect physical or electrical contact with each other, or two or more components operating or moving together. As used herein, the term "circuit" can refer to a device in which at least one transistor and / or at least one active or passive component are connected in a certain manner to process signals.
[0009] As used herein, the term "and / or" includes any combination of one or more of the listed related items. In this document, the terms first, second, third, etc., are used to describe and identify individual elements. Therefore, a first element in this document may also be referred to as a second element without departing from the intent of this document. For ease of understanding, similar elements in the various figures will be designated with the same reference numerals.
[0010] Figure 1 is a schematic diagram of a signal sampling device 100 according to some embodiments of the present invention. In some embodiments, the signal sampling device 100 may include a buffer circuit 110, a buffer circuit 120, and a bootstrap (or self-bootstrapping) switching circuit 130. The buffer circuit 110 is used to generate a buffer signal VB1 based on the input signal VIN. The buffer circuit 120 is used to generate a buffer signal VB2 based on the input signal VIN. The bootstrap switching circuit 130 is used to generate a control voltage VC1 based on the buffer signal VB2, and to sample the buffer signal VB1 based on the control voltage VC1, thereby generating a sampled signal VS1.
[0011] In detail, the bootie switch circuit 130 may include a bootie capacitor circuit 132 and a sampling circuit 134. The bootie capacitor circuit 132 may include a plurality of switches (not shown) and at least one capacitor (not shown), wherein the plurality of switches may be switched according to one or more clock signals (not shown) to charge and / or discharge the at least one capacitor using the buffer signal VB2, thereby generating a control voltage VC1 via the at least one capacitor, i.e., generating a control voltage VC1 according to the buffer signal VB2. In some embodiments, during the period when the bootie switch circuit 130 samples the buffer signal VB1, the bootie switch circuit 130 may maintain a voltage difference between the control voltage VC1 and the buffer signal VB1. In other words, during this period, there is a fixed voltage difference between the control voltage VC1 and the buffer signal VB1 (the difference may be, but is not limited to, the power supply voltage VDD shown in FIG. 3, FIG. 4A or FIG. 4B). In this way, the switch SW in the sampling circuit 134, controlled by the control voltage VC1, can have a more stable (or fixed) on-resistance value during the sampling period of the buffered signal VB1, thereby improving the overall linearity and accuracy, and thus improving the accuracy of signal sampling. The sampling circuit 134 samples the buffered signal VB1 based on the control voltage VC1 and generates the sampling signal VS1 accordingly. For example, the sampling circuit 134 may include a switch SW and a capacitor C. The switch SW can be controlled by the control voltage VC1, and the capacitor C can store the buffered signal VB1 when the switch SW is on, and generate the sampling signal VS1 accordingly. The detailed circuit arrangement of the bootie switch circuit 130 is understandable to those skilled in the art, and therefore will not be described in detail here.
[0012] In some embodiments, the specifications of the buffer circuit 120 may be lower than those of the buffer circuit 110. For example, the aforementioned specifications may include, but are not limited to, bandwidth, linearity, area, current consumption, rated voltage, etc. For instance, the bandwidth of the buffer circuit 120 is lower than that of the buffer circuit 110. The linearity of the buffer circuit 120 is lower than that of the buffer circuit 110. The area of the buffer circuit 120 is lower than that of the buffer circuit 110. The current consumption of the buffer circuit 120 is lower than that of the buffer circuit 110. The rated voltage of the buffer circuit 120 is lower than that of the buffer circuit 110. As can be seen from Figure 1, the buffer signal VB2 generated by the buffer circuit 120 is mainly provided to the bootie switch circuit 130 to generate the control voltage VC1, while the buffer signal VB1 generated by the buffer circuit 110 is used to generate the sampling signal VS1. In other words, the signal path that generates the sampling signal VS1 based on the buffer signal VB1 is the main path for generating the sampling signal VS1 in the signal sampling device 100, while the signal path that generates the control voltage VC1 based on the buffer signal VB2 is a relatively secondary path. Since the main path is used to generate the high-resolution sampling signal VS1, if the main path is affected by kickback noise, the quality of the sampling signal VS1 will be significantly reduced and difficult to recover. Therefore, by setting up another secondary path, a higher-specification buffer circuit 110 is configured for the aforementioned main path, and a lower-specification buffer circuit 120 is configured for the aforementioned secondary path. In this way, the performance of the main path can be improved (e.g., to improve the resolution, linearity, etc. of the sampling signal VS1) while reducing the overall circuit area and cost. By setting up the buffer circuit 120, the impact of kickback noise generated by the bootie switch circuit 130 can be further reduced, thereby improving the overall performance.
[0013] In some related technologies, signal sampling devices use multiple buffer circuits connected in series. A first buffer circuit generates a first signal based on an input signal, and a second buffer circuit generates a second signal based on the first signal. A bootie switch circuit in the signal sampling device generates a control voltage based on the second signal and samples the first signal based on the control voltage. In the above-mentioned technology, because the multiple buffer circuits are connected in series, a certain phase error will occur between the first and second signals, making it impossible for the control voltage to accurately maintain a constant voltage difference between the control voltage and the first signal. This will reduce the efficiency of the signal sampling device in this technology. Furthermore, because the multiple buffers are connected in series, the backlash noise generated by the bootie switch circuit may affect the first buffer circuit via the second buffer circuit, resulting in a deterioration in overall efficiency. Moreover, because the multiple buffers are connected in series, the first buffer circuit needs to drive both the sampling circuit and the second buffer circuit, which increases the specifications (e.g., current drive capability) of the first buffer circuit. This will significantly increase the overall circuit cost.
[0014] Compared to the above-described technology, in some embodiments of this invention, by setting two parallel buffer circuits 110 and 120, the circuit specification requirements can be reduced while avoiding phase errors, so as to more accurately maintain the aforementioned fixed voltage difference. In this way, the overall circuit performance can be maintained while reducing circuit costs.
[0015] Figure 2 is a schematic diagram of a signal sampling device 200 according to some embodiments of the present invention. Compared to Figure 1, the signal sampling device 200 further includes a bootie switch circuit 230. The bootie switch circuit 230 can generate a control voltage VC2 based on a buffer signal VB2, and sample the buffer signal VB1 based on the control voltage VC2 to generate a sampled signal VS2. In this example, the signal sampling device 200 can be applied to a time-interleaved analog-to-digital converter. For example, the bootie switch circuit 130 can correspond to channel CH1 of this time-interleaved analog-to-digital converter, and the bootie switch circuit 230 can correspond to channel CH2 of this time-interleaved analog-to-digital converter. In other words, the bootie switch circuit 130 and the bootie switch circuit 230 can sequentially sample the buffer signal VB1 to sequentially generate sampled signals VS1 and VS2. Similarly, by setting up parallel buffer circuits 110 and 120, backlash noise or signal disturbances from different channels can be prevented from affecting the buffer circuit 110 that processes the main path, thereby improving the signal quality of sampling signals VS1 and VS2.
[0016] It should be understood that the circuit configurations in Figures 1 and 2 are examples of single-ended signal applications, but this invention is not limited thereto. In other embodiments, the signal sampling device 100 and / or the signal sampling device 200 may be equipped with more buffer circuits and corresponding bootie switch circuits to suit differential signal applications. Therefore, this invention is not limited to the circuit configurations and number of circuits shown in Figures 1 and 2.
[0017] Figure 3 is a schematic diagram of the buffer circuit 120 in Figure 1 or Figure 2 according to some embodiments of this invention. In some embodiments, the buffer circuit 120 is an analog buffer circuit, such as a source follower circuit. For example, the buffer circuit 120 includes transistor MP1 and transistor MP2. The first terminal of transistor MP1 (e.g., the source) receives the power supply voltage VDD, the second terminal of transistor MP1 (e.g., the drain) is coupled to the output node NO, and the control terminal of transistor MP1 (e.g., the gate) receives the reference voltage VREF. The first terminal of transistor MP2 is coupled to the second terminal of transistor MP1 to the output node NO and outputs a buffer signal VB2, the second terminal of transistor MP2 receives the power supply voltage VSS, and the control terminal of transistor MP2 receives the input signal VIN. With the above configuration, transistor MP1 can operate as a current source to drive transistor MP2 according to the reference voltage VREF and the power supply voltage VDD, and transistor MP2 can generate the buffer signal VB2 according to the input signal VIN.
[0018] Figure 4A is a schematic diagram of the buffer circuit 110 in Figure 1 or Figure 2 according to some embodiments of this invention. In some embodiments, the buffer circuit 110 may also be an analog buffer circuit, such as a source follower circuit. Compared to the buffer circuit 120 in Figure 3, the buffer circuit 110 further includes a transistor MP3. The transistor MP1 operates as a current source based on the reference voltage VREF and the power supply voltage VDD. The transistors MP2 and MP3 are connected in series and coupled to the output node NO along with the transistor MP1. Specifically, in this example, the first terminal of the transistor MP2 is used to output the buffer signal VB1, and the second terminal of the transistor MP2 is coupled to the first terminal of the transistor MP3. The second terminal of the transistor MP3 receives the power supply voltage VSS, and the control terminal of the transistor MP3 receives the input signal VIN. Thus, the transistors MP2 and MP3 can generate the buffer signal VB1 according to the input signal VIN. Compared to the setup in Figure 3, the linearity of the buffer circuit 110 can be further improved by setting the transistor MP3.
[0019] Figure 4B is a schematic diagram of a buffer 400 according to some embodiments of this invention. In some embodiments, if the current application has low requirements for noise performance, the buffer circuit 110 and buffer circuit 120 of Figure 1 or Figure 2 can be integrated into a single buffer. For example, the aforementioned buffer circuit 110 and buffer circuit 120 can be implemented as the buffer 400 of Figure 4B to jointly generate buffer signals VB1 and VB2, wherein transistor MP2 is coupled between transistor MP1 and transistor MP3, and transistor MP3 is used to generate buffer signal VB2 according to the input signal VIN. The circuit arrangement in Figure 4B is roughly the same as that in Figure 4A, so it will not be described again.
[0020] In Figure 4A or Figure 4B, the levels of the first, second, and control terminals of transistor MP2 vary with the input signal VIN. Therefore, the voltage difference between these terminals is relatively fixed, resulting in relatively good linearity for transistor MP2, thus generating a buffer signal VB1 with high linearity. Conversely, since the second terminal of transistor MP3 receives the power supply voltage VSS, it has a fixed level, causing the voltage difference between its terminals to vary less. Under these conditions, transistor MP3 has relatively low linearity, resulting in lower linearity for the buffer signal VB2 (relative to the buffer signal VB1). On the other hand, although transistors MP1, MP2, and MP3 are located on the same path, since transistor MP2 is coupled between transistors MP1 and MP3 (i.e., located between the node used to output buffered signal VB1 (e.g., output node NO) and the node used to output buffered signal VB2 (e.g., the second end of transistor MP2)), transistor MP2 can provide a certain buffering effect for buffered signals VB1 and VB2 to reduce the impact of backflash noise.
[0021] In some other embodiments, the output node NO can be used to output the buffered signal VB2, and the second terminal of the transistor MP2 can be used to output the buffered signal VB1. Various circuit configurations used to generate the corresponding buffered signals VB1 and VB2 are within the scope of this invention. In the examples of Figures 3, 4A, and 4B, each of the plurality of transistors MP1, MP2, and MP3 can be a P-type transistor. In other examples, the circuit configurations of Figures 3, 4A, and 4B can be implemented using transistors with other conductivity types. Therefore, the above-described configurations of the buffer circuits 110, 120, and / or 400 are merely examples, and this invention is not limited thereto.
[0022] Figure 5 is a flowchart of a signal sampling method 500 according to some embodiments of this invention. In operation S510, a first buffer circuit generates a first buffer signal based on an input signal. In operation S520, a second buffer circuit generates a second buffer signal based on the input signal, wherein the specifications of the second buffer circuit are lower than those of the first buffer circuit. In operation S530, a first bootie switch circuit generates a control voltage based on the second buffer signal, and samples the first buffer signal based on the control voltage to generate a first sampling signal.
[0023] The relevant operations of the signal sampling method 500 can be referred to the descriptions of the foregoing embodiments, and therefore will not be repeated here. The various operations in the signal sampling method 500 are merely examples and are not limited to being performed in the order shown in these examples. Without departing from the operation mode and scope of the embodiments of this application, the relevant operations in the signal sampling method 500 may be appropriately added, replaced, omitted, or performed in a different order. Alternatively, the relevant operations in the above figures may be performed simultaneously or partially simultaneously.
[0024] In summary, the signal sampling apparatus and signal sampling method provided in some embodiments of this case can reduce the overall circuit cost and improve the quality of the sampled signal at the same time by using multiple parallel buffer circuits.
[0025] Although the embodiments of this case are described above, these embodiments are not intended to limit this case. Those skilled in the art can make changes to the technical features of this case based on the express or implied content of this case. All such changes may fall within the scope of patent protection sought in this case. In other words, the scope of patent protection of this case shall be determined by the scope of the patent application in this specification. [Simplified Explanation of the Diagram]
[0026] [Figure 1] is a schematic diagram of a signal sampling device according to some embodiments of the present invention; [Figure 2] is a schematic diagram of a signal sampling device according to some embodiments of the present invention; [Figure 3] is a schematic diagram of a buffer circuit in Figure 1 or Figure 2 according to some embodiments of the present invention; [Figure 4A] is a schematic diagram of a buffer circuit in Figure 1 or Figure 2 according to some embodiments of the present invention; [Figure 4B] is a schematic diagram of a buffer according to some embodiments of the present invention; and [Figure 5] is a flowchart of a signal sampling method according to some embodiments of the present invention.
Claims
1. A signal sampling device, comprising: a first buffer circuit for generating a first buffer signal based on an input signal; a second buffer circuit for generating a second buffer signal based on the input signal, wherein the specifications of the second buffer circuit are lower than those of the first buffer circuit; a first bootie switch circuit for generating a first control voltage based on the second buffer signal and sampling the first buffer signal based on the first control voltage to generate a first sampling signal; and a second bootie switch circuit for generating a second control voltage based on the second buffer signal and sampling the first buffer signal based on the second control voltage to generate a second sampling signal.
2. The signal sampling device of claim 1, wherein the first bootie switch circuit corresponds to a first channel of a time-interleaved analog-to-digital converter, and the second bootie switch circuit corresponds to a second channel of the time-interleaved analog-to-digital converter.
3. The signal sampling device of claim 1, wherein the first buffer circuit and the second buffer circuit are integrated into a buffer, and the buffer includes: a first transistor for operating as a current source according to a reference voltage and a power supply voltage; a second transistor for generating the second buffer signal according to the input signal; and a third transistor coupled between the first transistor and the second transistor for generating the first buffer signal according to the input signal, wherein the first transistor, the third transistor and the second transistor are connected in series and have the same conductivity type.
4. The signal sampling device of claim 1, wherein the bandwidth of the second buffer circuit is lower than the bandwidth of the first buffer circuit.
5. The signal sampling device of claim 1, wherein the linearity of the second buffer circuit is lower than that of the first buffer circuit.
6. The signal sampling device of claim 1, wherein the area of the second buffer circuit is smaller than the area of the first buffer circuit.
7. The signal sampling apparatus of claim 1, wherein the second buffer circuit comprises: a first transistor for operating as a current source according to a reference voltage and a power supply voltage; and a second transistor coupled to the first transistor to an output node and for generating the second buffer signal according to the input signal.
8. The signal sampling apparatus of claim 1, wherein the first buffer circuit comprises: a first transistor for operating as a current source according to a reference voltage and a power supply voltage; and a plurality of second transistors connected in series and coupled to the first transistor to an output node for generating the first buffer signal according to the input signal.
9. A signal sampling method, comprising: generating a first buffer signal based on an input signal using a first buffer circuit; generating a second buffer signal based on the input signal using a second buffer circuit, wherein the specifications of the second buffer circuit are lower than those of the first buffer circuit; generating a first control voltage based on the second buffer signal using a first bootstrap switch circuit, and sampling the first buffer signal based on the first control voltage to generate a first sampling signal; and generating a second control voltage based on the second buffer signal using a second bootstrap switch circuit, and sampling the first buffer signal based on the second control voltage to generate a second sampling signal.