Front-end circuitry and signal conversion method
Patent Information
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- REALTEK SEMICON CORP
- Filing Date
- 2025-01-23
- Publication Date
- 2026-08-01
AI Technical Summary
Existing analog-to-digital converters (ADCs) suffer from kickback noise due to switching operations in sampling circuits, comparators, and capacitor arrays, which degrade output signal quality, particularly in high-speed or high-precision converters.
A front-end circuit system utilizing buffer circuits to isolate switching noise, comprising a first buffer circuit, switches, analog-to-digital and digital-to-analog converters, and a subtractor circuit to generate and subtract feedback signals, thereby reducing noise impact.
The system improves output signal quality by minimizing noise interference from switching operations, reducing circuit area, power consumption, and cost while maintaining acceptable error tolerance.
Smart Images
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Abstract
Description
[Technical Field]
[0001] This case relates to front-end circuit systems, and in particular to front-end circuit systems and signal conversion methods that can utilize buffer circuits to reduce the impact of noise. [Previous Technology]
[0002] In existing analog-to-digital converters (ADCs), circuits such as sampling circuits, comparators, and / or capacitor arrays typically involve multiple switching operations. These switching operations can cause kickback noise, which can have unintended effects on the input signal, ultimately leading to a degraded output signal quality. Specifically, kickback noise is mainly caused by instantaneous voltage or current changes within the circuitry due to the switching operations. If these changes couple to the signal input, they will degrade the input signal quality, ultimately resulting in a degraded output signal quality. This phenomenon is more pronounced in high-speed or high-precision analog-to-digital converters. [Summary of the Invention]
[0003] In some embodiments, one of the objectives of this invention is (but not limited to) to provide a front-end circuit system and signal conversion method that can utilize buffer circuits to reduce the impact of noise, thereby improving the shortcomings of the prior art.
[0004] In some embodiments, the front-end circuit system includes a first buffer circuit, a first switch, an analog-to-digital converter circuit, a digital-to-analog converter circuit, a second switch, and a subtractor circuit. The first buffer circuit generates a first buffer signal based on an input signal. The first switch is turned on according to a control signal to output the first buffer signal as a first signal. The analog-to-digital converter circuit generates a digit code based on the first signal. The digital-to-analog converter circuit generates a feedback signal based on the digit code. The second switch is turned on according to the control signal to output a second signal based on the input signal. The subtractor circuit subtracts the feedback signal from the second signal to generate an output signal.
[0005] In some embodiments, the signal conversion method includes the following operations: generating a first buffer signal by a first buffer circuit based on an input signal; turning on a first switch according to a control signal to output the first buffer signal as a first signal via the first switch; generating a digit code by an analog-to-digital converter circuit based on the first signal; generating a feedback signal by a digital-to-analog converter circuit based on the digit code; turning on a second switch according to the control signal to output a second signal via the second switch based on the input signal; and subtracting the feedback signal from the second signal by a subtractor circuit to generate an output signal.
[0006] Regarding the features, implementation and effects of this case, the preferred embodiments are described in detail below with reference to the drawings.
Implementation Method
[0007] All terms used herein have their common meanings. The definitions of the above terms in commonly used dictionaries, and any examples of the use of any term discussed herein, are merely illustrative and should not limit the scope or meaning of this application. Similarly, this application is not limited to the various embodiments shown in this specification.
[0008] The terms "coupled" or "connected" as used herein can refer to two or more components making direct physical or electrical contact with each other, or making indirect physical or electrical contact with each other, or two or more components operating or moving together. As used herein, the term "circuit" can refer to a device in which at least one transistor and / or at least one active or passive component are connected in a certain manner to process signals.
[0009] As used herein, the term "and / or" includes any combination of one or more of the listed related items. In this document, the terms first, second, third, etc., are used to describe and identify individual elements. Therefore, a first element in this document may also be referred to as a second element without departing from the intent of this document. For ease of understanding, similar elements in the various figures will be designated with the same reference numerals.
[0010] Figure 1 is a schematic diagram of a front-end circuit system 100 according to some embodiments of the present invention. In different embodiments, the front-end circuit system 100 can be applied to various types of analog-to-digital converters and / or digital-to-analog converters. For example, the front-end circuit system 100 can be applied to, but is not limited to, multiplying digital-to-analog converters (MDACs) in pipelined analog-to-digital converters.
[0011] The front-end circuit system 100 includes a buffer circuit 110, a switch SW1, an analog-to-analog converter circuit 120, a digital-to-analog converter circuit 130, a switch SW2, and a subtractor circuit 140. The buffer circuit 110 generates a buffer signal VB1 based on the input signal VIN. The switch SW1 is turned on according to the control signal VC to output the buffer signal VB1 as a signal S1. The analog-to-digital converter circuit 120 generates a digital code SD based on the signal S1. In some embodiments, the analog-to-digital converter circuit 120 may be, but is not limited to, a flash analog-to-digital converter.
[0012] The digital-to-analog converter circuit 130 is used to generate a feedback signal FB based on the digital code SD. In some embodiments, the digital-to-analog converter circuit 130 may be, but is not limited to, a capacitive digital-to-analog converter. The capacitive digital-to-analog converter may include a capacitor array circuit (not shown) and a switching circuit (not shown), wherein the switching circuit is controlled by the digital code SD to switch the connection relationship in the capacitor array circuit to perform capacitor charging and discharging operations to generate the corresponding feedback signal FB. The switch SW2 is used to be turned on according to the control signal VC to output a signal S2 according to the input signal VIN. The subtractor circuit 140 is used to subtract the feedback signal FB from the signal S2 to generate an output signal SO.
[0013] As mentioned above, the analog-to-digital converter circuit 120 can be a flash analog-to-digital converter. Generally, a flash analog-to-digital converter may contain several comparators. In practical applications, the switching of these comparators and switch SW1 may cause kickback noise to the input signal VIN. By indirectly isolating switch SW1 through buffer circuit 110, the impact of kickback noise on the input signal VIN can be reduced. Furthermore, since the analog-to-digital converter circuit 120 typically has a certain error tolerance range, the phase difference caused by buffer circuit 110 to the input signal VIN can be adjusted to an acceptable range without affecting the original circuit operation. Therefore, by setting buffer circuit 110, the unexpected disturbances caused by analog-to-digital converter circuit 120 to the input signal VIN can be reduced, thereby improving the quality of digital code SD and output signal SO.
[0014] Figure 2 is a schematic diagram of a front-end circuit system 200 according to some embodiments of the present invention. Compared to the example in Figure 1, in this example, the front-end circuit system 200 further includes a buffer circuit 220. The buffer circuit 220 is used to generate a buffer signal VB2 according to the input signal VIN, and the switch SW2 is further used to turn on according to the control signal VC to output the buffer signal VB2 as the signal S2.
[0015] In some embodiments, the specifications of the buffer circuit 110 may be lower than those of the buffer circuit 220. In some embodiments, the aforementioned specifications include, but are not limited to, bandwidth, linearity, area, current consumption, rated voltage, etc. For example, the bandwidth of the buffer circuit 110 is lower than that of the buffer circuit 220. The linearity of the buffer circuit 110 is lower than that of the buffer circuit 220. The area of the buffer circuit 110 is lower than that of the buffer circuit 220. The current consumption of the buffer circuit 110 is lower than that of the buffer circuit 220. The rated voltage of the buffer circuit 110 is lower than that of the buffer circuit 220. In practical applications, the switching of the digital-to-analog converter circuit 130 and the switch SW2 may also cause backlash noise to the input signal VIN. Therefore, by setting the buffer circuit 220 to indirectly isolate the switch SW2, the impact of backlash noise from the digital-to-analog converter circuit 130 and the switch SW2 can be reduced. On the other hand, as mentioned earlier, since the analog-to-digital converter circuit 120 has a certain error tolerance range, it can accept the lower quality buffered signal VB1. Therefore, in terms of design considerations, the specifications of the buffer circuit 110 can be reduced to save circuit area, power consumption, and / or cost. At the same time, in order to effectively reduce the impact of backlash noise introduced by the switching of the digital-to-analog converter circuit 130 and switch SW2, a buffer circuit with higher specifications can be used to implement the buffer circuit 220, thereby further improving the quality of the output signal SO.
[0016] Figure 3A is a schematic diagram of the buffer circuit 110 in Figure 1 or Figure 2 according to some embodiments of this invention. In some embodiments, the buffer circuit 110 may be an analog buffer circuit, such as, but not limited to, a source follower circuit. For example, the buffer circuit 110 includes transistor MP1 and transistor MP2. A first terminal (e.g., the source) of transistor MP1 receives a power supply voltage VDD, a second terminal (e.g., the drain) of transistor MP1 is coupled to a first terminal of transistor MP2, and a control terminal (e.g., the gate) of transistor MP1 receives a reference voltage VREF. A first terminal of transistor MP2 outputs a buffer signal VB1, a second terminal of transistor MP2 receives a power supply voltage VSS, and a control terminal of transistor MP2 receives an input signal VIN. With the above configuration, transistor MP1 can be biased by the reference voltage VREF to operate as a current source to drive transistor MP2, and transistor MP2 can generate the buffer signal VB1 according to the input signal VIN.
[0017] Figure 3B is a schematic diagram of the buffer circuit 220 in Figure 2 according to some embodiments of this invention. In some embodiments, the buffer circuit 220 may be an analog buffer circuit, such as, but not limited to, a source follower circuit. Compared to the buffer circuit 110, the buffer circuit 220 further includes a transistor MP3. The transistor MP1 is biased via a reference voltage VREF. The transistors MP2 and MP3 are connected in series and coupled to the transistor MP1. Specifically, in this example, the first terminal of the transistor MP2 is used to output a buffered signal VB2, and the second terminal of the transistor MP2 is coupled to the first terminal of the transistor MP3. The second terminal of the transistor MP3 receives a power supply voltage VSS, and the control terminals of both the transistors MP2 and MP3 receive an input signal VIN. Thus, the transistors MP2 and MP3 can generate the buffered signal VB2 according to the input signal VIN. Compared to Figure 3A, in this example, since the levels of each terminal of transistor MP2 change with the input signal VIN, the voltage difference between the multiple terminals of transistor MP2 is relatively fixed. Therefore, the linearity of transistor MP2 can be improved, resulting in a buffer signal VB2 with better quality.
[0018] Figure 4 is a schematic diagram of a front-end circuit system 400 according to some embodiments of the present invention. Compared to the example in Figure 1, in this example, the buffer circuit 110 is further used to generate a buffer signal VB2 according to the input signal VIN, and the switch SW2 is further turned on according to the control signal VC to output the buffer signal VB2 as signal S2. In other words, in this example, the buffer circuit 110 can be used to generate the buffer signals VB1 and VB2 in Figure 2. Equivalently, the buffer circuit 110 and the buffer circuit 220 in Figure 2 can be integrated into the buffer circuit 110 in Figure 4.
[0019] Figure 5 is a schematic diagram of the buffer circuit 110 in Figure 4 according to some embodiments of this invention. Compared to Figure 3A, in this example, the buffer circuit 110 can generate a buffer signal VB2 based on the input signal VIN. Specifically, the buffer circuit 110 includes transistors MP1, MP2, and MP3. Transistor MP1 is biased via a reference voltage VREF. Transistor MP3 is used to generate the buffer signal VB1 based on the input signal. Transistor MP2 is coupled between transistors MP1 and MP3 and is used to generate the buffer signal VB2 based on the input signal VIN. In this example, although transistors MP1, MP2, and MP3 are located on the same path, since transistor MP2 is coupled between transistors MP1 and MP3 (i.e., located between the node of the output buffer signal VB1 and the node of the output buffer signal VB2), transistor MP2 can provide a certain buffering effect for the buffer signals VB1 and VB2 to reduce the influence of backlash noise.
[0020] In some other embodiments, the first terminal of transistor MP2 can be replaced with an output buffer signal VB1, and the second terminal of transistor MP2 can be replaced with an output buffer signal VB2. Various circuit configurations used to generate the corresponding buffer signals VB1 and VB2 are within the scope of this invention. In the examples of Figures 3A, 3B, and 5, each of the plurality of transistors MP1, MP2, and MP3 can be a P-type transistor. In other examples, the circuit configurations of Figures 3A, 3B, and 5 can be implemented using transistors with other conductivity types. Therefore, the above-described configurations of buffer circuit 110 and / or buffer circuit 220 are merely examples, and this invention is not limited thereto.
[0021] Figure 6 is a flowchart illustrating a signal conversion method 600 according to some embodiments of the present invention. In operation S610, a first buffer signal is generated by a first buffer circuit based on an input signal. In operation S620, a first switch is turned on according to a control signal, so that the first buffer signal is output as a first signal via the first switch. In operation S630, a digit code is generated by an analog-to-digital converter circuit based on the first signal. In operation S640, a feedback signal is generated by a digit-to-analog converter circuit based on the digit code. In operation S650, a second switch is turned on according to the control signal, so that a second signal is output via the second switch based on the input signal. In operation S660, the feedback signal is subtracted from the second signal by a subtractor circuit to generate an output signal.
[0022] The relevant operations of the signal conversion method 600 can be referred to the descriptions of the foregoing embodiments, and therefore will not be repeated here. The various operations in the signal conversion method 600 are merely examples and are not limited to being performed in the order shown in these examples. Without departing from the operation mode and scope of the embodiments of this application, the relevant operations in the signal conversion method 600 may be appropriately added, replaced, omitted, or performed in a different order. Alternatively, the relevant operations in the above figures may be performed simultaneously or partially simultaneously.
[0023] In summary, the front-end circuit system and signal conversion method provided in some embodiments of this case can reduce the impact of backflash noise by setting one or more buffer circuits, thereby reducing the overall circuit cost and improving the quality of the generated signal.
[0024] Although the embodiments of this case are described above, these embodiments are not intended to limit this case. Those skilled in the art can make changes to the technical features of this case based on the explicit or implicit content of this case. All such changes may fall within the scope of patent protection sought in this case. In other words, the scope of patent protection of this case shall be determined by the scope of the patent application in this specification. [Simplified Explanation of the Diagram]
[0025] [Figure 1] is a schematic diagram of a front-end circuit system according to some embodiments of the present invention; [Figure 2] is a schematic diagram of a front-end circuit system according to some embodiments of the present invention; [Figure 3A] is a schematic diagram of the buffer circuit in Figure 1 or Figure 2 according to some embodiments of the present invention; [Figure 3B] is a schematic diagram of the buffer circuit in Figure 2 according to some embodiments of the present invention; [Figure 4] is a schematic diagram of a front-end circuit system according to some embodiments of the present invention; [Figure 5] is a schematic diagram of the buffer circuit in Figure 4 according to some embodiments of the present invention; and [Figure 6] is a flowchart of a signal conversion method according to some embodiments of the present invention.
Claims
1. A front-end circuit system comprising: a first buffer circuit for generating a first buffer signal based on an input signal; a first switch for being turned on based on a control signal to output the first buffer signal as a first signal; an analog-to-digital converter circuit for generating a digit code based on the first signal; a digital-to-analog converter circuit for generating a feedback signal based on the digit code; a second switch for being turned on based on the control signal to output a second buffer signal as a second signal; and a subtractor circuit for subtracting the feedback signal from the second signal to generate an output signal, wherein... The second buffer signal is generated by the first buffer circuit based on the input signal, or the front-end circuit system further includes a second buffer circuit, which is used to generate the second buffer signal based on the input signal.
2. As in the front-end circuit system of request item 1, wherein the specifications of the first buffer circuit are lower than those of the second buffer circuit.
3. The front-end circuit system as requested in item 1, wherein the bandwidth of the first buffer circuit is lower than the bandwidth of the second buffer circuit.
4. The front-end circuit system as requested in item 1, wherein the linearity of the first buffer circuit is lower than that of the second buffer circuit.
5. The front-end circuit system as requested in claim 1, wherein the area of the first buffer circuit is smaller than the area of the second buffer circuit.
6. The front-end circuit system as claimed in claim 1, wherein the second buffer circuit comprises: a first transistor for biasing via a reference voltage; and a plurality of second transistors connected in series and coupled to the first transistor for generating the second buffer signal according to the input signal.
7. The front-end circuit system as claimed in claim 1, wherein the first buffer circuit comprises: a first transistor for biasing via a reference voltage; a second transistor for generating the first buffer signal according to the input signal; and a third transistor coupled between the first transistor and the second transistor for generating the second buffer signal according to the input signal.
8. A signal conversion method, comprising: generating a first buffer signal according to an input signal via a first buffer circuit; turning on a first switch according to a control signal to output the first buffer signal as a first signal via the first switch; generating a digit code according to the first signal via an analog-to-digital converter circuit; generating a feedback signal according to the digit code via a digital-to-analog converter circuit; generating a second buffer signal according to the input signal via the first buffer circuit or a second buffer circuit; turning on a second switch according to the control signal to output the second buffer signal as a second signal via the second switch; and subtracting the feedback signal from the second signal via a subtractor circuit to generate an output signal.