A serializer and a deserializer

Abstract

The present disclosure is related to a serializer and a deserializer. The serializer includes a serializing module and a data up-conversion processing module. The data up-conversion processing module receives a data packet sequence from a media access control block based on an output operating frequency and outputs the data packet sequence based on a serialization operation frequency. The deserializer includes a desequence module and a plurality of data down-conversion processing modules. The deserializer generates a data operating frequency based on the desequence operating frequency, and outputs a restored data packet sequence based on the data operating frequency. The present disclosure transmits or receives data in accordance with the operating frequency of the media access control block, and the data is exchanged at a transmission frequency that meets the transmission specification requirements of the physical layer. Thus, the purpose of improving the convenience of using a serializer and a deserializer is achieved.

Description

[Technical Field]

[0001] This application relates to a sequencer and a deserializer, and more particularly to a sequencer and a deserializer operable at high frequencies. [Previous Technology]

[0002] A sequencer / deserializer (SerDes) is a physical (PHY) layer element that can switch data between parallel communication mode and sequential communication mode, and enables high-speed transmission of large amounts of data between point-to-point using differential signals.

[0003] Generally, in applications, the sequencer / deserializer is directly connected to the Media Access Control (MAC) layer components (e.g., Field-Effect Programmable Gate Array (FPGA) chip). Since the operating frequency of the FPGA chip is relatively low (e.g., several hundred MHz), the sequencer / deserializer must operate at the lowest transmission frequency to match the operating frequency of the FPGA chip.

[0004] However, as the requirements for the transmission specifications of the physical layer increase, the transmission frequency requirements for the sequencer / deserializer also increase accordingly. Therefore, how to propose a sequencer / deserializer that is suitable for MAC layer components and meets the transmission specification requirements of the physical layer is one of the problems to be solved in this field. [Summary of the Invention]

[0005] In order to solve the above-mentioned technical problems, the present invention proposes a sequencer and a deserializer, which can transmit or receive data in conjunction with the operating frequency of the FPGA chip, and exchange data at a transmission frequency that meets the transmission specifications of the physical layer, thereby improving the convenience of the sequencer and deserializer in application.

[0006] To achieve one of the above objectives, the present invention provides a sequencer embodiment, which is a physical layer interface of an electronic device, comprising: a sequencer module and a data upsampling processing module. The sequencer module has a sequence operation frequency for converting parallel data packets into a serially transmitted data stream. The data upsampling processing module includes a frequency divider unit and a plurality of asynchronous register units. The frequency divider unit is electrically connected to a media access control block and the sequencer module, for receiving the sequence operation frequency and generating a device operation frequency based on the sequence operation frequency, the device operation frequency being provided to the media access control block, the device operation frequency being less than the sequence operation frequency. Each of the asynchronous register units is electrically connected to the Media Access Control (MAC) block and the sequence module. These asynchronous register units receive the sequence operation frequency and the output operation frequency from the MAC block. Based on the output operation frequency, these asynchronous register units receive a data packet sequence from the MAC block and output the data packet sequence based on the sequence operation frequency, where the output operation frequency is lower than the sequence operation frequency. The data packet sequence includes multiple non-repeating data packets, and the data stream includes repeated data packets.

[0007] To achieve one of the above objectives, the present invention provides a deserializer embodiment, which is a physical layer interface of an electronic device, including a deserialization module and a plurality of data downsampling processing modules. The deserialization module has a deserialization operation frequency for receiving serially transmitted data streams and converting the data streams into a sequence of parallel transmitted data packets, the data packet sequence including repeating data packets. Each data downsampling processing module includes a frequency division unit, an alignment unit, and a packet discarding unit. The frequency division unit is electrically connected to a media access control block and the deserialization module, for receiving the deserialization operation frequency and generating a data operation frequency based on the deserialization operation frequency, the data operation frequency being provided to the media access control block, the data operation frequency being less than the deserialization operation frequency. The alignment unit is electrically connected to the deserialization module for receiving the deserialization operation frequency and the data packet sequence from the deserialization module, the alignment unit being used to determine the start position of each data packet in the data packet sequence. The packet discarding unit is electrically connected to the alignment unit and the desequence module to receive the desequence operation frequency and the data packet sequence from the alignment unit, discard duplicate data packets in the data packet sequence, and output a restored data packet sequence, which includes non-repeating data packets.

[0008] Based on the above, the sequencer of the present invention can convert received low-frequency data into high-frequency data by upsampling through a data upsampling module, and the deserializer of the present invention downsampling the received high-frequency data into low-frequency data. Therefore, the sequencer / deserializer of the present invention can transmit or receive low-frequency data in accordance with the operating frequency of MAC layer components, and exchange data at a transmission frequency that meets the transmission specifications of the physical layer, thereby improving the convenience of sequencer and deserializer applications.

Implementation Method

[0009] Figure 1 is a block diagram illustrating an embodiment of electronic device 100. Electronic device 100 is, for example, a portable electronic device (e.g., a smartphone, tablet, etc.) or a non-portable electronic device (e.g., a desktop computer), such as a host device. Electronic device 100 is, for example, a data storage device or a flash storage device. For example, electronic device 100 is, for example, a solid-state disk (SSD) or flash memory. Generally, electronic device 100 includes a physical layer interface 110, an interface driver 120, and an application 130. Physical layer interface 110 is a physical circuit interface used to provide signals to external devices and receive signals from external devices. Physical layer interface 110 is, for example, a physical circuit conforming to the MIPI M-PHY™ physical layer specification. Physical layer interface 110 is, for example, a physical circuit conforming to the PCIe (Peripheral Component Interconnect Express) standard. The physical layer interface 110 is, for example, a physical circuit interface suitable for Universal Flash Storage (UFS). Interface driver 120 is electrically connected to the physical layer interface 110. Interface driver 120 is used to generate or decode data packets to perform tasks requested from application 130. In memory system applications, tasks include, for example, read operations, write operations, etc. Data packets generated by interface driver 120 are provided to physical layer interface 110 for transmission through physical layer interface 110. Interface driver 120 is, for example, a UFS driver. Application 130 is executed by electronic device 100, for example, an application performing memory system read operations under user control. Thus, electronic device 100 can implement the data packet transmission required by application 130 based on physical layer interface 110 and interface driver 120 under user control.

[0010] Please refer to Figures 1 and 2. Figure 2 is a schematic diagram of the application of electronic device 100. Figure 2 includes electronic device 100a and electronic device 100b. Electronic device 100a is, for example, a host device. Electronic device 100b is, for example, a flash storage device, and the present invention is not limited thereto. Electronic device 100a includes a sequencer 210a and a deserializer 220a that implement the physical layer function, and a media access control block 300a that implements the media access control layer function. The sequencer 210a and the deserializer 220a are, for example, the aforementioned physical layer interface 110, and the media access control block 300a is, for example, the aforementioned interface driver 120. Electronic device 100b includes a sequencer 210b and a deserializer 220b that implement the physical layer function, and a media access control block 300b that implements the media access control layer function. The sequencer 210b and deserializer 220b are, for example, the aforementioned physical layer interface 110, and the media access control block 300b is, for example, the aforementioned interface driver 120. Electronic devices 100a and 100b establish electrical connections with each other through sequencers 210a and 210b and deserializers 220a and 220b.

[0011] The Media Access Control (MAC) block 300a is electrically connected to the sequencer 210a and the deserializer 220a. The MAC block 300a generates a sequence of data packets to be transmitted in parallel and transmits the data packet sequence to the sequencer 210a. The MAC block 300a receives the data packet sequence from the deserializer 220a. The sequencer 210a receives the data packet sequence from the MAC block 300a, converts the parallel data packet sequence into a serial data stream, and transmits the serial data stream to the deserializer 220b of the electronic device 100b. The deserializer 220a receives the data stream from the serializer 210b of the electronic device 100b, converts the serially transmitted data stream into a parallel-transmitted data packet sequence, and transmits the parallel-transmitted data packet sequence to the media access control block 300a of the electronic device 100a. The operation of the media access control block 300b, the serializer 210b, and the deserializer 220b is the same as that of the media access control block 300a, the serializer 210a, and the deserializer 220a, and therefore will not be described again here.

[0012] Please refer to FIG3, which is a schematic diagram of a sequencer embodiment according to an embodiment of the present invention. FIG3 is illustrated using sequencer 210a as an example. Sequencer 210a is electrically connected to media access control block 300a. Sequencer 210a is used to provide device operating frequency CK2 to media access control block 300a. Device operating frequency CK2 is less than sequence operating frequency CK1. Device operating frequency CK2 is the frequency at which media access control block 300a can operate. Media access control block 300a generates a parallel data packet sequence DP based on the received device operating frequency CK2, and provides device operating frequency CK2 as output operating frequency CK3 to sequencer 210a. Thereby, media access control block 300a can generate a parallel data packet sequence DP based on the received device operating frequency CK2, at an output operating frequency CK3 corresponding to (same as) device operating frequency CK2.

[0013] The sequencer 210a includes a data upsampling processing module 211 and a sequence module 212. The sequence module 212 is electrically connected to the data upsampling processing module 211. The sequence module 212 has a sequence operation frequency CK1 and is used to receive a parallel data packet sequence DP from the data upsampling processing module 211. The sequence module 212 operates at the sequence operation frequency CK1 and converts the received data packet sequence DP into a serially transmitted data stream DS based on the sequence operation frequency CK1. The data upsampling processing module 211 includes a frequency divider unit 2111 and multiple asynchronous register units 2112. The frequency divider unit 2111 is electrically connected to the media access control block 300a and the sequence module 212. The frequency divider unit 2111 receives the sequence operation frequency CK1 of the sequence module 212 and generates a device operation frequency CK2 based on the sequence operation frequency CK1. Frequency divider 2111 reduces the sequence operation frequency CK1 to a lower device operation frequency CK2 based on a division factor (e.g., 2, 4, 6). Asynchronous register 2112 is electrically connected to the media access control block 300a and the sequence module 212. Asynchronous register 2112 receives the sequence operation frequency CK1 and the output operation frequency CK3 from the media access control block 300a. Asynchronous register 2112 receives the data packet sequence DP from the media access control block 300a based on the output operation frequency CK3 and outputs the data packet sequence DP based on the sequence operation frequency CK1. Asynchronous register 2112 is, for example, an asynchronous first-in-first-out (FIFO) element. The number of asynchronous registers 2112 is related to the division factor of frequency divider 2111. For example, when the division factor of frequency divider 2111 is 2, the number of asynchronous registers 2112 is correspondingly 2. In this way, the data packet sequence DP transmitted at the output operating frequency CK3 is converted to be transmitted at the sequence operating frequency CK1, so that the sequence module 212 can operate at the higher sequence operating frequency CK1.

[0014] Please refer to Figure 4, which is a schematic diagram of a data packet sequence DP according to an embodiment of the present invention. The data packet sequence DP includes multiple data packets D1 and D2. Taking data packet D1 as an example, each data packet D1 includes complex synchronization bits S0 and complex data bits Data. Different data packets have different synchronization bits. For example, the complex synchronization bits S0 of data packet D1 are different from the complex synchronization bits S1 of data packet D2.

[0015] Please refer to FIG5, which is a schematic diagram of a deserializer embodiment according to an embodiment of the present invention. FIG5 uses deserializer 220a as an example for illustration. Deserializer 220a is electrically connected to media access control block 300a. Deserializer 220a is used to provide multiple data operation frequencies (e.g., data operation frequencies CK5, CK7) and corresponding restored data packet sequences DP2, DP3 to media access control block 300a. Data operation frequencies CK5, CK7 are frequencies at which media access control block 300a can operate. Media access control block 300a reads the parallel data packet sequences DP based on the received data operation frequency CK5.

[0016] The deserializer 220a includes a deserialization module 222 and multiple data down-frequency processing modules 221a and 221b. The number of the multiple data down-frequency processing modules 221a and 221b corresponds to the frequency division factor. The deserialization module 222 has a deserialization operation frequency. The deserialization module 222 is used to receive the data stream DS from the sequencer 210b based on the deserialization operation frequency, and convert the data stream DS into a data packet sequence DP1 for parallel transmission. The deserialization module 222 is also used to generate multiple data processing frequencies CK4 and CK6 based on the deserialization operation frequency. The data processing frequencies CK4 and CK6 have different frequencies. Please refer to FIG6 first, FIG6 is a schematic diagram of an embodiment of the data packet sequence DP1 according to an embodiment of the present invention. The data packet sequence DP1 includes repeated data packets D1 and D2. For example, the data packet sequence DP1 includes two data packets D1 and two data packets D2. The number of repeated data packets D1 and D2 is related to the division factor of the division unit 2111 and / or the division unit 2211. For example, if the division factor is 2, then the data packet sequence DP1 includes two data packets D1 corresponding to the division factor.

[0017] Each data down-processing module 221a, 221b includes a frequency division unit 2211, an alignment unit 2212, and a packet discarding unit 2213. The following description uses data down-processing module 221a as an example. The frequency division unit 2211 is electrically connected to the media access control block 300a and the deserialization module 222. The frequency division unit 2211 receives the data processing frequency CK4 and generates a data operation frequency CK5 based on the data processing frequency CK4 and the frequency division factor. The data operation frequency CK5 is provided to the media access control block 300a, and the data operation frequency CK5 is less than the deserialization operation frequency and the data processing frequency CK4. The frequency division factor of the frequency division unit 2211 is the same as the frequency division factor of the frequency division unit 2211. The alignment unit 2212 is electrically connected to the deserialization module 222. Alignment unit 2212 receives data processing frequency CK4 and data packet sequence DP1 from deserialization module 222. Alignment unit 2212 determines the start position of each data packet in data packet sequence DP1. Alignment unit 2212 identifies the synchronization bit of each data packet to determine the start position of each data packet in the data packet sequence based on the synchronization bit. For example, alignment unit 2212 identifies the synchronization bit S0 of data packet D1 in data packet sequence DP1 based on data processing frequency CK4 to determine the start position of data packet D1. For example, the position of bit 0 in Figure 6. Alignment unit 2212 can be implemented by logic circuitry. Packet discard unit 2213 is electrically connected to alignment unit 2212, deserialization module 222, and media access control block 300a. The packet discarding unit 2213 receives the data processing frequency CK4, the data packet sequence DP1 from the alignment unit 2212, and the start position of the data packet D1. The packet discarding unit 2213 reads the data packet sequence DP1 based on the data processing frequency CK4, determines the position of the first data packet D1 in the data packet sequence DP1 based on the start position of the data packet D1, discards duplicate data packets D1 in the data packet sequence DP1, and outputs a restored data packet sequence DP2 to the media access control block 300a. The restored data packet sequence DP2 includes non-duplicate data packets D1. Referring also to Figure 6, the packet discarding unit 2213 can read data from bits 0 to 39 of the data packet sequence DP1 according to the known size and start position of the data packet D1, and output the data from bits 0 to 39 of the data packet sequence DP1 as data packet D1. Simultaneously, the packet discarding unit 2213 does not read the data from bits 40 to 79 in the data packet sequence DP1, thereby discarding duplicate data packets D1. The data down-conversion processing module 221b is used to receive the data processing frequency CK6, generate the data operation frequency CK7, and output the restored data packet sequence DP3 to the media access control block 300a.The restored data packet sequence DP3 includes the non-repeating data packet D2. The operation of the data down-conversion processing module 221b is the same as that of the data down-conversion processing module 221a, so it will not be described again here.

[0018] In summary, the sequencer of the present invention can convert received low-frequency data into high-frequency data by upsampling through a data upsampling module, and the deserializer of the present invention downsampling the received high-frequency data into low-frequency data. Therefore, the sequencer / deserializer of the present invention can transmit or receive low-frequency data in conjunction with the operating frequency of the media access control layer elements, and exchange data at a transmission frequency that meets the transmission specifications of the physical layer, thereby improving the convenience of using the sequencer and deserializer. [Simplified Explanation of the Diagram]

[0019] Figure 1 is a block embodiment schematic diagram of an electronic device; Figure 2 is an application schematic diagram of an electronic device; Figure 3 is a sequencer embodiment schematic diagram according to an embodiment of the present invention; Figure 4 is a data packet sequence embodiment schematic diagram according to an embodiment of the present invention; Figure 5 is a deserializer embodiment schematic diagram according to an embodiment of the present invention; and Figure 6 is a data packet sequence embodiment schematic diagram according to an embodiment of the present invention.

Claims

1. A sequencer, a physical layer interface of an electronic device, comprising: A sequence module with a sequence operating frequency is used to convert a sequence of parallel data packets into a data stream for serial transmission. The system also includes a data upsampling processing module comprising: a frequency divider electrically connected to a media access control block and the sequence module, for receiving the sequence operation frequency and generating a device operation frequency based on the sequence operation frequency, the device operation frequency being provided to the media access control block, the device operation frequency being less than the sequence operation frequency; and a plurality of asynchronous register units electrically connected to the media access control block and the sequence module, the asynchronous register units for receiving the sequence operation frequency and an output operation frequency from the media access control block, the asynchronous register units receiving a data packet sequence from the media access control block based on the output operation frequency, and outputting the data packet sequence based on the sequence operation frequency, the output operation frequency being less than the sequence operation frequency, wherein the data packet sequence includes a plurality of non-repeating data packets, and the data stream includes repeated data packets.

2. The sequencer as described in claim 1, wherein, The number of these asynchronous register units and the number of repeated data packets are related to the frequency division factor of the frequency division unit.

3. The sequencer as described in claim 1, wherein, The data packet includes a complex number of synchronization bits and a complex number of data bits, and different data packets have different synchronization bits.

4. The sequencer as described in claim 1, wherein, Each of these asynchronous register units is an asynchronous first-in-first-out (FIFO) element.

5. The sequencer as described in claim 1, wherein, The output operating frequency is the same as the device operating frequency.

6. A deserializer, a physical layer interface of an electronic device, comprising: A sequence deserialization module has a sequence deserialization operation frequency for receiving serially transmitted data streams and converting the data streams into parallel transmitted data packet sequences, the data packet sequences including repeating data packets; The system also includes multiple data downsampling modules, each of which comprises: a frequency divider unit electrically connected to a media access control block and the desequence module, for receiving a data processing frequency and generating a data operation frequency based on the data processing frequency, the data operation frequency being provided to the media access control block, the data operation frequency being less than the desequence operation frequency; and an alignment unit electrically connected to the desequence module, for receiving the data processing frequency and the data packet sequence from the desequence module, the alignment unit being used to determine the start position of each data packet in the data packet sequence. And a packet discarding unit, electrically connected to the alignment unit and the desequence module, for receiving the data processing frequency and the data packet sequence from the alignment unit, discarding repeated data packets in the data packet sequence, and outputting a restored data packet sequence, the restored data packet sequence including non-repeating data packets.

7. The deserializer as described in claim 6, wherein, The number of down-processing modules and the number of repeated data packets are related to the frequency division factor of the down-processing unit.

8. The deserializer as described in claim 6, wherein, The data processing frequencies of each of the data down-processing modules are different.

9. The deserializer as described in claim 6, wherein, The data packet includes a complex number of synchronization bits and a complex number of data bits, and different data packets have different synchronization bits.

10. The deserializer as described in claim 9, wherein, The alignment unit is used to identify the synchronization bits to determine the start position of each data packet in the data packet sequence based on the synchronization bits.

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