Decoder, decoding method, memory controller and memory system

Abstract

A decoder is provided, which includes a first memory and a message updating circuit. The first memory is configured to store posteriori probability messages. The message updating circuit is configured to: sequentially read posteriori probability messages corresponding to respective non-zero sub-matrices of a current layer from the first memory in accordance with a first reading order, the first reading order being determined based on positions of the respective non-zero sub-matrices of the current layer; obtain updated posteriori probability messages corresponding to the respective non-zero sub-matrices of the current layer based on posteriori probability messages corresponding to the respective non-zero sub-matrices of the current layer in a current iteration; and sequentially write the updated posteriori probability messages corresponding to the respective non-zero sub-matrices of the current layer into the first memory in accordance with a first writing order, the first writing order being determined based on the first reading order.

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