Driver

Abstract

A driver is provided. The driver includes a switch-signal generation circuit, a comparison circuit, a driving circuit, and a port control module. The switch-signal generation circuit generates an upper-path non-inverting phase switch signal, an upper-path inverting-phase switch signal, a lower-path non-inverting phase switch signal, and a lower-path inverting-phase switch signal. A non-inverting phase comparator input node of the comparison circuit is electrically connected to a driving output node. An inverting-phase comparator input node is electrically connected to an upper transistor gating node. The driving circuit includes a pull-up circuit and a pull-down circuit. The pull-up circuit and the pull-down circuit selectively adjust the voltage of the driving output node according to the upper transistor gating node and the lower transistor gating node. The port control module sets the voltage of the upper transistor gating node and the voltage of the lower transistor gating node.

Description

drive This invention relates to a driver, and more particularly to a single-stage driver suitable for low-power applications. The Mobile Industry Processor Interface (MIPI) is a specification defined for processor designs widely used in mobile devices such as smartphones. In the MIPI architecture, the MIPI controller uses a PHY layer transmitter to transmit clock and data signals to the receiving circuitry. The data signals transmitted by the MIPI transmitter can be transmitted via one or more data lanes, and the MIPI transmitter has a port physical layer driver for each data lane. Please refer to Figure 1, which is a block diagram of a conventional MIPI port physical layer driver. After receiving the drive circuit enable signal EN and the digital format driver input signal inDAT (which switches between 0 and 1) from the MIPI controller, the MIPI port physical layer driver 10 generates a voltage format driver output signal outSIG based on the driver input signal inDAT when the drive circuit enable signal EN is equal to a high logic level H (EN=H). Alternatively, when the drive circuit enable signal EN is equal to a low logic level L (EN=L), the generation of the driver output signal outSIG based on the driver input signal inDAT is stopped. The driver output signal outSIG is then further transmitted to the MIPI receiver. The MIPI port physical layer driver 10 includes: a port control circuit 101, a low-dropout regulator (LDO) 103, a first-stage driver circuit (DRV1) 105, and a second-stage driver circuit (DRV2) 107. The first-stage driver circuit (DRV1) 105 includes: a pull-up circuit upCKT1 and a pull-down circuit dnCKT1; the second-stage driver circuit (DRV2) 107 includes: a pull-up path capacitor Cup, a pull-up circuit upCKT2, a pull-down path capacitor Cdn, and a pull-down circuit dnCKT2. Port control circuit 101 is electrically connected to the first-stage drive circuit (DRV1) 105 and the second-stage drive circuit (DRV2) 107. Low-dropout regulator 103 is electrically connected to the first-stage drive circuit (DRV1) 105. Furthermore, port control circuit 101, pull-up path capacitor Cup, pull-down path capacitor Cdn, pull-up circuits upCKT1 and upCKT2, and pull-down circuits dnCKT1 and dnCKT2 are all electrically connected to the driver output terminal ND. out The pull-up circuit upCKT1 is electrically connected to the low supply voltage terminal Vddl (e.g., 1.2V), the pull-up circuit upCKT2 is electrically connected to the high supply voltage terminal Vddh (e.g., 1.8V), and the pull-down circuits dnCKT1 and dnCKT2 are both electrically connected to the ground voltage terminal Gnd. For ease of explanation, this document uses the same symbols to represent signal lines and the signal / voltage on those lines. For example, Vddh represents both the high supply voltage endpoint and the high supply voltage. The voltage of the driver output signal outSIG changes according to the value of the driver input signal inDAT. When the driver input signal inDAT is "0" (inDAT="0"), the MIPI port physical layer driver 10 at the driver output terminal ND... out The generated driver output signal outSIG is 0V. When the driver input signal inDAT is "1" (inDAT="1"), the MIPI port physical layer driver 10 is at the driver output terminal ND. out The resulting driver output signal outSIG is 1.2V. Port control circuit 101 receives the driver input signal inDAT from the MIPI controller; receives an input reference voltage Vref_in (e.g., 1V) and a high supply voltage Vddh (e.g., 1.8V) with a fixed voltage value; and receives the driver output terminal ND. out Receive the driver output signal outSIG. After receiving the high supply voltage Vddh (e.g., 1.8V) and the low dropout reference voltage Vref_ldo (e.g., 0.6V), the low dropout regulator 103 first generates a low supply voltage Vddl (e.g., 1.2V) to the first-stage driver circuit (DRV1) 105. Port control circuit 101 generates control signals ctlSIG_pg1, ctlSIG_pg2, ctlSIG_ng1, and ctlSIG_ng2 in response to changes in the driver input signal inDAT. Specifically, port control circuit 101 transmits control signal ctlSIG_pg1 to the pull-up circuit upCKT1 of the first-stage drive circuit (DRV1) 105; transmits control signal ctlSIG_ng1 to the pull-down circuit dnCKT1 of the first-stage drive circuit (DRV1) 105; transmits control signal ctlSIG_pg2 to the pull-up circuit upCKT2 and pull-up path capacitor Cup of the second-stage drive circuit (DRV2) 107; and transmits control signal ctlSIG_ng2 to the pull-down circuit dnCKT2 and pull-down path capacitor Cdn of the second-stage drive circuit (DRV2) 107. When the driver input signal inDAT is in a transient process (inDAT = L → H) from a low logic level L to a high logic level H, the port control circuit 101 enables the pull-up circuit upCKT2 using the control signal ctlSIG_pg2. On the other hand, the port control circuit 101 disables the pull-up circuit upCKT1 using the control signal ctlSIG_pg1, disables the pull-down circuit dnCKT1 using the control signal ctlSIG_ng1, and disables the pull-down circuit dnCKT2 using the control signal ctlSIG_ng2. When the driver input signal inDAT is in a stable state, maintaining a high logic level H, the port control circuit 101 enables the pull-up circuit upCKT1 using the control signal ctlSIG_pg1, keeping the driver output signal outSIG equal to the low supply voltage Vddl (e.g., 1.2V). Simultaneously, the port control circuit 101 disables the pull-down circuit dnCKT1 using the control signal ctlSIG_ng1, disables the pull-up circuit upCKT2 using the control signal ctlSIG_pg2, and disables the pull-down circuit dnCKT2 using the control signal ctlSIG_ng2. When the driver input signal inDAT is in a transient process of changing from a high logic level H to a low logic level L (inDAT=H→L), the port control circuit 101 enables the pull-down circuit dnCKT2 using the control signal ctlSIG_ng2. On the other hand, the port control circuit 101 disables the pull-up circuit upCKT1 using the control signal ctlSIG_pg1, disables the pull-down circuit dnCKT1 using the control signal ctlSIG_ng1, and disables the pull-up circuit upCKT2 using the control signal ctlSIG_pg2. When the driver input signal inDAT is in a stable state maintained at a low logic level L, the port control circuit 101 enables the pull-down circuit dnCKT1 using the control signal ctlSIG_ng1, so that the driver output signal outSIG is maintained at a ground voltage Gnd. At the same time, the port control circuit 101 disables the pull-up circuit upCKT1 using the control signal ctlSIG_pg1, disables the pull-up circuit upCKT2 using the control signal ctlSIG_pg2, and disables the pull-down circuit dnCKT2 using the control signal ctlSIG_ng2. Continuing from the above, in order to generate a 1.2V driver output signal outSIG when the driver input signal inDAT is at a high logic level H (inDAT="H"), the MIPI port physical layer driver 10 needs to be equipped with two driver circuits: a first-stage driver circuit (DRV1) 105 and a second-stage driver circuit (DRV2) 107. The first-stage driver circuit (DRV1) 105 is used to generate the 1.2V driver output signal outSIG; the second-stage driver circuit (DRV2) 107 is used to adjust the slew rate of the driver output signal outSIG during transients of the driver input signal inDAT (e.g., when the driver input signal inDAT changes from a low logic level L to a high logic level H (inDAT="L→H"), or when the driver input signal inDAT changes from a high logic level H to a low logic level L (inDAT="H→L")). As can be seen from Figure 1, the conventional MIPI port physical layer driver 10 has at least the following problems: First, it needs to receive two reference voltages from the outside (input reference voltage Vref_in and low dropout reference voltage Vref_ldo); second, it requires an additional low dropout regulator 103 to provide a low supply voltage Vddl; third, an error amplifier needs to be set inside the low dropout regulator 103, and an operational amplifier (OP) used as a comparator also needs to be set inside the port control circuit 101. Therefore, the circuit design of the conventional MIPI port physical layer driver 10 is still too complicated. This invention relates to a driver implemented using a single-stage drive circuit. The driver of this invention requires only one comparator circuit, resulting in a small circuit area and suitability for low-power applications. According to one aspect of the present invention, a driver is provided. The driver includes: a switching signal generation circuit, a comparator circuit, a drive circuit, and a port control module. The switching signal generation circuit generates a pull-up path positive phase switching signal, a pull-up path negative phase switching signal, a pull-down path positive phase switching signal, and a pull-down path negative phase switching signal based on a drive circuit enable signal and a driver input signal. The comparator circuit is electrically connected to a first fixed voltage terminal and a second fixed voltage terminal. The comparator circuit includes: a positive comparator input terminal, an negative comparator input terminal, a positive comparator output terminal, and a negative comparator output terminal. The positive comparator input terminal is electrically connected to the driver output terminal of the driver. The negative comparator input terminal receives a reference voltage. The reference voltage is greater than the voltage of the second fixed voltage terminal and less than the voltage of the first fixed voltage terminal. The negative comparator output terminal is electrically connected to the pull-up transistor gate terminal. The drive circuit includes: a pull-up circuit and a pull-down circuit. The pull-up circuit is electrically connected to the switching signal generation circuit and the comparator circuit. The pull-up circuit selectively adjusts the voltage at the driver output terminal based on the positive-inverting pull-up path switching signal and the voltage at the pull-up transistor gate terminal. The pull-down circuit is electrically connected to the switching signal generation circuit. The pull-down circuit selectively adjusts the voltage at the driver output terminal based on the negative-inverting pull-down path switching signal and the voltage at the pull-down transistor gate terminal. The port control module is electrically connected to the switching signal generation circuit, the comparator circuit, and the driver circuit. The port control module sets the voltages at the pull-up and pull-down transistor gate terminals based on the positive-inverting pull-up path switching signal, the negative-inverting pull-up path switching signal, the positive-inverting pull-down path switching signal, and the negative-inverting pull-down path switching signal. To provide a better understanding of the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings: To address the shortcomings of conventional MIPI port physical drivers, this disclosure presents the following embodiments of a physical driver. The disclosed portDRV driver can be applied to MIPI port physical drivers or other types of applications. As disclosed in the following embodiments, the disclosed portDRV driver does not require an additional low-dropout regulator, only requires a single operational amplifier, only a single-stage drive circuit, and only needs to receive a reference voltage Vref (e.g., 1.2V). Please refer to Figure 2, which is a block diagram of the driver portDRV according to the present disclosure. The driver portDRV includes: a switching signal generation circuit swGenCKT, a port control module portCtrlMDL, a comparator circuit cfCKT, a drive circuit DRV, and a compensation circuit compCKT. The signals related to the switching signal generation circuit swGenCKT, the port control module portCtrlMDL, the comparator circuit cfCKT, the drive circuit DRV, and the compensation circuit compCKT will then be described in sequence. The switching signal generation circuit swGenCKT is electrically connected to the external controller extCTL (e.g., a MIPI controller), the port control module portCtrlMDL, the drive circuit DRV, and the compensation circuit compCKT. After receiving the drive circuit enable signal EN and the driver input signal inDAT from the external controller extCTL, the switching signal generation circuit swGenCKT generates the pull-up path positive phase switching signal SW_P, the pull-up path negative phase switching signal SWB_P, the pull-down path positive phase switching signal SW_N, and the pull-down path negative phase switching signal SWB_N based on the logic levels of the drive circuit enable signal EN and the driver input signal inDAT. Figure 3 will illustrate the details related to the switching signal generation circuit swGenCKT. The port control module portCtrlMDL is electrically connected to the supply voltage terminal Vcc, the ground voltage terminal Gnd, and the switching signal generation circuit swGenCKT. The port control module portCtrlMDL is biased via the NMOS current mirror terminal ND. mrr_nm PMOS current mirror bias terminal ND mrr_pm ND, the gate control terminal of the pull-up transistor PG18 The comparator circuit cfCKT is electrically connected; the port control module portCtrlMDL is connected to the pull-up capacitor terminal ND. Cup ND terminal of pull-down capacitor Cdn ND, the gate control terminal of the pull-down transistor NG18 and the pull-up transistor gate control terminal ND PG18 The power is connected to the drive circuit DRV; and the port control module portCtrlMDL is biased to the compensation circuit terminal ND. mrr_comp The circuit is electrically connected to the compensation circuit compCKT. The supply voltage terminal Vcc and the ground voltage terminal Gnd have constant voltage values. For example, the supply voltage terminal Vcc is 1.8V; the ground voltage terminal Gnd is 0V. The port control module portCtrlMDL receives the pull-up path positive phase switching signal SW_P, the pull-up path negative phase switching signal SWB_P, the pull-down path positive phase switching signal SW_N, and the pull-down path negative phase switching signal SWB_N from the self-switching signal generation circuit swGenCKT, and generates signals related to the comparator circuit cfCKT, the drive circuit DRV, and the compensation circuit compCKT. Figure 4 illustrates the internal components of the port control module portCtrlMDL and their related signals. The comparator circuit cfCKT is electrically connected to the supply voltage terminal Vcc, the ground voltage terminal Gnd, the port control module portCtrlMDL, the driver circuit DRV, and the compensation circuit compCKT. The comparator circuit cfCKT has an inverting comparator output terminal cfout-, a non-inverting comparator output terminal cfout+, an inverting comparator input terminal cfin-, and a non-inverting comparator input terminal cfin+. The inverting comparator output terminal cfout- is electrically connected to the pull-up transistor gate terminal ND of the driver circuit DRV. PG18 Furthermore, the output terminal cfout+ of the positive comparator is electrically connected to the compensation circuit enable terminal ND of the compensation circuit compCKT. comp_en The comparator circuit cfCKT receives a reference voltage Vref (e.g., 1.2V) with a constant value at the inverting comparator input cfin-; and receives the value of the driving circuit DRV at the driver output ND at the non-inverting comparator input cfin+. out The generated driver output signal is outSIG. Figure 5 will illustrate the internal components and connections of the comparator circuit cfCKT. The drive circuit DRV is electrically connected to the supply voltage terminal Vcc, the ground voltage terminal Gnd, and the switching signal generation circuit swGenCKT. The drive circuit DRV is connected via the pull-up capacitor terminal ND. Cup ND terminal of pull-down capacitor Cdn ND, the gate control terminal of the pull-up transistor PG18 With pull-down transistor gate terminal ND NG18 The electrical connection is to the port control module portCtrlMDL; and the output terminal ND is connected via the driver. outElectrically connected to the compensation circuit compCKT. According to the concept disclosed herein, the internal components of the drive circuit DRV, along with the drive circuit enable signal EN transmitted by the external controller extCTL, and the inverting comparator output Cfout- of the comparator circuit cfCKT (equivalent to the pull-up transistor gate terminal ND), are connected. PG18 The voltage and port control module portCtrlMDL sets the pull-down transistor gate control endpoint ND. NG18 The voltage, along with the pull-up path positive phase switching signal SW_P and pull-down path positive phase switching signal SW_N transmitted by the switching signal generation circuit swGenCKT, changes the driver output signal outSIG. Furthermore, the driver circuit DRV transmits the driver output signal outSIG to the positive phase comparator input cfin+ of the comparator circuit cfCKT. Figure 6 will illustrate the internal components of the driver circuit DRV and their associated signals. The compensation circuit compCKT is electrically connected to the supply voltage terminal Vcc and the ground voltage terminal Gnd. The compensation circuit enable terminal ND of compCKT is... comp_en The voltage is electrically connected to the non-inverting comparator output terminal cfout+ of the comparator circuit cfCKT. Therefore, the voltage at the non-inverting comparator output terminal cfout+ of the comparator circuit cfCKT is equal to the enable terminal ND of the compensation circuit. comp_en The voltage. Additionally, the compensation circuit compCKT and the self-switching signal generation circuit swGenCKT receive the pull-up path positive phase switching signal SW_P; and the driver output terminal ND of the self-driving circuit DRV. out Receive the driver output signal outSIG. For details on the internal components of the compensation circuit compCKT and its associated signals, please refer to Figure 7. The additional current enable circuit (addEnCKT) is electrically connected to the external controller (extCTL), the switching signal generation circuit (swGenCKT), and the compensation circuit (compCKT). One input of the addEnCKT receives the external enable signal IQ_extEN from the external controller (extCTL), and the other input receives the pull-up path positive phase switching signal SW_P from the switching signal generation circuit (swGenCKT). The additional current path enable signal IQ_EN output by the addEnCKT is further transmitted to the compensation circuit (compCKT). Please refer to Figure 3, which is a schematic diagram illustrating how the switching signal generation circuit swGenCKT of this disclosure can be implemented using logic circuitry. In Figure 3, the switching signal generation circuit swGenCKT includes NAND gates NAND1 and NAND2 and NOT gates NOT1a, NOT1b, and NOT1c. In practical applications, the implementation of the switching signal generation circuit swGenCKT is not limited to the example in Figure 3. One input of the reverse gate NAND1 receives the drive circuit enable signal EN, and the other input receives the driver input signal inDAT. The output of the reverse gate NAND1 is defined as the pull-up path inverting switching signal SWB_P. After receiving the pull-up path inverting switching signal SWB_P, the input of the reverse gate NOT1b generates the pull-up path non-inverting switching signal SW_P. After receiving the driver input signal inDAT, the input of the reverse gate NOT1a generates the inverting driver input signal inDAT'. One input of the reverse gate NAND2 receives the drive circuit enable signal EN, and the other input receives the inverting driver input signal inDAT' output by the reverse gate NOT1a. The output of the reverse gate NAND2 is defined as the pull-down path inverting switching signal SWB_N. After receiving the pull-down path inverting switching signal SWB_N, the input of the reverse gate NOT1c generates the pull-down path non-inverting switching signal SW_N. In Figure 3, the logic levels of the drive circuit enable signal EN and the driver input signal inDAT are related to the logic levels of the pull-up path positive phase switching signal SW_P, the pull-up path negative phase switching signal SWB_P, the pull-down path positive phase switching signal SW_N, and the pull-down path negative phase switching signal SWB_N, as shown in Table 1. Table 1 As can be seen from Table 1, the logic level of the input signal inDAT does not necessarily affect the logic levels of the pull-up path positive switching signal SW_P, the pull-up path negative switching signal SWB_P, the pull-down path positive switching signal SW_N, and the pull-down path negative switching signal SWB_N, depending on the logic level of the enable signal EN of the drive circuit. When the driver enable signal EN is at a low logic level L (EN=L), the logic level of the driver input signal inDAT does not affect the logic levels of the pull-up path positive phase switching signal SW_P, the pull-up path negative phase switching signal SWB_P, the pull-down path positive phase switching signal SW_N, and the pull-down path negative phase switching signal SWB_N. More specifically, when the driver enable signal EN is at a low logic level L (EN=L), regardless of how the logic level of the driver input signal inDAT changes, the pull-up path positive phase switching signal SW_P and the pull-down path positive phase switching signal SW_N remain at a low logic level L (SW_P=SW_N=L); and the pull-up path negative phase switching signal SWB_P and the pull-down path negative phase switching signal SWB_N remain at a high logic level H (SWB_P=SWB_N=H). Conversely, when the drive circuit enable signal EN is at a high logic level H (EN=H), the logic levels of the pull-up path in-phase switching signal SW_P and the pull-down path in-phase switching signal SWB_N remain equal to the logic level of the driver input signal inDAT (SW_P=SWB_N=inDAT). Furthermore, the logic levels of the pull-up path in-phase switching signal SWB_P and the pull-down path in-phase switching signal SW_N remain equal to the logic level of the inverting driver input signal inDAT' (SWB_P=SW_N=inDAT'). Please refer to Figure 4, which is a schematic diagram of the internal components and related signals of the port control module portCtrlMDL according to the present disclosure. The port control module portCtrlMDL includes: a reference current source curSRC, a path selection circuit pathSelCKT, a PMOS current mirror disable transistor cfdisPM, an NMOS current mirror disable transistor cfdisNM, a pull-up path disable transistor updisPM, a pull-up path bypass transistor upbpPM, a pull-down path disable transistor dndisNM, a pull-down path bypass transistor dnbpNM, and a compensation disable transistor comp_disNM. The reference current source curSRC is electrically connected to the supply voltage terminal Vcc and the path selection circuit pathSelCKT. The reference current source curSRC is used to provide a stable reference current Iref (e.g., Iref = 10μA). The path selection circuit pathSelCKT is electrically connected to the switching signal generation circuit swGenCKT, the comparator circuit cfCKT, and the pull-down transistor gate terminal ND. NG18 The path selection circuit pathSelCKT and the self-switching signal generation circuit swGenCKT receive the pull-up path positive phase switching signal SW_P and the pull-down path positive phase switching signal SW_N. The PMOS current mirror forbidden transistor cfdisPM is electrically connected to the supply voltage terminal Vcc, the switching signal generation circuit swGenCKT, and the PMOS current mirror bias terminal ND. mrr_pm Furthermore, the PMOS current mirror disabled transistor cfdisPM is biased by the PMOS current mirror terminal ND. mrr_pm Simultaneously, it is electrically connected to the compensation circuit compCKT and the PMOS current mirror pMRR. The PMOS current mirror disable transistor cfdisPM receives the pull-up path positive phase switching signal SW_P from the self-switching signal generation circuit swGenCKT. When the PMOS current mirror disable transistor cfdisPM is turned on according to the logic level of the pull-up path positive phase switching signal SW_P, the PMOS current mirror disable transistor cfdisPM will conduct the supply voltage Vcc to the PMOS current mirror bias terminal ND. mrr_pm That is, ND mrr_pm =Vcc. Conversely, when the PMOS current mirror disable transistor cfdisPM is turned off according to the logic level of the pull-up path positive switching signal SW_P, the PMOS current mirror disable transistor cfdisPM does not affect the PMOS current mirror bias terminal ND. mrr_pm The voltage. The NMOS current mirror barrier transistor cfdisNM is electrically connected to the ground voltage terminal Gnd, the switching signal generation circuit swGenCKT, and the NMOS current mirror bias terminal ND. mrr_nm Furthermore, the NMOS current mirror disabled transistor cfdisNM is biased by the NMOS current mirror terminal ND. mrr_nm The NMOS current mirror nMRR is electrically connected. The NMOS current mirror disable transistor cfdisNM's self-switching signal generation circuit swGenCKT receives the pull-up path inverting switching signal SWB_P. When the NMOS current mirror disable transistor cfdisNM is turned on according to the logic level of the pull-up path inverting switching signal SWB_P, the NMOS current mirror disable transistor cfdisNM will conduct the ground voltage Gnd to the NMOS current mirror bias terminal ND. mrr_nm That is, ND mrr_nm =Gnd. Conversely, when the NMOS current mirror disable transistor cfdisNM is turned off according to the logic level of the pull-up path inverting switching signal SWB_P, the NMOS current mirror disable transistor cfdisNM does not affect the NMOS current mirror bias terminal ND. mrr_nm The voltage. The pull-up path disabled transistor updisPM is electrically connected to the supply voltage terminal Vcc, the switching signal generation circuit swGenCKT, and the gate control terminal ND of the pull-up transistor. PG18 Furthermore, the pull-up path disabled transistor updisPM is controlled by the pull-up transistor gate terminal ND. PG18 The power supply is connected to the drive circuit DRV. The pull-up path disable transistor updisPM receives the pull-up path positive phase switching signal SW_P from the self-switching signal generation circuit swGenCKT. When the pull-up path disable transistor updisPM is turned on according to the logic level of the pull-up path positive phase switching signal SW_P, the pull-up path disable transistor updisPM will conduct the supply voltage Vcc to the gate control terminal ND of the pull-up transistor. PG18 That is, ND PG18 =Vcc. Conversely, when the pull-up path disable transistor updisPM is disconnected along with the logic level of the pull-up path positive switching signal SW_P, the pull-up path disable transistor updisPM does not affect the pull-up transistor gate terminal ND. PG18 The voltage. The pull-up path bypass transistor upbpPM is electrically connected to the supply voltage terminal Vcc, the switching signal generation circuit swGenCKT, and the pull-up capacitor terminal ND. Cup Furthermore, the pull-up path bypass transistor upbpPM passes through the pull-up capacitor terminal ND. Cup The circuit is electrically connected to the driver circuit DRV. The pull-up path bypass transistor upbpPM receives the pull-up path positive phase switching signal SW_P from the self-switching signal generation circuit swGenCKT. When the pull-up path bypass transistor upbpPM is turned on according to the logic level of the pull-up path positive phase switching signal SW_P, the pull-up path bypass transistor upbpPM will conduct the supply voltage Vcc to the pull-up capacitor terminal ND. Cup That is, ND Cup =Vcc. Conversely, when the pull-up path bypass transistor upbpPM is disconnected according to the logic level of the pull-up path positive switching signal SW_P, the pull-up path bypass transistor upbpPM does not affect the pull-up capacitor terminal ND. Cup The voltage. The pull-down path bypass transistor dnbpNM is electrically connected to the ground voltage terminal Gnd, the switching signal generation circuit swGenCKT, and the pull-down capacitor terminal ND. Cdn Furthermore, the pull-down path bypass transistor dnbpNM passes through the pull-down capacitor terminal ND. Cdn The circuit is electrically connected to the driver circuit DRV. The pull-down path bypass transistor dnbpNM receives the pull-down path inverting switching signal SWB_N from the self-switching signal generation circuit swGenCKT. When the pull-down path bypass transistor dnbpNM is turned on according to the logic level of the pull-down path inverting switching signal SWB_N, the pull-down path bypass transistor dnbpNM will conduct the ground voltage Gnd to the pull-down capacitor terminal ND. Cdn That is, ND Cdn =Gnd. When the pull-down path bypass transistor dnbpNM is disconnected according to the logic level of the pull-down path inverting switching signal SWB_N, the pull-down path bypass transistor dnbpNM does not affect the ND terminal of the pull-down capacitor. Cdn The voltage. The pull-down path disable transistor dndisNM is electrically connected to the ground voltage terminal Gnd, the switching signal generation circuit swGenCKT, and the pull-down transistor gate control terminal ND. NG18 Furthermore, the pull-down path disabled transistor dndisNM is controlled by the pull-down transistor gate terminal ND. NG18 The circuit is electrically connected to the drive circuit DRV. The pull-down path disable transistor dndisNM receives the pull-down path inverted switching signal SWB_N from the self-switching signal generation circuit swGenCKT. When the pull-down path disable transistor dndisNM is turned on according to the logic level of the pull-down path inverted switching signal SWB_N, the pull-down path disable transistor dndisNM will conduct the ground voltage Gnd to the gate terminal ND of the pull-down transistor. NG18 That is, ND NG18 =Gnd. When the pull-down path disable transistor dndisNM is disconnected according to the logic level of the pull-down path inverting switching signal SWB_N, the pull-down path disable transistor dndisNM does not affect the pull-down transistor gate endpoint ND. NG18 The voltage. The compensating power-disk transistor comp_disNM is electrically connected to the ground voltage terminal Gnd, the switching signal generation circuit swGenCKT, and the compensation circuit bias terminal ND. mrr_comp Furthermore, the compensated power-disabled transistor comp_disNM is biased through the compensation circuit's ND terminal. mrr_comp The compensation circuit compCKT is electrically connected to the compensation transistor comp_disNM. The self-switching signal generation circuit swGenCKT receives the pull-up path inverting switching signal SWB_P. When the compensation transistor comp_disNM is turned on according to the logic level of the pull-up path inverting switching signal SWB_P, the compensation transistor comp_disNM will conduct the ground voltage Gnd to the bias terminal ND of the compensation circuit. mrr_comp That is, ND mrr_comp =Gnd. When the compensation disable transistor comp_disNM is turned off according to the logic level of the pull-up path inverting switching signal SWB_P, the compensation disable transistor comp_disNM does not affect the bias terminal ND of the compensation circuit. mrr_comp The voltage. Please refer to Figure 5, which is a schematic diagram of the internal components and related signals of the comparator circuit cfCKT according to the present disclosure. According to the present disclosure, the comparator circuit cfCKT is a single-stage CMOS operational amplifier. The comparator circuit cfCKT includes: a PMOS current mirror pMRR, an NMOS current mirror nMRR, and a differential input circuit diffInCKT. The PMOS current mirror pMRR is electrically connected to the PMOS current mirror disable transistor cfdisPM and the differential input circuit diffInCKT. The NMOS current mirror nMRR is electrically connected to the NMOS current mirror disable transistor cfdisNM, the differential input circuit diffInCKT, and the path selection circuit pathSelCKT. The PMOS current mirror pMRR further includes: a PMOS current mirror positive phase transistor pmrr_pPM and a PMOS current mirror negative phase transistor pmrr_nPM. The differential input circuit diffInCKT further includes: a positive phase differential input transistor diffpNM and a negative phase differential input transistor diffnNM. The NMOS current mirror nMRR further includes: an NMOS current mirror positive phase transistor nmrr_pNM and an NMOS current mirror negative phase transistor nmrr_nNM. Wherein, the PMOS current mirror positive phase transistor pmrr_pPM and the PMOS current mirror negative phase transistor pmrr_nPM are PMOS transistors; the positive phase differential input transistor diffpNM, the negative phase differential input transistor diffnNM, the NMOS current mirror positive phase transistor nmrr_pNM, and the NMOS current mirror negative phase transistor nmrr_nNM are NMOS transistors. In the PMOS current mirror pMRR, the source of the PMOS current mirror transistor pmrr_pPM is connected to the supply voltage terminal Vcc, and the gate is connected to the PMOS current mirror bias terminal ND. mrr_pm The drain terminal is connected to the output terminal cfout+ of the positive comparator; the source terminal of the PMOS current mirror inverting transistor pmrr_nPM is connected to the supply voltage terminal Vcc, and the gate terminal is connected to the PMOS current mirror bias terminal ND. mrr_pm The drain current is connected to the output terminal cfout- of the inverting comparator. Therefore, the conduction state of both the PMOS current mirror positive transistor pmrr_pPM and the PMOS current mirror inverting transistor pmrr_nPM depends on the PMOS current mirror bias terminal ND. mrr_pm The voltage. Furthermore, the gate and drain of the PMOS current mirror positive transistor pmrr_pPM are connected to each other. Therefore, the output terminal cfout+ of the positive comparator is equal to the bias terminal ND of the PMOS current mirror. mrr_pm The voltage. The PMOS current mirror forbidden transistor cfdisPM is electrically connected to the switching signal generation circuit swGenCKT, the supply voltage terminal Vcc, and the PMOS current mirror bias terminal ND. mrr_pm Furthermore, the PMOS current mirror disabled transistor cfdisPM receives the pull-up path positive phase switching signal SW_P from the self-switching signal generation circuit swGenCKT. The PMOS current mirror disabled transistor cfdisPM is selectively turned on according to the logic level of the pull-up path positive phase switching signal SW_P. When the PMOS current mirror gated transistor cfdisPM is turned on, the PMOS current mirror gated transistor cfdisPM conducts the supply voltage Vcc to the PMOS current mirror bias terminal ND. mrr_pm That is, ND mrr_pm =Vcc. Consequently, the PMOS current mirror inverting transistor pmrr_pPM and the PMOS current mirror inverting transistor pmrr_nPM will be disconnected because their gates are connected to the supply voltage Vcc. Conversely, when the PMOS current mirror disable transistor cfdisPM is disconnected, it does not affect the PMOS current mirror bias terminal ND. mrr_pm The voltage does not affect the state of the PMOS current mirror positive transistor pmrr_pPM and the PMOS current mirror negative transistor pmrr_nPM. In the differential input circuit diffInCKT, the drain of the positive differential input transistor diffpNM is connected to the PMOS current mirror bias terminal ND. mrr_pm The gate is the positive comparator input terminal cfin+. The drain of the inverting differential input transistor diffnNM is connected to the inverting comparator output terminal cfout-, and the gate is the inverting comparator input terminal cfin-. The source of the positive differential input transistor diffpNM and the source of the inverting differential input transistor diffnNM are connected via the differential terminal ND. diff The common electrical connection is to the NMOS current mirror nMRR. Therefore, whether the positive differential input transistor diffpNM is turned on depends on the voltage at the input terminal cfin+ of the positive comparator; and whether the negative differential input transistor diffnNM is turned on depends on the voltage at the input terminal cfin- of the negative comparator. According to the concept disclosed herein, the positive comparator input terminal cfin+ of the comparator circuit cfCKT is electrically connected to the driver output terminal ND. out Furthermore, the inverting comparator input terminal cfin- of the comparator circuit cfCKT receives the reference voltage Vref. Therefore, the voltage at the non-inverting comparator input terminal cfin+ is equal to the voltage of the driver output signal outSIG. Thus, it can be concluded that whether the non-inverting differential input transistor diffpNM is turned on depends on the voltage of the driver output signal outSIG. In the NMOS current mirror nMRR, the drain and gate of the NMOS current mirror positive transistor nmrr_pNM are electrically connected to the NMOS current mirror bias terminal ND. mrr_nmThe source of the NMOS current mirror transistor (nmrr_nNM) is connected to the ground voltage terminal Gnd; the drain of the NMOS current mirror transistor is connected to the differential terminal ND. diff The gate is electrically connected to the NMOS current mirror bias terminal ND. mrr_nm The source is electrically connected to the ground voltage terminal Gnd. Therefore, whether the NMOS current mirror positive transistor nmrr_pNM and the NMOS current mirror negative transistor nmrr_nNM are turned on or off depends on the NMOS current mirror bias terminal ND. mrr_nm The voltage. Also, the NMOS current mirror bias terminal ND. mrr_nm The voltage changes depending on the conduction state of the path selection circuit pathSelCKT and the NMOS current mirror disabled transistor cfdisNM. The path selection circuit pathSelCKT is electrically connected to the NMOS current mirror bias terminal ND. mrr_nm The path selection circuit pathSelCKT and the self-switching signal generation circuit swGenCKT receive the pull-up path positive phase switching signal SW_P and the pull-down path positive phase switching signal SW_N. When the path selection circuit pathSelCKT is turned on, it conducts the supply voltage Vcc to the NMOS current mirror bias terminal ND. mrr_nm This causes the NMOS current mirror's positive transistor nmrr_pNM and NMOS current mirror's negative transistor nmrr_nNM to conduct. Conversely, when the path selection circuit pathSelCKT is disconnected, the path selection circuit pathSelCKT does not affect the NMOS current mirror's bias terminal ND. mrr_nm The voltage. The NMOS current mirror forbid transistor cfdisNM is electrically connected to the NMOS current mirror bias terminal ND. mrr_nm Furthermore, the NMOS current mirror disable transistor cfdisNM, through its self-switching signal generation circuit swGenCKT, receives the pull-up path inverting switching signal SWB_P. The NMOS current mirror disable transistor cfdisNM selectively conducts according to the logic level of the pull-up path inverting switching signal SWB_P. When the NMOS current mirror disable transistor cfdisNM is on, the NMOS current mirror bias terminal ND... mrr_nm Equal to ground voltage Gnd(ND) mrr_nm=Gnd), which causes the NMOS current mirror positive transistor nmrr_pNM and the NMOS current mirror negative transistor nmrr_nNM to disconnect. Conversely, when the NMOS current mirror disable transistor cfdisNM is disconnected, the NMOS current mirror disable transistor cfdisNM does not affect the state of the NMOS current mirror positive transistor nmrr_pNM and the NMOS current mirror negative transistor nmrr_nNM. Based on the PMOS current mirror pMRR architecture, when the PMOS current mirror positive transistor pmrr_pPM and the PMOS current mirror negative transistor pmrr_nPM are turned on, the comparator reference current I flowing through the PMOS current mirror positive transistor pmrr_pPM... pPM It will be equal to the comparator mirror current I flowing through the PMOS current mirror inverting transistor pmrr_nPM. nPM (I pPM =I nPM Furthermore, the comparator reference current I flowing through the PMOS current mirror positive transistor pmrr_pPM pPM and the comparator mirror current I flowing through the PMOS current mirror inverting transistor pmrr_nPM nPM The current is collected into a bias mirror current I. nNM (I pPM +I nPM =I nNM After that, the current flows through the NMOS current mirror inverting transistor nmrr_nNM. Furthermore, based on the NMOS current mirror nMRR architecture, when both the NMOS current mirror positive transistor nmrr_pNM and the NMOS current mirror inverting transistor nmrr_nNM are turned on, the bias reference current I flowing through the NMOS current mirror positive transistor nmrr_pNM... pNM Equal to the bias mirror current I flowing through the NMOS current mirror inverting transistor nmrr_nNM nNM (I pNM =I nNM ). Please refer to Figure 6, which is a schematic diagram of the internal components and related signals of the drive circuit DRV according to the present disclosure. The drive circuit DRV includes: a pull-up circuit upCKT, a pull-down circuit dnCKT, a drive circuit enable transmission gate enTG, and an output impedance Rout. One end of the pull-up circuit upCKT, the pull-down circuit dnCKT, and the drive circuit enable transmission gate enTG are all electrically connected to the capacitor feedback terminal ND. Cfb The other end of the drive circuit enables the transmission gate enTG and is electrically connected to the output impedance Rout. The drive circuit enable transmission gate enTG receives the drive circuit enable signal EN from the external controller extCTL. The drive circuit enable transmission gate enTG is selectively turned on depending on the drive circuit enable signal EN. When the drive circuit enable signal EN is at a high logic level H (EN=H), the drive circuit enable transmission gate enTG will be turned on, and the driver output signal outSIG will be determined by either the pull-up circuit upCKT or the pull-down circuit dnCKT. When the drive circuit enable signal EN is at a low logic level L (EN=L), the drive circuit enable transmission gate enTG will be turned off, and the driver output signal outSIG will be in a floating state. The pull-up circuit upCKT includes: a pull-up transistor upPM, a pull-up path transmission gate upTG, and a pull-up path capacitor Cup. The source of the pull-up transistor upPM is connected to the supply voltage terminal Vcc, and the gate is connected to the pull-up transistor gate control terminal ND. PG18 The drain electrode is connected to the capacitor's feedback terminal ND. Cfb The pull-up path transmission gate upTG is electrically connected to the pull-up transistor gate control terminal ND. PG18 , and the pull-up capacitor terminal ND Cup The pull-up path capacitor Cup is electrically connected to the pull-up capacitor terminal ND. Cup With capacitor feedback terminal ND Cfb Between. The pull-up circuit upCKT self-switching signal generation circuit swGenCKT receives the pull-up path positive phase switching signal SW_P. Among them, the pull-up path transmission gate upTG, the pull-up path disable transistor updisPM, and the pull-up path bypass transistor upbpPM are all selectively turned on with the pull-up path positive phase switching signal SW_P. The pull-down circuit dnCKT includes: a pull-down transistor dnNM, a pull-down path transmission gate dnTG, and a pull-down path capacitor Cdn. The source of the pull-down transistor dnNM is electrically connected to the ground voltage terminal Gnd, and the gate is electrically connected to the pull-down transistor gate control terminal ND. NG18 The drain electrode is connected to the capacitor's feedback terminal ND. Cfb The pull-down path transmission gate dnTG is electrically connected to the pull-down transistor gate control terminal ND. NG18 With pull-down capacitor terminal ND Cdn The pull-down path capacitor Cdn is electrically connected to the pull-down capacitor terminal ND. Cdn With capacitor feedback terminal ND Cfb Between. The pull-down circuit dnCKT and the self-switching signal generation circuit swGenCKT receive the pull-down path positive phase switching signal SW_N. Among them, the pull-down path transmission gate dnTG is selectively turned on with the pull-down path positive phase switching signal SW_N; the pull-down path disable transistor dndisNM and the pull-down path bypass transistor dnbpNM are selectively turned on with the pull-down path inverse phase switching signal SWB_N. According to the concept disclosed herein, the capacitance value of the pull-up path capacitor Cup is greater than the capacitance value of the pull-down path capacitor Cdn. For example, the pull-up path capacitor Cup is 330fF; the pull-down path capacitor Cdn is 80fF. These capacitance values ​​are used as examples only and are not strictly limited to practical applications. Please refer to Figure 7, which is a schematic diagram of the internal components and related signals of the compensation circuit compCKT according to the present disclosure. The compensation circuit compCKT includes: a compensation reference current path comp_refPATH, K compensation current paths comp_curPATH[1]~comp_curPATH[K], and K additional current paths add_curPATH[1]~add_curPATH[K]. Wherein, K is a positive integer. The compensation reference current path comp_refPATH is electrically connected to the supply voltage endpoint Vcc and the compensation circuit bias endpoint ND. mrr_comp Ground voltage endpoint Gnd. Compensation current path comp_curPATH[1]~comp_curPATH[K] is electrically connected to the driver output endpoint ND. out ND, the bias terminal of the compensation circuit mrr_compGround voltage endpoint Gnd. Additional current paths add_curPATH[1]~add_curPATH[K] are electrically connected to the driver output endpoint ND. out Additional current enable circuit addEnCKT, ground voltage terminal Gnd. The comp_disNM transistor of the compensation circuit selectively switches the bias terminal ND of the compensation circuit according to the logic level of the pull-up path inverting switching signal SWB_P. mrr_comp Pull down to ground voltage Gnd. Furthermore, the compensation reference current path comp_refPATH, compensation current path comp_curPATH[1]~comp_curPATH[K], and additional current path add_curPATH[1]~add_curPATH[K] should correspond to the compensation circuit bias endpoint ND. mrr_comp The voltage is deactivated or a compensation reference current I is generated respectively. comp_ref Compensation current I comp_iq Additional current I add_iq Among them, the compensation current I comp_iq With additional current I add_iq This is the quiescent current used to pull down the driver output signal outSIG. Additionally, the additional current paths add_curPATH[1] to add_curPATH[K] are selected. When the power-disable transistor comp_disNM of the compensation circuit is turned on, the power-disable transistor comp_disNM will turn on the ND terminal of the compensation circuit. mrr_comp Pull down to ground voltage Gnd. Along with ground, the compensation reference current path comp_refPATH will stop generating the compensation reference current I. comp_ref The compensation current path comp_curPATH[1]~comp_curPATH[K] will stop generating compensation current I. comp_iq Furthermore, the additional current paths add_curPATH[1]~add_curPATH[K] will stop generating additional current I. add_iq . Conversely, when the power-disable transistor comp_disNM of the compensation circuit is disconnected, does the compensation reference current path comp_refPATH generate the compensation reference current I? comp_ref It depends on the output terminal cfout+ of the inverting comparator (equivalent to the enable terminal ND of the compensation circuit). comp_en The voltage of the compensation current path (comp_curPATH); whether the compensation current I is generated. comp_iq This depends on the logic level of the pull-up path positive phase switching signal SW_P; and whether the additional current path add_curPATH generates an additional current I. add_iq This depends on the logic level of the additional current path enable signal IQ_EN. The additional current path enable signal IQ_EN is output by the additional current enable circuit addEnCKT. Therefore, the additional current path enable signal IQ_EN depends on the input signal of the additional current enable circuit addEnCKT, that is, the logic level of the pull-up path positive phase switching signal SW_P and the logic level of the additional current path external enable signal IQ_extEN. For simplicity, the following explanation will assume that the additional current path enable signal IQ_EN is at a low logic level (IQ_EN=L), thus disabling the additional current paths add_curPATH[1]~add_curPATH[K]. According to the concept disclosed herein, the additional current enable circuit addEnCKT can be an AND gate. If the external controller extCTL does not enable the additional current paths add_curPATH[1]~add_curPATH[K], the external controller extCTL can set the external enable signal IQ_extEN of the additional current path to a low logic level L (IQ_extEN=L). At this time, no matter how the pull-up path positive phase switching signal SW_P changes, the additional current enable signal IQ_EN output by the additional current enable circuit addEnCKT remains equal to the low logic level L (IQ_EN=L). That is, when IQ_extEN=L, IQ_EN=L. Furthermore, if the external controller extCTL wants to enable the additional current paths add_curPATH[1]~add_curPATH[K], the external controller extCTL can continuously set the external enable signal IQ_extEN of the additional current path to a high logic level H (IQ_extEN=H). At this time, the additional current path enable signal IQ_EN output by the additional current enable circuit addEnCKT changes according to the pull-up path positive phase switching signal SW_P. That is, when IQ_extEN=H, IQ_EN=SW_P. In the foregoing description, Figure 3 illustrates how the switching signal generation circuit swGenCKT is constructed using logic circuits; Figure 4 illustrates the internal components and related signals of the port control module portCtrlMDL; Figure 5 illustrates the internal components and related signals of the comparator circuit cfCKT; Figure 6 illustrates the internal components and related signals of the driver circuit DRV; and Figure 7 illustrates the internal components and related signals of the compensation circuit compCKT. Next, this disclosure will summarize the circuit components mentioned in Figures 4 through 7 in Figure 8. Subsequently, based on the circuit diagram shown in Figure 8, Figures 9 through 14 will illustrate how the driver portDRV presents different circuit states in response to combinations of logic level changes in the driver circuit enable signal EN and the driver input signal inDAT. Please refer to Figure 8, which is a circuit diagram of the driver portDRV according to the present disclosure. In Figures 3, 5, and 6, the circuit elements of the switching signal generation circuit swGenCKT, the comparator circuit cfCKT, and the driver circuit DRV have been described in more detail, respectively. Here, we will further explain how to implement the port control module portCtrlMDL in Figure 4 and the compensation circuit compCKT in Figure 7 using transistors. First, we will explain how to implement the port control module portCtrlMDL using transistors. As shown in Figure 4, the port control module portCtrlMDL includes: a reference current source curSRC, a path selection circuit pathSelCKT, a PMOS current mirror disable transistor cfdisPM, an NMOS current mirror disable transistor cfdisNM, a pull-up path disable transistor updisPM, a pull-up path bypass transistor upbpPM, a pull-down path disable transistor dndisNM, a pull-down path bypass transistor dnbpNM, and a compensation disable transistor comp_disNM. The composition and connection method of these components are described below. Please refer to Figures 4 and 8 as well. The reference current source curSRC is electrically connected to the supply voltage terminal Vcc and the path selection terminal ND. pathSEL Between. The reference current source curSRC is used to provide the reference current Iref (e.g., 10 μA). The path selection circuit pathSelCKT includes: an up-path selection transmission gate upselTG and a down-path selection transmission gate dnselTG. The up-path selection transmission gate upselTG is controlled by the up-path positive phase switching signal SW_P; and the down-path selection transmission gate dnselTG is controlled by the down-path positive phase switching signal SW_N. The pull-up path uses a transmission gate UPSELTG electrically connected to the path selection endpoint ND. pathSELWith NMOS current mirror bias terminal ND mrr_nm When the pull-up path positive phase switching signal SW_P is at a high logic level H (SW_P=H), the pull-up path selection transmission gate upselTG is turned on. Conversely, when the pull-up path positive phase switching signal SW_P is at a low logic level L (SW_P=L), the pull-up path selection transmission gate upselTG is turned off. The pull-down path uses the transmission gate dnselTG, which is electrically connected to the path selection endpoint ND. pathSEL With pull-down transistor gate terminal ND NG18 When the pull-down path positive phase switching signal SW_N is at a high logic level H (SW_N=H), the pull-down path selection transmission gate dnselTG is turned on. Conversely, when the pull-down path positive phase switching signal SW_N is at a low logic level L (SW_N=L), the pull-down path selection transmission gate dnselTG is turned off. When the enable signal EN of the drive circuit is at a high logic level H (EN=H), the pull-up path positive phase switching signal SW_P and the pull-down path positive phase switching signal SW_N remain in opposite phase, so the pull-up path transmission gate upselTG and the pull-down path transmission gate dnselTG will be turned on alternately. When the pull-up path uses the transmission gate upselTG and is turned on while the pull-down path uses the transmission gate dnselTG and is turned off, the reference current Iref flows through the pull-up path uses the transmission gate upselTG and conducts the supply voltage Vcc to the NMOS current mirror bias terminal ND. mrr_nm When the pull-up path transmission gate upselTG is off and the pull-down path transmission gate dnselTG is on, the reference current Iref flows through the pull-down path transmission gate dnselTG, and the pull-down path transmission gate dnselTG conducts the supply voltage Vcc to the pull-down transistor gate control terminal ND. NG18 . Next, the connection method of the transistors in the port control module portCtrlMDL will be explained. As shown in Figure 8, the pull-up path disable transistor updisPM and the pull-up path bypass transistor upbpPM are PMOS transistors; and the pull-down path disable transistor dndisNM and the pull-down path bypass transistor dnbpNM are NMOS transistors. Furthermore, the operation of the pull-up path disable transistor updisPM, the pull-up path bypass transistor upbpPM, and the pull-up circuit upCKT are related; and the operation of the pull-down path disable transistor dndisNM, the pull-down path bypass transistor dnbpNM, and the pull-down circuit dnCKT are related. The connection method and related operation of these circuit elements will be explained one by one below. The source of the pull-up path disable transistor updisPM is connected to the supply voltage terminal Vcc, the gate receives the pull-up path in-phase switching signal SW_P, and the drain is connected to the output terminal cfout- of the inverting comparator. Therefore, whether the pull-up path disable transistor updisPM is on or off depends on the logic level of the pull-up path in-phase switching signal SW_P. When the pull-up path in-phase switching signal SW_P is at a high logic level H (SW_P=H), the pull-up path disable transistor updisPM is off without affecting the voltage at the output terminal cfout- of the inverting comparator (equivalent to the gate terminal ND of the pull-up transistor being off). PG18 The voltage of the pull-up path inverting switch signal SW_P is at a low logic level L (SW_P=L), the pull-up path disable transistor updisPM is turned on, and the voltage at the output terminal cfout- of the inverting comparator is turned on (equivalent to the voltage at the gate terminal ND of the pull-up transistor). PG18 Let the voltage be the supply voltage Vcc. That is, cfout -= ND PG18 =Vcc. The source of the pull-up path bypass transistor upbpPM is connected to the supply voltage terminal Vcc, the gate receives the pull-up path in-phase switching signal SW_P, and the drain is connected to the pull-up capacitor terminal ND. Cup Therefore, whether the pull-up path bypass transistor upbpPM is turned on or off depends on the logic level of the pull-up path positive switching signal SW_P. When the pull-up path positive switching signal SW_P is at a high logic level H (SW_P=H), the pull-up path bypass transistor upbpPM is turned off without affecting the pull-up capacitor terminal ND. Cup The voltage. Conversely, when the pull-up path positive switching signal SW_P is at a low logic level L (SW_P=L), the pull-up path bypass transistor upbpPM is turned on, and the pull-up capacitor terminal ND is switched on. Cup The voltage is set to the supply voltage Vcc. That is, ND Cup =Vcc. The drain of the pull-down path disabled transistor dndisNM is connected to the gate terminal ND of the pull-down transistor. NG18 The gate receives the pull-down path inversion switching signal SWB_N, and the source is electrically connected to the ground voltage terminal Gnd. Therefore, whether the pull-down path disable transistor dndisNM is turned on or off depends on the logic level of the pull-down path inversion switching signal SWB_N. When the pull-down path inversion switching signal SWB_N is at a low logic level L (SWB_N=L), the pull-down path disable transistor dndisNM is turned off without affecting the gate control terminal ND of the pull-down transistor. NG18 The voltage. Conversely, when the pull-down path inverting switching signal SWB_N is at a high logic level H (SWB_N=H), the pull-down path disable transistor dndisNM is turned on, and the gate terminal ND of the pull-down transistor is turned on. NG18 Let ND be the ground voltage Gnd. NG18 =Gnd. The drain of the pull-down path bypass transistor dnbpNM is connected to the ND terminal of the pull-down capacitor. Cdn The gate receives the pull-down path inverting switching signal SWB_N, and the source is electrically connected to the ground voltage terminal Gnd. Therefore, whether the pull-down path bypass transistor dnbpNM is turned on or off depends on the logic level of the pull-down path inverting switching signal SWB_N. When the pull-down path inverting switching signal SWB_N is at a low logic level L (SWB_N=L), the pull-down path bypass transistor dnbpNM is turned off without affecting the pull-down capacitor terminal ND. Cdn The voltage. Conversely, when the pull-down path inverting switching signal SWB_N is at a high logic level H (SWB_N=H), the pull-down path bypass transistor dnbpNM is turned on, and the pull-down capacitor terminal ND is switched on. Cdn The voltage is set to the ground voltage Gnd. That is, ND Cdn =Gnd. The connection relationships between the pull-up path disable transistor updisPM, the pull-up path bypass transistor upbpPM, the pull-up path transmission gate upTG, and the pull-up transistor upPM are further explained. As can be seen from Figure 8, the conduction of the pull-up path disable transistor updisPM, the pull-up path bypass transistor upbpPM, and the pull-up path transmission gate upTG all depend on the logic level of the pull-up path positive phase switching signal SW_P. Therefore, when the pull-up path positive switching signal SW_P is at a low logic level L (SW_P=L), the pull-up path disable transistor updisPM and the pull-up path bypass transistor upbpPM will be turned on, and the pull-up path transmission gate upTG will be turned off. At this time, the voltage at the output terminal cfout- of the inverting comparator (equivalent to the voltage at the gate control terminal ND of the pull-up transistor) will be... PG18 The voltage of the pull-up path is set to the supply voltage Vcc, thereby disconnecting the pull-up transistor upPM. On the other hand, when the pull-up path inverting switching signal SW_P is at a high logic level H (SW_P=H), the pull-up path disable transistor updisPM and the pull-up path bypass transistor upbpPM will be disconnected, and the pull-up path transmission gate upTG will be turned on. At this time, the voltage at the output terminal cfout- of the inverting comparator (equivalent to the voltage at the gate control terminal ND of the pull-up transistor) will be... PG18 The voltage depends on the driver output signal outSIG and the reference voltage Vref received by the comparator circuit cfCKT. The relationship between the pull-down path disable transistor dndisNM, the pull-down path bypass transistor dnbpNM, the pull-down path transmission gate dnTG, and the pull-down transistor dnNM is further explained below. As shown in Figure 8, the conduction of the pull-down path disable transistor dndisNM and the pull-down path bypass transistor dnbpNM depends on the logic level of the pull-down path inverting switching signal SWB_N. On the other hand, the conduction of the pull-down path transmission gate dnTG depends on the logic level of the pull-down path non-inverting switching signal SW_N. Because the logic levels of the pull-down path inverting switching signal SWB_N and the pull-down path positive switching signal SW_N are opposite to each other, in Figure 8, when the pull-down path disable transistor dndisNM and the pull-down path bypass transistor dnbpNM are turned on with the high logic level H (SWB_N=H) of the pull-down path inverting switching signal SWB_N, the pull-down path transmission gate dnTG will be turned off with the low logic level L (SW_N=L) of the pull-down path positive switching signal SW_N. At this time, the pull-down transistor gate control terminal ND... NG18The voltage becomes equal to the ground voltage Gnd as the pull-down path disabled transistor dndisNM turns on, thus causing the pull-down transistor dnNM to turn off. Alternatively, when the pull-down path disable transistor dndisNM and the pull-down path bypass transistor dnbpNM are turned off at the low logic level L (SWB_N=L) of the pull-down path inverting switching signal SWB_N, the pull-down path transmission gate dnTG will be turned on at the high logic level H (SW_N=H) of the pull-down path positive switching signal SW_N. In this case, whether the pull-down transistor dnNM is turned on depends on the gate control terminal ND of the pull-down transistor. NG18 The voltage. Also, because the pull-down path uses a transmission gate dnselTG which conducts with the high logic level H (SW_N=H) of the pull-down path positive phase switching signal SW_N, the pull-down transistor gate control terminal ND at this time... NG18 The voltage is equal to the path selection endpoint ND. pathSEL The voltage (equivalent to the supply voltage Vcc), i.e., ND NG18 =ND pathSEL =Vcc. Therefore, it can be concluded that the pull-down transistor dnNM will conduct under this condition. As can be seen from the foregoing description, under the premise that the enable signal EN of the drive circuit is at a high logic level H (EN=H), the conduction state of the pull-up path disable transistor updisPM and the pull-up path bypass transistor upbpPM is the same, and the conduction state of the pull-up path transmission gate upTG is opposite; and the conduction state of the pull-down path disable transistor dndisNM and the pull-down path bypass transistor dnbpNM is the same, and the conduction state of the pull-down path transmission gate dnTG is opposite. The power-disk transistor comp_disNM in the compensation circuit is an NMOS transistor. The drain of the power-disk transistor comp_disNM is connected to the bias terminal ND of the compensation circuit. mrr_comp The gate receives the pull-up path inverted switching signal SWB_P, and the source is electrically connected to the ground voltage terminal Gnd. Therefore, when the pull-up path inverting switching signal SWB_P is at a high logic level H (SWB_P=H), the compensation circuit's disable transistor comp_disNM will be turned on, and the compensation circuit's bias terminal ND will be activated. mrr_comp It equals the ground voltage Gnd. Once the compensation circuit bias terminal ND... mrr_compIf the voltage is equal to the ground voltage Gnd, then the compensation reference current path comp_refPATH, the compensation current path comp_curPATH, and the additional current path add_curPATH are all disabled, and no current flows through them. Conversely, when the pull-up path inverting switch signal SWB_P is at a low logic level L (SWB_P=L), the compensation circuit disable transistor comp_disNM will be turned off. In this case, the compensation circuit disable transistor comp_disNM does not affect the operation of the compensation reference current path comp_refPATH, the compensation current path comp_curPATH, and the additional current path add_curPATH. Next, we will explain how to implement the compensation circuit compCKT using transistors. Please refer to Figures 7 and 8. For simplicity, Figure 8 assumes that K=1 in the compensation circuit compCKT. That is, the compensation circuit compCKT includes: a compensation reference current path comp_refPATH, a compensation current path comp_curPATH, and an additional current path add_curPATH. The compensation reference current path `comp_refPATH` includes: the compensation current source pull-up bias transistor `comp_bspPM` and the compensation current source pull-down bias transistor `comp_bsnNM`. The compensation current source pull-up bias transistor `comp_bspPM` is a PMOS transistor, and the compensation current source pull-down bias transistor `comp_bsnNM` is an NMOS transistor. The source of the compensation current source pull-up bias transistor `comp_bspPM` is connected to the supply voltage terminal Vcc, and the gate is connected to the PMOS current mirror bias terminal ND. mrr_pm And the drain electrode is connected to the bias terminal ND of the compensation circuit. mrr_comp The drain and gate of the comp_bsnNM pull-down bias transistor, which is used for the compensation current source, are both electrically connected to the bias terminal ND of the compensation circuit. mrr_comp The source is electrically connected to the ground voltage terminal Gnd. Therefore, when the power-disable transistor comp_disNM of the compensation circuit is off, the compensation reference current I... comp_ref Whether the current flows through the compensated reference current path comp_refPATH will depend on the voltage at the output terminal cfout+ of the positive comparator. The current compensation path `comp_curPATH` includes: the current compensation path enabling transistor `comp_iqenNM` and the current compensation path transistor `comp_iqNM`. Both the current compensation path enabling transistor `comp_iqenNM` and the current compensation path transistor `comp_iqNM` are NMOS transistors. The drain of the current compensation path enabling transistor `comp_iqenNM` is connected to the driver output terminal ND. out The gate receives the positive phase switching signal SW_P from the pull-up path, and the source is electrically connected to the drain of the compensation current path transistor comp_iqNM. The gate of the compensation current path transistor comp_iqNM is electrically connected to the bias terminal ND of the compensation circuit. mrr_comp The source is electrically connected to the ground voltage terminal Gnd. Therefore, when the power-disable transistor comp_disNM of the compensation circuit is off, the compensation current I... comp_iq Whether the current flows through the compensation current path comp_curPATH depends on the logic level of the pull-up path positive phase switching signal SW_P. The additional current path add_curPATH includes: the additional current path enabling transistor add_iqenNM and the additional current path transistor add_iqNM. Both the additional current path enabling transistor add_iqenNM and the additional current path transistor add_iqNM are NMOS transistors. The drain of the additional current path enabling transistor add_iqenNM is connected to the driver output terminal ND. out The gate receives the additional current path enable signal IQ_EN, and the source is electrically connected to the drain of the additional current path transistor add_iqNM. The gate of the additional current path transistor add_iqNM is electrically connected to the bias terminal ND of the compensation circuit. mrr_comp The source is electrically connected to the ground voltage terminal Gnd. Therefore, when the power-disable transistor comp_disNM of the compensation circuit is off, the additional current I... add_iq Whether the current flows through the additional current path add_curPATH will depend on the logic level of the additional current path enable signal IQ_EN. Table 2 shows the current paths included in the compensation circuit compCKT, the transistors included in each current path, and the current when the current path is turned on. Table 2 Please refer to Figure 9, which is a schematic diagram of the circuit state of the driver portDRV according to the present disclosure when the drive circuit enable signal EN is at a low logic level L (EN=L). As listed in Table 1, when the drive circuit enable signal EN is at a low logic level L (EN=L), both the pull-up path positive phase switching signal SW_P and the pull-down path positive phase switching signal SW_N remain at a low logic level L (SW_P=SW_N=L); and both the pull-up path negative phase switching signal SWB_P and the pull-down path negative phase switching signal SWB_N remain at a high logic level H (SWB_P=SWB_N=H). The circuit behavior related to the pull-up path, pull-down path, and compensation circuit compCKT in Figure 9 will be described in sequence below. In the pull-up path, because the pull-up path positive switching signal SW_P is at a low logic level L (SW_P=L), the pull-up path transmission gate upselTG is off, the PMOS current mirror disable transistor cfdisPM is on, the pull-up path disable transistor updisPM is on, and the pull-up path bypass transistor upbpPM is on, while the pull-up path transmission gate upTG is off. Furthermore, because the pull-up path inverting switching signal SWB_P is at a high logic level H (SWB_P=H), the NMOS current mirror disable transistor cfdisNM is on. In the comparator circuit cfCKT, because the NMOS current mirror disable transistor cfdisNM is turned on, the NMOS current mirror disable transistor cfdisNM conducts the ground voltage Gnd to the NMOS current mirror bias terminal ND. mrr_nm That is, ND mrr_nm =Gnd. Consequently, the NMOS current mirror positive transistor nmrr_pNM and the NMOS current mirror negative transistor nmrr_nNM in the NMOS current mirror will be disconnected. Additionally, due to the conduction of the PMOS current mirror disabling transistor cfdisPM, the PMOS current mirror disabling transistor cfdisPM conducts the supply voltage Vcc to the PMOS current mirror bias terminal ND. mrr_pm That is, ND mrr_pm =cfout+=Vcc. Consequently, the PMOS current mirror positive transistor pmrr_pPM and the PMOS current mirror negative transistor pmrr_nPM in the PMOS current mirror will be disconnected. In the pull-up circuit upCKT, the gate of the pull-up transistor upPM is controlled by the gate control terminal ND of the pull-up transistor. PG18Voltage control. Due to the conduction of the pull-up path disabled transistor updisPM, the pull-up transistor gate terminal ND... PG18 The voltage of ND is equal to the supply voltage Vcc. That is, ND PG18 =Vcc. Therefore, the pull-up transistor upPM is off. Therefore, in Figure 9, the pull-up transistor upPM does not affect the driver output signal outSIG. In the pull-down path, because the pull-down path positive switching signal SW_N is at a low logic level L (SW_N=L), the pull-down path transmission gate dnselTG and the pull-down path transmission gate dnTG are disconnected; because the pull-down path negative switching signal SWB_N is at a high logic level H (SWB_N=H), the pull-down path bypass transistor dnbpNM and the pull-down path disable transistor dndisNM are turned on. Because the pull-down path disabled transistor dndisNM is turned on, the pull-down path disabled transistor dndisNM conducts the ground voltage Gnd to the gate terminal ND of the pull-down transistor. NG18 This causes the pull-down transistor gate terminal ND to... NG18 It equals the ground voltage Gnd. That is, ND NG18 =Gnd. Along with this, the pull-down transistor dnNM is connected to the gate control terminal ND of the pull-down transistor. NG18 The voltage is equal to the ground voltage Gnd and is disconnected. Therefore, in Figure 9, the pull-down transistor dnNM does not affect the driver output signal outSIG. In the compensation circuit compCKT, because the pull-up path positive switching signal SW_P is at a low logic level L (SW_P=L), the compensation current path enabling transistor comp_iqenNM is turned off. Furthermore, because the pull-up path inverting switching signal SWB_P is at a high logic level H (SWB_P=H), the compensation circuit disabling transistor comp_disNM is turned on. The turned-on disabling transistor comp_disNM conducts the ground voltage Gnd to the compensation circuit bias terminal ND. mrr_comp That is, ND mrr_comp =Gnd. Consequently, the compensating current source pull-down bias transistor comp_bsnNM and the compensating current path transistor comp_iqNM are also disconnected. Therefore, in Figure 9, the compensation circuit compCKT will not affect the driver output signal outSIG. On the other hand, because the voltage at the positive comparator output terminal cfout+, which is electrically connected to the gate of the comparator pull-up piezoelectric crystal comp_bspPM, is equal to the supply voltage Vcc, the comparator pull-up piezoelectric crystal comp_bspPM is also in the off state. In Figure 9, the drive circuit enable gate enTG is disconnected because the drive circuit enable signal EN is at a low logic level (EN=L). Therefore, in Figure 9, the output signal outSIG is in a floating state. Consequently, the positive differential input transistor diffpNM and the inverting differential input transistor diffnNM are also disconnected. As mentioned earlier, when the drive circuit enable signal EN is at a low logic level L (EN=L), the output signal outSIG is in a floating state. Subsequent explanations in Figures 10-21 regarding how the circuit state of the driver portDRV changes with the driver input signal inDAT assume that the drive circuit enable signal EN is at a high logic level H (EN=H). Please refer to Figure 10, which is a schematic diagram showing how the port control module portCtrlMDL, according to the present disclosure, controls the driver portDRV to change its circuit state in response to changes in the driver input signal inDAT when the driver circuit enable signal EN is at a high logic level H (EN=H). With changes in the driver input signal inDAT, the driver portDRV may operate in the rising transient phase PH1, the high steady-state phase PH2, the falling transient phase PH3, and the low steady-state phase PH4. The following describes how the driver portDRV changes its operating state according to the level of the driver input signal inDAT, and the logic levels of the pull-up path positive phase switching signal SW_P, the pull-up path negative phase switching signal SWB_P, the pull-down path positive phase switching signal SW_N, and the pull-down path negative phase switching signal SWB_N, as well as the voltage of the driver output signal outSIG, when the driver portDRV is in the rising transient phase PH1, the high steady-state phase PH2, the falling transient phase PH3, and the low steady-state phase PH4. When the driver input signal inDAT is in the transient process of transitioning from a low logic level L to a high logic level H, the driver portDRV is in the rising transient phase PH1. At this time, the pull-up path positive switching signal SW_P and the pull-down path negative switching signal SWB_N are at high logic level H (SW_P=SWB_N=H); and the pull-up path negative switching signal SWB_P and the pull-down path positive switching signal SW_N are at low logic level L (SWB_P=SW_N=L). On the other hand, the voltage of the driver output signal outSIG gradually rises from the ground voltage Gnd to the reference voltage Vref (outSIG=Gnd→Vref). Figure 11 shows the driver portDRV in the rising transient phase PH1. When the driver input signal inDAT is in a stable state at high logic level H, the driver portDRV is in a high stable state phase PH2. At this time, the pull-up path positive phase switching signal SW_P and the pull-down path negative phase switching signal SWB_N are at high logic level H (SW_P=SWB_N=H); and the pull-up path negative phase switching signal SWB_P and the pull-down path positive phase switching signal SW_N are at low logic level L (SWB_P=SW_N=L). On the other hand, the voltage of the driver output signal outSIG remains at the reference voltage Vref. That is, outSIG=Vref. Figure 12 shows the driver portDRV in the high stable state phase PH2. When the driver input signal inDAT is in the transient process of changing from a high logic level H to a low logic level L, the driver portDRV is in the falling transient phase PH3. At this time, the pull-up path positive switching signal SW_P and the pull-down path negative switching signal SWB_N are at low logic level L (SW_P=SWB_N=L); and the pull-up path negative switching signal SWB_P and the pull-down path positive switching signal SW_N are at high logic level H (SWB_P=SW_N=H). On the other hand, the voltage of the driver output signal outSIG gradually decreases from the reference voltage Vref to the ground voltage Gnd (outSIG=Vref→Gnd). Figure 13 shows the driver portDRV in the falling transient phase PH3. When the driver input signal inDAT is in a stable state at low logic level L, the driver portDRV is in a low stable state phase PH4. At this time, the pull-up path positive phase switching signal SW_P and the pull-down path negative phase switching signal SWB_N are at low logic level L (SW_P=SWB_N=L); and the pull-up path negative phase switching signal SWB_P and the pull-down path positive phase switching signal SW_N are at high logic level H (SWB_P=SW_N=H). On the other hand, the voltage of the driver output signal outSIG remains at the ground voltage Gnd (outSIG=Gnd). Figure 14 shows the driver portDRV in the low stable state phase PH4. Based on the four stages listed in Figure 10, the drive circuit DRV may exhibit two types of situations. Please also refer to Figures 6 and 10. The first case is when the pull-up path positive switching signal SW_P is at a high logic level H (SW_P=H); the pull-down path positive switching signal SW_N is at a low logic level L (SW_N=L); and the pull-down path negative switching signal SWB_N is at a high logic level H (SWB_N=H). In other words, the first case corresponds to the rising transient phase PH1 and the high steady-state phase PH2. The states of the components of the pull-up circuit upCKT and the pull-down circuit dnCKT in the first case are described below. In the pull-up circuit upCKT under the first type of case, the pull-up path transmission gate upTG will be turned on, and the pull-up path disable transistor updisPM and the pull-up path bypass transistor upbpPM will be turned off. Therefore, the pull-up path disable transistor updisPM will not affect the pull-up transistor gate control terminal ND. PG18 The voltage of the pull-up path bypass transistor upbpPM will not affect the ND terminal of the pull-up capacitor. Cup The voltage. At the same time, the pull-up path transmission gate upTG will connect the pull-up transistor gate control terminal ND. PG18 The voltage is conducted to the ND terminal of the pull-up capacitor. Cup On the other hand, in the pull-down circuit dnCKT in the first case, the pull-down path transmission gate dnTG will be open, and the pull-down path disable transistor dndisNM and the pull-down path bypass transistor dnbpNM will be turned on. The turned-on pull-down path disable transistor dndisNM will conduct the ground voltage Gnd to the gate control terminal ND of the pull-down transistor. NG18 Furthermore, the pull-down path bypass transistor dnbpNM in the on state will conduct the ground voltage Gnd to the pull-down capacitor terminal ND. Cdn . The second case is when the pull-up path positive switching signal SW_P is at a low logic level L (SW_P=L); the pull-down path positive switching signal SW_N is at a high logic level H (SW_N=H); and the pull-down path negative switching signal SWB_N is at a low logic level L (SWB_N=L). In other words, the second case corresponds to the falling transient phase PH3 and the low steady-state phase PH4. The states of the components of the pull-up circuit upCKT and the pull-down circuit dnCKT in the second case are described below. In the second type of pull-up circuit upCKT, the pull-up path transmission gate upTG will be disconnected, and the pull-up path disable transistor updisPM and the pull-up path bypass transistor upbpPM will be turned on. At this time, the turned-on pull-up path disable transistor updisPM will conduct the supply voltage Vcc to the pull-up transistor gate control terminal ND. PG18 Furthermore, the conducting pull-up bypass transistor upbpPM will conduct the supply voltage Vcc to the pull-up capacitor terminal ND. Cup On the other hand, in the second type of pull-down circuit dnCKT, the pull-down path transmission gate dnTG will be turned on, and the pull-down path disable transistor dndisNM and the pull-down path bypass transistor dnbpNM will be turned off. In this case, the pull-down path disable transistor dndisNM will not affect the pull-down transistor gate control terminal ND. NG18 The voltage of the pull-down path bypass transistor dnbpNM will not affect the ND terminal of the pull-down capacitor. Cdn The voltage. At the same time, the pull-down path transmission gate dnTG will connect the pull-down transistor gate control terminal ND. NG18 The voltage is conducted to the ND terminal of the pull-down capacitor. Cdn . Next, Figures 11-14 illustrate the states of the circuit elements in the portDRV driver during the rising transient phase PH1, the high steady-state phase PH2, the falling transient phase PH3, and the low steady-state phase PH4, respectively. In Figures 11-14, crosses represent transistors and / or transmission gates in the off state; and dashed arrows represent the signal conduction direction. Furthermore, this paper defines the pull-up path as a combination of the transmission gate upselTG, the elements in the comparator circuit cfCKT, the elements in the pull-up circuit upCKT, the pull-up path disable transistor updisPM, and the pull-up path bypass transistor upbpPM; and defines the pull-down path as a combination of the transmission gate dnselTG, the elements in the pull-down circuit dnCKT, the pull-down path disable transistor dndisNM, and the pull-down path bypass transistor dnbpNM. Please refer to Figure 11, which is a schematic diagram of the circuit state of the driver portDRV according to the present disclosure during the rising transient phase PH1. During the rising transient phase PH1, the driver circuit enable signal EN is at a high logic level H (EN=H); and the driver input signal inDAT transitions from a low logic level L to a high logic level H (inDAT=L→H). Figure 15 will illustrate the component and signal states of the driver portDRV in Figure 11 (during the rising transient phase PH1). Please refer to Figure 12, which is a schematic diagram of the circuit state of the driver portDRV according to the present disclosure during the high steady-state phase PH2. Please also refer to Figures 10 and 12. During the high steady-state phase PH2, the driver circuit enable signal EN is at a high logic level H (EN=H); and the driver input signal inDAT remains equal to the high logic level H (inDAT=H). Figure 15 will illustrate the component and signal states of the driver portDRV during Figure 12 (the high steady-state phase PH2). Please refer to Figure 13, which is a schematic diagram of the circuit state of the driver portDRV according to the present disclosure during the falling transient phase PH3. Please also refer to Figures 10 and 13. During the falling transient phase PH3, the driver circuit enable signal EN is at a high logic level H (EN=H); and the driver input signal inDAT transitions from a high logic level H to a low logic level L (inDAT=H→L). Figure 15 will illustrate the component and signal states of the driver portDRV in Figure 13 (during the falling transient phase PH3). Please refer to Figure 14, which is a schematic diagram of the circuit state of the driver portDRV according to the present disclosure during the low steady-state phase PH4. Please also refer to Figures 10 and 14. During the low steady-state phase PH4, the driver circuit enable signal EN is at a high logic level H (EN=H); and the driver input signal inDAT remains equal to a low logic level L (inDAT=L). Figure 15 will illustrate the component and signal states of the driver portDRV during Figure 14 (the low steady-state phase PH4). Next, the operation of the portDRV driver at each stage is illustrated using the waveforms in Figures 15 and 16. To simplify the diagrams, the waveforms in Figures 15 and 16 do not show the supply voltage terminal Vcc with a constant voltage value, the ground voltage terminal Gnd, or the inverting comparator input cfin- (receive reference voltage Vref). Please refer to Figure 15, which shows the waveforms of the internal endpoints of the driver portDRV according to the present disclosure, when the driver circuit enable signal EN is at a high logic level H (EN=H) and the external enable signal IQ_extEN for the additional current path is set to a low logic level L (IQ_extEN=L) and the additional current path add_curPATH is disabled, as the driver input signal inDAT changes. Figure 15 illustrates the waveforms related to the driver portDRV: driver input signal inDAT, driver output signal outSIG, pull-up path positive phase switching signal SW_P, pull-down path negative phase switching signal SWB_N, pull-up path negative phase switching signal SWB_P, pull-down path positive phase switching signal SW_N, positive phase comparator output cfout+, and pull-up transistor gate terminal ND. PG18 ND, the gate control terminal of the pull-down transistor NG18 , pull-up capacitor terminal ND Cup ND terminal of pull-down capacitor Cdn Compensation reference current I comp_ref Compensation current I comp_iq ND, the bias terminal of the compensation circuit mrr_comp The process changes depending on the different stages of the rising transient phase PH1, the high steady-state phase PH2, the falling transient phase PH3, and the low steady-state phase PH4. Table 3 summarizes the waveform changes in Figure 15. The voltage and current values ​​listed here are approximate figures for illustrative purposes. Furthermore, the voltage and current values ​​used in actual applications are not limited to these figures. Table 3 In Figure 15, the periods t2~t3 and t6~t7 correspond to the rising transient phase PH1 (for the state of the driver portDRV in the rising transient phase PH1, please refer to Figure 11); the periods t3~t4 and t7~t8 correspond to the high steady-state phase PH2 (for the state of the driver portDRV in the high steady-state phase PH2, please refer to Figure 12); the periods t4~t5 and t8~t9 correspond to the falling transient phase PH3 (for the state of the driver portDRV in the falling transient phase PH3, please refer to Figure 13); and the periods t1~t2, t5~t6, and t9~t10 correspond to the low steady-state phase PH4 (for the state of the driver portDRV in the low steady-state phase PH4, please refer to Figure 14). Since the state of the driver portDRV cycles between the rising transient phase PH1, the high steady-state phase PH2, the falling transient phase PH3, and the low steady-state phase PH4, the following description of the waveform is based on time points t2 to t6. Please also refer to Figures 11, 12, and 15. During the rising transient phase PH1 (see Figure 11) from time t2 to t3, the driver input signal inDAT changes from a low logic level L to a high logic level H (inDAT = L → H); during the high steady-state phase PH2 from time t3 to t4, the driver input signal inDAT remains equal to the high logic level H (inDAT = H) (see Figure 12). During the rising transient phase PH1 and the high steady-state phase PH2, the switching signal generation circuit swGenCKT generates a high logic level H pull-up path positive phase switching signal SW_P and a pull-down path negative phase switching signal SWB_N (SW_P=SWB_N=H), as well as a low logic level L pull-up path negative phase switching signal SWB_P and a pull-down path positive phase switching signal SW_N (SWB_P=SW_N=L). Please refer to Figures 11 and 15. During the period from time t2 to t3, in the pull-up path, because the pull-up path positive phase switching signal SW_P is at a high logic level H (SW_P=H), the pull-up path transmission gate upselTG is turned on, the PMOS current mirror disable transistor cfdisPM is turned off, the pull-up path disable transistor updisPM is turned off, the pull-up path bypass transistor upbpPM is turned off, and the pull-up path transmission gate upTG is turned on. During time points t2 to t3, because the pull-up path inverting switching signal SWB_P is at a low logic level L (SWB_P=L), the NMOS current mirror disable transistor cfdisNM is turned off. Therefore, during the rising transient phase, PH1 of the NMOS current mirror disable transistor cfdisNM does not affect the NMOS current mirror bias terminal ND. mrr_nm The voltage. At this time, the pull-up path selected by the conduction gate upselTG conducts the supply voltage Vcc to the NMOS current mirror bias terminal ND. mrr_nm That is, ND mrr_nm =Vcc. Because the gate is connected to the NMOS current mirror bias terminal ND mrr_nm Because of this, the NMOS current mirror positive transistor nmrr_pNM and NMOS current mirror negative transistor nmrr_nNM in the NMOS current mirror nMRR will change with the NMOS current mirror bias terminal ND. mrr_nm Set to supply voltage Vcc (ND) mrr_nm =Vcc) and then conduct. Furthermore, the reference current Iref (e.g., 10μA) provided by the reference current source curSRC will become the bias reference current I flowing through the NMOS current mirror positive transistor nmrr_pNM to the ground voltage Gnd. pNM Based on the current mirror architecture, the NMOS current mirror inverting transistor nmrr_nNM also has a bias mirror current I. nNM (For example: 40μA) flows through. On the other hand, because the PMOS current mirror disable transistor cfdisPM is disconnected by the positive phase switching signal SW_P (SW_P=H) of the pull-up path, the PMOS current mirror disable transistor cfdisPM does not affect the PMOS current mirror bias terminal ND. mrr_pm (Also, the voltage at the output terminal cfout+ of the positive comparator). At this time, whether the PMOS current mirror positive transistor pmrr_pPM and PMOS current mirror negative transistor pmrr_nPM in the PMOS current mirror pMRR are turned on or off depends on the bias terminal ND of the PMOS current mirror. mrr_pm (Also, the voltage at the output terminal cfout+ of the positive comparator). In the comparator circuit cfCKT, the gate of the inverting differential input transistor diffnNM (equivalent to the inverting comparator input terminal cfin-) is turned on due to receiving the reference voltage Vref, which in turn causes the output terminal cfout- of the inverting comparator (also the pull-up transistor gate terminal ND) to be turned on. PG18 The voltage is gradually reduced from the supply voltage Vcc to approximately 1.3V (cfout - ND). PG18 =Vcc↓). Consequently, during time points t2 to t3, the PMOS current mirror bias terminal ND, which is symmetrical to the output terminal cfout of the inverting comparator, is... mrr_pm The voltage at the output terminal cfout+ of the non-inverting comparator (i.e., the voltage at cfout+) gradually decreases from the supply voltage Vcc to approximately 1.4V (cfout+=ND) as the non-inverting differential input transistor diffpNM and the NMOS current mirror inverting transistor nmrr_nNM are turned on. mrr_pm =ND comp_en =Vccà1.4V). As the voltage at the output terminal cfout+ of the non-inverting comparator decreases, the PMOS current mirror non-inverting transistor pmrr_pPM gradually turns on, generating a current (e.g., 20 μA) flowing through the PMOS current mirror non-inverting transistor pmrr_pPM and the non-inverting differential input transistor diffpNM. This current is due to the bias terminal ND of the PMOS current mirror. mrr_pm Because it is electrically connected to the output terminal cfout+ of the positive comparator, the PMOS current mirror inverting transistor pmrr_nPM gradually turns on. The PMOS current mirror inverting transistor pmrr_nPM, now in the on state, will then pull up the output terminal cfout- (which is also the pull-up transistor gate terminal ND) of the inverting comparator. PG18 The voltage is slightly increased from 1.3V to 1.5V. Subsequently, the PMOS current mirror inverting transistor pmrr_nPM, the inverting differential input transistor diffnNM, and the NMOS current mirror inverting transistor nmrr_nNM, in the on-state, will cause the pull-up transistor gate terminal ND to... PG18 It remains roughly at 1.5V. Simultaneously, a current (e.g., 20 μA) is generated flowing through the PMOS current mirror inverting transistor pmrr_nPM and the inverting differential input transistor diffnNM. Furthermore, the current flowing through the NMOS current mirror inverting transistor nmrr_nNM is equivalent to the sum of the currents flowing through the inverting differential input transistor diffnNM and the currents flowing through the non-inverting differential input transistor diffpNM (e.g., 40 μA). In the pull-up circuit upCKT, the gate of the pull-up transistor upPM is controlled by the gate control terminal ND of the pull-up transistor. PG18 Voltage control. As mentioned earlier, the pull-up transistor gate terminal ND... PG18The voltage is equal to the voltage at the output terminal cfout- of the inverting comparator (ND). PG18 =cfout-). Therefore, the pull-up transistor gate terminal ND PG18 The voltage first gradually decreases from the supply voltage Vcc to 1.3V, then slightly increases to 1.5V. That is, ND... PG18 =cfout-=1.8Và1.3Và1.5V. With the pull-up transistor gate control terminal ND PG18 The voltage change causes the pull-up transistor upPM to change from an off state to a conducting state, which in turn pulls up the voltage of the driver output signal outSIG during time points t2~t3, thus gradually increasing it from the ground voltage Gnd. Furthermore, because the compensation current path comp_curPATH generates a compensation current I... comp_iq As a result, the voltage of the driver output signal outSIG is simultaneously pulled down by the compensation current path comp_curPATH. Therefore, at time t3, the driver output signal outSIG will not rise to the supply voltage Vcc, but will rise to the reference voltage Vref. That is, outSIG = Gnd → Vref. Because the pull-up path transmission gate upTG is turned on by the pull-up path positive phase switching signal SW_P (SW_P=H) of the high logic level H, during time points t2~t3, the pull-up capacitor terminal ND Cup The voltage at the output terminal cfout- of the inverting comparator is equal to the voltage at that terminal. Therefore, the voltage at the pull-up capacitor terminal ND... Cup The voltage also drops from 1.8V to 1.3V during the time interval t2~t3, and then rises from 1.3V to 1.5V. That is, ND Cup =1.8V → 1.3V → 1.5V. During this period, the pull-up path capacitor Cup also flows through the PMOS current mirror inverting transistor pmrr_nPM and the pull-up transistor gate terminal ND. PG18 The pull-up path transmission gate upTG and the pull-up capacitor terminal ND Cup And then it was charged. In the pull-down path, because the pull-down path positive switching signal SW_N is at a low logic level L (SW_N=L), the pull-down path transmission gate dnselTG and the pull-down path transmission gate dnTG are disconnected; because the pull-down path negative switching signal SWB_N is at a high logic level H (SWB_N=H), the pull-down path bypass transistor dnbpNM and the pull-down path disable transistor dndisNM are turned on. Because the pull-down path disabled transistor dndisNM is turned on, the pull-down path disabled transistor dndisNM conducts the ground voltage Gnd to the gate terminal ND of the pull-down transistor. NG18 This causes the pull-down transistor gate terminal ND to... NG18 The voltage ND is equal to the ground voltage Gnd. That is, ND NG18 =Gnd. Along with this, the pull-down transistor dnNM is connected to the gate control terminal ND of the pull-down transistor. NG18 The voltage is equal to the ground voltage Gnd(ND) NG18 =Gnd) and disconnected. Therefore, in Figure 11, the pull-down transistor dnNM does not affect the driver output signal outSIG. Additionally, because the pull-down path bypass transistor dnbpNM is turned on, the pull-down capacitor terminal ND... Cdn As the pull-down path bypass transistor dnbpNM is turned on, it is pulled down to the ground voltage Gnd. In the compensation circuit compCKT in Figure 11, the compensation current path enabling transistor comp_iqenNM is turned on because the pull-up path positive switching signal SW_P is at a high logic level H (SW_P=H). Conversely, the compensation circuit disabling transistor comp_disNM is turned off because the pull-up path inverting switching signal SWB_P is at a low logic level L (SWB_P=L). The off state of the compensation circuit disabling transistor comp_disNM does not affect the compensation circuit bias terminal ND. mrr_comp The voltage. On the other hand, because the gate of the pull-up bias transistor comp_bspPM is connected to the output terminal cfout+ of the positive comparator, whether the pull-up bias transistor comp_bspPM is turned on depends on the voltage at the output terminal cfout+ of the positive comparator (cfout+=ND). mrr_pm =ND comp_en ). Because the output terminal cfout+ of the inverting comparator gradually decreases from the supply voltage Vcc to 1.4V (cfout+=ND) mrr_pm =ND comp_en Because of the voltage Vcc (approximately 1.4V), the pull-up bias transistor comp_bspPM of the compensation current source will gradually change from the off state to the on state. Furthermore, the on-state comp_bspPM will conduct the supply voltage Vcc to the bias terminal ND of the compensation circuit. mrr_comp The bias terminal ND of the compensation circuit mrr_comp The voltage gradually increases. With the bias terminal ND of the compensation circuit mrr_comp As the voltage rises, the pull-down bias transistor comp_bsnNM of the compensation current source and the compensating current path transistor comp_iqNM also turn on. As the pull-up bias transistor comp_bspPM of the compensation current source gradually turns on, a compensation reference current I will be generated in the compensation reference current path comp_refPATH, flowing through the pull-up bias transistor comp_bspPM and the pull-down bias transistor comp_bsnNM of the compensation current source. comp_ref (For example, 10μA). Because both the pull-up bias transistor comp_bspPM and the pull-down bias transistor comp_bsnNM of the compensation current source are conducting, during time points t2~t3, the bias terminal ND of the compensation circuit... mrr_comp The voltage will rise from the ground voltage Gnd to approximately 0.5V. Meanwhile, the compensation current path transistor comp_iqNM, which forms a current mirror with the compensation current source pull-down bias transistor comp_bsnNM, also flows along with the bias terminal ND of the compensation circuit connected to its gate. mrr_comp It conducts because the voltage is equal to 0.5V. Also, because the compensation current path enabling transistor comp_iqenNM conducts with the pull-up path positive-phase switching signal SW_P (SW_P=H) of the high logic level H, a compensation current I is generated in the compensation current path comp_curPATH, flowing through the compensation current path enabling transistor comp_iqenNM and the compensation current path transistor comp_iqNM. comp_iq (e.g., 20μA). Because the compensation current path enables the drain current of the transistor comp_iqenNM, it is connected to the driver output terminal ND. out Because of this, the compensation current path enables the transistor comp_iqenNM to conduct the ground voltage Gnd to the driver output terminal ND. out This causes the voltage of the driver output signal outSIG to vary with the compensation current I. comp_iq The dropdown was triggered by the generation of [something]. As previously mentioned, in Figure 11, the driver output signal outSIG is simultaneously pulled up by the turn-on of the pull-up transistor upPM and pulled down by the turn-on of both the compensation current path enable transistor comp_iqenNM and the compensation current path transistor comp_iqNM. Consequently, the driver output signal outSIG will be between the ground voltage Gnd and the supply voltage Vcc. At this time, based on the symmetrical structure of the PMOS current mirror pMRR, the voltage of the driver output signal outSIG is equal to the reference voltage Vref. Continuing from the previous point, in Figure 11, the driver output signal outSIG rises from the ground voltage Gnd to the reference voltage Vref. That is, outSIG = Gnd → Vref = 0V → 1.2V. Also, in Figure 11, the driver circuit enable transmission gate enTG is turned on by the driver circuit enable signal EN (EN = H) at the high logic level H. Therefore, the capacitor feedback terminal ND... Cfb The voltage changes with the output signal outSIG. That is, ND Cfb =0V→1.2V. When the driver portDRV is in the rising transient phase PH1, in addition to using the pull-up transistor upPM to pull up the voltage of the output signal outSIG, the pull-up path capacitor Cup is also charged simultaneously via the pull-up path transmission gate upTG. Simultaneously, the pull-up transistor gate control terminal ND... PG18 It will also be affected by this voltage conduction path. Accordingly, the setting of the pull-up path capacitor Cup can compensate for the AC response of the driver output signal outSIG during time points t2~t3. As mentioned above, the pull-up path capacitor (Cup) exhibits the Miller effect, affecting the slew rate of the driver's output signal (outSIG). A larger pull-up path capacitor (Cup) results in a lower slew rate of the driver's output signal (outSIG), meaning a smoother voltage rise. Conversely, a smaller pull-up path capacitor (Cup) results in a higher slew rate of the driver's output signal (outSIG), meaning a sharper voltage rise during the rising transient phase (PH1). In practical applications, the selected value of the pull-up path capacitor (Cup) depends on the specifications required by the driver's portDRV. During time points t3~t4 (high steady-state stage PH2, see Figure 12), the driver input signal inDAT remains equal to the high logic level H (inDAT=H). Therefore, in Figure 12, the on / off state of the transistor in the driver portDRV remains the same as in the latter part of Figure 11. Furthermore, the driver output signal outSIG, the pull-up path positive phase switching signal SW_P, the pull-down path negative phase switching signal SWB_N, the pull-up path negative phase switching signal SWB_P, the pull-down path positive phase switching signal SW_N, the positive phase comparator output cfout+, and the pull-up transistor gate control terminal ND... PG18 ND, the gate control terminal of the pull-down transistor NG18 , pull-up capacitor terminal ND Cup ND terminal of pull-down capacitor Cdn Compensation reference current I comp_ref Compensation current I comp_iq ND, the bias terminal of the compensation circuit mrr_comp The waveforms during time points t3 to t4 remain unchanged from those at time point t3. Therefore, the on / off states of the transistors in the driver portDRV and the voltages at each terminal, as shown in Figure 12, will not be repeated here. Please also refer to Figures 13, 14, and 15. During the falling transient phase PH3, the driver input signal inDAT transitions from a high logic level H to a low logic level L (inDAT = H → L); during the low steady-state phase PH4, the driver input signal inDAT remains equal to the low logic level L (inDAT = L). During the falling transient phase PH3 and the low steady-state phase PH4, the switching signal generation circuit swGenCKT generates a positive-phase pull-up path switching signal SW_P and a negative-phase pull-down path switching signal SWB_N (SW_P = SWB_N = L) for the low logic level L, and a negative-phase pull-up path switching signal SWB_P and a positive-phase pull-down path switching signal SW_N (SWB_P = SW_N = H) for the high logic level H. The circuit behavior related to the pull-up path, pull-down path, and compensation circuit compCKT is described below in sequence. Please refer to Figures 13 and 15 simultaneously. During time points t4 to t5, in the pull-up path, because the pull-up path positive switching signal SW_P is at a low logic level L (SW_P=L), the pull-up path transmission gate upselTG is off, the PMOS current mirror disable transistor cfdisPM is on, the pull-up path disable transistor updisPM is on, and the pull-up path bypass transistor upbpPM is on, while the pull-up path transmission gate upTG is off. Furthermore, because the pull-up path inverting switching signal SWB_P is at a high logic level H (SWB_P=H), the NMOS current mirror disable transistor cfdisNM is on. Because the NMOS current mirror disabling transistor cfdisNM is turned on, the NMOS current mirror disabling transistor cfdisNM conducts the ground voltage Gnd to the reference bias terminal and the NMOS current mirror bias terminal ND. mrr_nm That is, ND mrr_nm =Gnd. Therefore, the NMOS current mirror positive transistor nmrr_pNM and the NMOS current mirror negative transistor nmrr_nNM are connected to the gate of the NMOS current mirror bias terminal ND. mrr_nm Equal to ground voltage Gnd(ND) mrr_nm It was disconnected because of =Gnd). In the comparator circuit cfCKT, as the NMOS current mirror bias terminal ND... mrr_nm Set as ground voltage Gnd(ND) mrr_nm=Gnd), the NMOS current mirror inverting transistor nmrr_pNM and the NMOS current mirror inverting transistor nmrr_nNM will be turned off. Additionally, because the PMOS current mirror disable transistor cfdisPM is turned on, the PMOS current mirror disable transistor cfdisPM will conduct the supply voltage Vcc to the PMOS current mirror bias terminal ND. mrr_pm Make the output terminal cfout+ of the non-inverting comparator equal to the supply voltage Vcc (cfout+=ND) mrr_pm =ND comp_en =Vcc). At this time, the PMOS current mirror positive transistor pmrr_pPM and PMOS current mirror negative transistor pmrr_nPM are disconnected due to the supply voltage Vcc received at the gate. As shown in Figure 13, the pull-up path disabled transistor updisPM turns on when SW_P=L. The supply voltage Vcc of the conducting pull-up path disabled transistor updisPM is conducted to the gate terminal ND of the pull-up transistor. PG18 That is, ND PG18 =Vcc. Along with ground, the pull-up transistor upPM, along with the pull-up transistor gate terminal ND... PG18 The voltage equals the supply voltage Vcc, causing it to disconnect. At this time, the pull-up transistor upPM does not affect the driver output signal outSIG. Additionally, during time points t4~t5, due to the conduction of the pull-up path bypass transistor upbpPM, the pull-up capacitor terminal ND... Cup It equals the supply voltage Vcc. That is, ND Cup =1.8V. Furthermore, during time points t4~t5, the pull-up path capacitor Cup passes through the pull-up path bypass transistor upbpPM and the pull-up capacitor terminal ND. Cup It continues to be charged to 1.8V. In the pull-down path, because the pull-down path positive switching signal SW_N is at a high logic level H (SW_N=H), the pull-down path transmission gate dnselTG and the pull-down path transmission gate dnTG are turned on; because the pull-down path negative switching signal SWB_N is at a low logic level L (SWB_N=L), the pull-down path bypass transistor dnbpNM and the pull-down path disable transistor dndisNM are turned off. Because the pull-down path disable transistor dndisNM is disconnected, the pull-down path disable transistor dndisNM does not affect the gate control terminal ND of the pull-down transistor. NG18 The voltage. At this time, the conducting pull-down path uses the transmission gate dnselTG to conduct the supply voltage Vcc to the gate control terminal ND of the pull-down transistor. NG18 Pull-down transistor gate terminal ND NG18 During the period from time t4 to t5, the self-grounding voltage Gnd rises to the supply voltage Vcc. That is, ND NG18 =GndàVcc. Consequently, the pull-down transistor dnNM is connected to the gate control terminal ND of the pull-down transistor. NG18 The driver turns on because the voltage is equal to the supply voltage Vcc, which in turn causes the driver output signal outSIG to drop from the supply voltage Vcc to the ground voltage Gnd. That is, outSIG = Vcc → Gnd. During the period from time t4 to t5, due to the conduction of the pull-down path transmission gate dnTG, the pull-down capacitor terminal ND... Cdn With the pull-down transistor gate terminal ND NG18 The voltage rises synchronously to the supply voltage Vcc. In the compensation circuit compCKT, because the pull-up path inverting switching signal SWB_P is at a high logic level H (SWB_P=H), the compensation circuit disable transistor comp_disNM is turned on. Furthermore, the compensation circuit disable transistor comp_disNM will turn on the ND bias terminal of the compensation circuit. mrr_comp Set as ground voltage Gnd(ND) mrr_comp =Gnd). Consequently, the compensating current source pull-down bias transistor comp_bsnNM and the compensating current path transistor comp_iqNM remain disconnected during time points t4~t5. Whether the compensating current source pull-up bias transistor comp_bspPM is turned on depends on the PMOS current mirror bias terminal ND. mrr_pm (Equivalent to the voltage at the output terminal cfout+ of the non-inverting comparator, where cfout+ = ND) mrr_pm =ND comp_enFurthermore, because the output terminal cfout+ of the positive comparator in Figure 13 is equal to the supply voltage Vcc, the pull-up piezoelectric transistor comp_bspPM of the compensation current source remains off during time points t4 to t5. Therefore, there is no compensation reference current I during time points t4 to t5. comp_ref The compensation reference current path `comp_refPATH` is generated. On the other hand, in the compensation current path `comp_curPATH`, the compensation current path enabling transistor `comp_iqenNM` is disconnected because the pull-up path positive phase switching signal `SW_P` is at a low logic level L (SW_P=L). Therefore, in the compensation current path `comp_curPATH`, both the compensation current path enabling transistor `comp_iqenNM` and the compensation current path transistor `comp_iqNM` are disconnected. At this time, there is no compensation current `I` in the compensation current path `comp_curPATH`. comp_iq produce. Furthermore, in Figure 13, the driver output signal outSIG is pulled down to the ground voltage Gnd when the pull-down transistor dnNM is turned on. Therefore, the positive differential input transistor diffpNM in the differential input circuit diffInCKT is turned off because the driver output signal outSIG received at its gate is equal to the ground voltage Gnd. Consequently, the inverting differential input transistor diffnNM, located on the other side of the differential input circuit diffInCKT, is also turned off during the falling transient phase of PH3. When the driver portDRV is in the falling transient phase PH3, in addition to using the pull-down transistor dnNM to pull down the voltage of the driver output signal outSIG, the pull-down path capacitor Cdn is also charged simultaneously through the pull-down path transmission gate dnTG. Simultaneously, the pull-down transistor gate control terminal ND... NG18 It will also be affected by this voltage conduction path. Accordingly, the setting of the pull-down path capacitor Cdn can compensate for the AC response of the driver output signal outSIG during time points t4~t5. As mentioned above, the pull-down path capacitor Cdn exhibits the Miller effect, affecting the slew rate of the driver's output signal outSIG. A larger value for the pull-down path capacitor Cdn results in a lower slew rate for the driver's output signal outSIG. That is, during the transient hysteresis phase PH3, the voltage drop of the driver's output signal outSIG is more gradual. Conversely, a smaller value for the pull-down path capacitor Cdn results in a higher slew rate for the driver's output signal outSIG. That is, the voltage drop of the driver's output signal outSIG is steeper. In practical applications, the capacitance value of the pull-down path capacitor Cdn depends on the specifications required by the driver's portDRV. During time points t5~t6 (low steady-state stage PH4, see Figure 14), because the driver input signal inDAT remains equal to the low logic level L (inDAT=L), the on / off state of the transistor in the driver portDRV remains the same as that described in the latter part of Figure 13, as shown in Figure 14. Furthermore, the driver output signal outSIG, the pull-up path positive phase switching signal SW_P, the pull-down path negative phase switching signal SWB_N, the pull-up path negative phase switching signal SWB_P, the pull-down path positive phase switching signal SW_N, the positive phase comparator output cfout+, and the pull-up transistor gate control terminal ND... PG18 ND, the gate control terminal of the pull-down transistor NG18 , pull-up capacitor terminal ND Cup ND terminal of pull-down capacitor Cdn Compensation reference current I comp_ref Compensation current I comp_iq ND, the bias terminal of the compensation circuit mrr_comp The waveforms during time points t5 to t6 remain consistent with the state at time point t5 without change. Therefore, the on / off states of the transistors in the driver portDRV and the voltages at each terminal will not be repeated here as shown in Figure 14. As mentioned earlier, the external enable signal IQ_extEN for the additional current path is one input to the additional current enable circuit addEnCKT. The other input to the additional current enable circuit addEnCKT is the pull-up path positive phase switching signal SW_P. Here, it can be assumed that the additional current enable circuit addEnCKT is a gate. When the external enable signal IQ_extEN for the additional current path is at a low logic level L (IQ_extEN=L), regardless of the logic level of the pull-up path positive phase switching signal SW_P, the additional current path enable signal IQ_EN at the gate output remains at a low logic level L (IQ_EN=L). The waveform in Figure 15 corresponds to the case where the additional current path add_curPATH in Figure 5 is disabled. In other words, the waveform change in Figure 15 corresponds to the state of the driver portDRV in Figures 11-14. On the other hand, when the external enable signal IQ_extEN for the additional current path is at a high logic level H (IQ_extEN=H), the additional current path enable signal IQ_EN at the gate output changes according to the logic level of the positive phase switching signal SW_P for the pull-up path. When the positive phase switching signal SW_P for the pull-up path is at a high logic level H (SW_P=H), the additional current path enable signal IQ_EN is also at a high logic level H (IQ_EN=(IQ_extEN AND SW_P)=H). When the positive phase switching signal SW_P for the pull-up path is at a low logic level L (SW_P=L), the additional current path enable signal IQ_EN is also at a low logic level L (IQ_EN=L). Figure 16 shows the waveform of the additional current path enabled by assuming that the external enable signal IQ_extEN of the additional current path is maintained at a high logic level H (IQ_extEN=(IQ_extEN AND SW_P)=H), thus enabling the additional current path by making the external enable signal IQ_EN of the additional current path at a high logic level H (IQ_EN=H) during the rising transient phase PH1 and the high steady-state phase PH2. Please refer to Figure 16, which is a waveform diagram showing how the internal endpoints of the driver portDRV according to the present disclosure change with the driver input signal inDAT when the driver circuit enable signal EN is at a high logic level H (EN=H) and the external enable signal IQ_extEN of the additional current path is set to a high logic level H (IQ_extEN=H) to enable the additional current path add_curPATH. The signal waveforms shown in Figures 15 and 16 are largely similar. The difference lies in the fact that Figure 16 assumes the external enable signal IQ_extEN for the additional current path is at a high logic level H (IQ_extEN=H), thus adding an additional current I compared to Figure 15. add_iq The waveform of the additional current path enable signal IQ_EN. In other words, Figure 15 is equivalent to assuming an additional current I... add_iq The current path enable signal IQ_EN remains at 0 μA and remains at a low logic level L (IQ_EN=L). With the additional current I add_iq The generation of this effect makes the change process of some signals smoother. For example, the bias terminal ND of the comparator compensation circuit... mrr_comp As can be seen from the waveforms in Figures 15 and 16, although the bias terminal ND of the compensation circuit... mrr_comp In Figures 15 and 16, during the time points t2~t3, the voltage rises from 0V to 0.5V, but the bias terminal ND of the compensation circuit... mrr_comp The waveform during time point t2~t3 in Figure 16 (the rising transient phase PH1) is slightly smoother than the waveform during time point t2~t3 in Figure 15. Other terminals include the output of the inverting comparator (cfout+), the output of the inverting comparator (cfout-), and the pull-up capacitor (ND). Cup The waveforms in Figures 15 and 16 also show a trend where the waveform in Figure 16 is smoother or has a slightly smaller range of variation than the waveform in Figure 15. Therefore, it can be concluded that the additional current I... add_iq The generation of this signal does not change the way the signal changes; it simply makes the change in the signal during the rising transient phase PH1 smoother. Therefore, when describing the signal in Figure 16 below, we will not repeat the descriptions of other signals that have already been drawn in Figure 15. Table 4 summarizes how the waveforms of signals not appearing in Figure 15 change with different stages, as shown in Figure 16. The voltage and current values ​​listed here are approximate and for reference only. Furthermore, the voltage and current values ​​used in actual applications are not limited to these. Table 4 Please refer to Figure 16 and Table 4 simultaneously. Because the pull-up path positive phase switching signal SW_P is at a high logic level H (SW_P=H) during the rising transient phase PH1 and the high steady-state phase PH2, the additional current path enable signal IQ_EN is also at a high logic level H (IQ_EN=H) during the rising transient phase PH1 and the high steady-state phase PH2. Furthermore, the additional current I... add_iq The current value rises from 0 μA to 20 μA during the rising transient phase PH1, and remains at 20 μA during the high steady-state phase PH2. During the falling transient phase PH3 and the low steady-state phase PH4, the additional current path enable signal IQ_EN is at a low logic level L (IQ_EN=L), and no additional current I is generated at this time. add_iq . Please refer to Figure 17, which is a schematic diagram showing the connection of the transistor path output impedance Rout_ts and the capacitor path output impedance Rout_cp to the driver portDRV. In this diagram, the transistor path output impedance Rout_ts (e.g., Rout_ts = 500Ω) is electrically connected to the transistor path output terminal ND. Rout_ts With the driver output terminal ND outBetween; the capacitor path output impedance Rout_cp (e.g., Rout_cp = 250Ω) is electrically connected to the drive circuit enable transmission gate enTG and the driver output terminal ND. out Between. Wherein, the transistor path output impedance Rout_ts is greater than the capacitor path output impedance Rout_cp. In practical applications, the impedance values ​​of the transistor path output impedance Rout_ts and the capacitor path output impedance Rout_cp are not limited to the examples here. Please refer to Figure 18A, which is a schematic diagram showing the calculation of the equivalent output impedance Rout_eq when pull-up paths are selected during the rising transient phase PH1 and the high steady-state phase PH2 after adding the transistor path output impedance Rout_ts and the capacitor path output impedance Rout_cp to the driver portDRV. Please also refer to Figures 11, 12, and 18A. When the driver portDRV is in the rising transient phase PH1 or the high steady-state phase PH2, the calculation of the equivalent output impedance Rout_eq must consider the pull-up path output impedances Rout_up1 and Rout_up2 on two signal pull-up transmission paths. The first is the pull-up path output impedance Rout_up1 on the signal pull-up transmission path (Rout_ts+upPM) of the series-connected transistor path Rout_ts; the second is the path output impedance Rout_up2 on the signal pull-up transmission path (Rout_cp+Cup) of the series-connected capacitor path Rout_cp and the pull-up path capacitor Cup. Because the signal pull-up transmission paths (Rout_ts+upPM) and (Rout_cp+Cup) are parallel to each other, the equivalent output impedance Rout_eq of the driver portDRV in Figure 18A is equivalent to the parallel connection of the pull-up path output impedances Rout_up1 and Rout_up2. That is, Rout_eq = Rout_up1 / / Rout_up2. In the signal pull-up transmission path (Rout_ts+upPM), because the pull-up transistor upPM has only a very small turn-on resistance when it is turned on, the pull-up path output impedance Rout_up1 is approximately equal to the transistor path output impedance Rout_ts. That is, Rout_up1 ≈ Rout_ts. Furthermore, because the impedance of the pull-up path capacitor Cup is equivalent to infinity (∞), the pull-up path output impedance Rout_up2 in the signal pull-up transmission path (Rout_cp+Cup) is approximately infinite (∞). That is, Rout_up2 ≈ ∞. Therefore, in Figure 18A, the equivalent output impedance Rout_eq is equivalent to the result of connecting the pull-up path output impedances Rout_up1 and Rout_up2 in parallel on the signal pull-up transmission paths (Rout_ts+upPM) and (Rout_cp+Cup). In this case, the equivalent output impedance Rout_eq approximates the transistor path output impedance Rout_ts. That is, Rout_eq = Rout_up1 / / Rout_up2 ≈ Rout_ts. Please refer to Figure 18B, which shows the calculation of the equivalent output impedance Rout_eq when the pull-down path is selected during the transient phase PH3 and the low steady-state phase PH4 after adding the transistor path output impedance Rout_ts and the capacitor path output impedance Rout_cp to the driver portDRV. Please also refer to Figures 13, 14, and 18B. When the driver portDRV is in the transient PH3 or the low steady-state PH4, the calculation of the equivalent output impedance Rout_eq must consider the pull-down path output impedances Rout_dn1 and Rout_dn2 on two signal pull-down transmission paths. The first is the pull-down path output impedance Rout_dn1 on the signal pull-down transmission path (Rout_ts+dnNM) of the series-connected transistor path Rout_ts and the pull-down path output impedance Rout_dn2 on the signal pull-down transmission path (Rout_cp+Cdn) of the series-connected capacitor path Rout_cp and the pull-down path capacitor Cdn. Since the signal pull-down transmission paths (Rout_ts+dnNM) and (Rout_cp+Cdn) are parallel, the equivalent output impedance Rout_eq of the driver portDRV in Figure 18B can be expressed as the parallel connection of the pull-down path output impedances Rout_dn1 and Rout_dn2. That is, Rout_eq=Rout_dn1 / / Rout_dn2. In the signal pull-down transmission path (Rout_ts+dnNM), because the pull-down transistor dnNM has only a very small turn-on resistance when it is turned on, the pull-down path output impedance Rout_dn1 is approximately equal to the transistor path output impedance Rout_ts. That is, Rout_dn1≈Rout_ts. Furthermore, because the impedance of the pull-down path capacitor Cdn is equivalent to infinity (∞), the pull-down path output impedance Rout_dn2 on the signal pull-down transmission path (Rout_cp+Cdn) is approximately equal to infinity (∞). That is, Rout_dn2≈∞. Therefore, in Figure 18B, the equivalent output impedance Rout_eq is equivalent to the result of connecting the pull-down path output impedances Rout_dn1 and Rout_dn2 in parallel on the signal pull-down transmission paths (Rout_ts+dnNM) and (Rout_cp+Cdn). At this point, the equivalent output impedance Rout_eq is approximately equal to the transistor path output impedance Rout_ts. That is, Rout_eq = Rout_dn1 / / Rout_dn2 ≈ Rout_ts. In practical applications, the portDRV driver disclosed herein can be configured with K pull-up transistors upPM[1]~upPM[K] in the pull-up circuit upCKT and K pull-down transistors dnNM[1]~dnNM[K] in the pull-down circuit dnCKT, based on electrostatic discharge (ESD) protection considerations. K is a positive integer. The following example assumes K=4. Please refer to Figure 19, which is a schematic diagram of multiple parallel pull-up transistors upPM[1]~upPM[4], multiple parallel pull-down transistors dnNM[1]~dnNM[4], and multiple parallel transistor path output impedances Rout_ts[1]~Rout_ts[4] set in the driver portDRV. The pull-up circuit upCKT contains pull-up transistors upPM[1]~upPM[4] connected in parallel; the pull-down circuit dnCKT contains pull-down transistors dnNM[1]~dnNM[4] connected in parallel. The source terminals of pull-up transistors upPM[1] to upPM[4] are all electrically connected to the supply voltage terminal Vcc, and the gate terminals are all electrically connected to the gate control terminal ND of the pull-up transistor. PG18 Therefore, the on / off states of the pull-up transistors upPM[1]~upPM[4] remain consistent. The sources of the pull-down transistors dnNM[1]~dnNM[K] are all electrically connected to the ground voltage terminal Gnd, and the gates are all electrically connected to the gate control terminal ND of the pull-down transistor. NG18 Therefore, the on / off states of the pull-down transistors dnNM[1]~dnNM[4] remain consistent. The drain of pull-up transistor upPM[k] and the drain of pull-down transistor dnNM[k] are electrically connected to the output terminal ND of the transistor path. Rout_ts [k]. Furthermore, the transistor path output impedance Rout_ts[k] is electrically connected to the transistor path output terminal ND. Rout_ts [k] and driver output endpoint ND out Between. k and K are positive integers, and k≤K. For example, the drain of the pull-up transistor upPM[1] and the drain of the pull-down transistor dnNM[1] are electrically connected to the output terminal ND of the transistor path. Rout_ts [1]. Furthermore, the transistor path output impedance Rout_ts[1] is electrically connected to the transistor path output terminal ND. Rout_ts [1] and driver output terminal ND out between. Since the transistor path output impedances Rout_ts[1]~Rout_ts[K] are connected in parallel, by analogy with the explanations in 18A and 18B, we can know that the equivalent output impedance Rout_eq is approximately the result of the transistor path output impedances Rout_ts[1]~Rout_ts[K] connected in parallel. That is, the equivalent output impedance Rout_eq = (Rout_ts[1] / / Rout_ts[2] / / ... / / Rout_ts[K]). Based on the consideration of maintaining the resistance value of the equivalent output impedance Rout_eq, if K is larger, then a transistor path output impedance Rout_ts[1]~Rout_ts[K] with a larger resistance value needs to be used. In this way, the resistance value of the equivalent output impedance Rout_eq can be maintained while increasing K. However, using a transistor path output impedance Rout_ts[1]~Rout_ts[K] with a larger resistance value also means that a larger circuit area is required. Therefore, in practical applications, electrostatic discharge protection can be provided by increasing the number of pull-up transistors upPM[1]~upPM[K] and pull-down transistors dnNM[1]~dnNM[K]. However, the value of K still needs to be determined by referring to the total area occupied by the pull-up transistors upPM[1]~upPM[K], pull-down transistors dnNM[1]~dnNM[K], capacitor path output impedance Rout_cp, and transistor path output impedance Rout_ts[1]~Rout_ts[K]. If the driver portDRV adds pull-up transistors upPM[1]~upPM[K] and pull-down transistors dnNM[1]~dnNM[K] for electrostatic protection considerations, as shown in Figure 19, then the number of compensation current paths comp_curPATH[1]~comp_curPATH[K] and additional current paths add_curPATH[1]~add_curPATH[K] must also be adjusted accordingly. Figure 20 assumes that when K=4, it is necessary to set compensation current paths comp_curPATH[1]~comp_curPATH[4] and additional current paths add_curPATH[1]~add_curPATH[4]. Please refer to Figure 20, which is a schematic diagram of the parallel compensation current paths comp_curPATH[1]~comp_curPATH[4] and the parallel additional current paths add_curPATH[1]~add_curPATH[4] set up in response to the driver portDRV in Figure 19. For the sake of simplicity, only the compensation circuit compCKT is shown in Figure 20. In Figure 20, the compensation circuit compCKT includes: the compensation reference current path comp_refPATH and the compensation current paths comp_curPATH[1]~comp_curPATH[4]. Among them, the compensation reference current path comp_refPATH includes: the compensation current source pull-up bias transistor comp_bspPM and the compensation current source pull-down bias transistor comp_bsnNM. The compensation current path comp_curPATH[k] (k=1~4) includes: the compensation current path enable transistor comp_iqenNM[k] and the compensation current path transistor comp_iqNM[k]. When the compensation reference current I comp_ref When a compensation current Icomp_iq[k] (e.g., 20μA) is generated (e.g., 10μA), a corresponding compensation current Icomp_iq[k] is also generated on the compensation current path comp_curPATH[k]. When the pull-up path capacitor Cup has a small capacitance value, the AC stability of the driver portDRV will be poor. In this case, an additional current path add_curPATH can be used to improve the AC stability of the driver portDRV. Figure 20 illustrates the architecture when K=4 and additional current paths add_curPATH[1]~add_curPATH[K] are selected. The additional current paths add_curPATH[k] (k=1~4) include: the additional current path enabling transistor add_iqenNM[k] and the additional current path transistor add_iqNM[k]. Both the additional current path enabling transistor add_iqenNM[k] and the additional current path transistor add_iqNM[k] are NMOS transistors. Please refer to Figures 16 and 20. As can be seen from the waveform in Figure 16, the additional current path enable signal IQ_EN is at a high logic level H (IQ_EN=H=1.8V) when the driver portDRV is in the rising transient phase PH1 and the high steady-state phase PH2. Therefore, the additional current path add_curPATH[k] will generate an additional current I during the rising transient phase PH1 and the high steady-state phase PH2. add_iq [k] (e.g., 20 μA). The value of K here refers to the compensation reference current I. comp_ref The current value of the compensation current Icomp_iq[k], the current value of the additional current I add_iq The current values ​​for [k] are examples and are not limited to these values ​​in actual applications. Please refer to Figure 21, which is a schematic diagram of a low-dropout regulator (LDO) formed by a comparator circuit cfCKT, a pull-up transistor upPM, and a compensation circuit compCKT according to the concept disclosed herein. Please also refer to Figures 8 and 21. The circuit elements and connections shown in Figure 21 are the same as those in Figure 8. In Figure 21, the circuit elements and connections within the comparator circuit cfCKT, pull-up transistor upPM, and compensation circuit compCKT are indicated by thick black lines. The circuit elements and connections of the comparator circuit cfCKT, pull-up transistor upPM, and compensation circuit compCKT in this diagram are equivalent to a low-dropout regulator (LDO). When the driver portDRV is in the high steady-state phase PH2, this LDO architecture can stably maintain the driver output signal outSIG equal to the reference voltage Vref. Therefore, it can be seen that the driver portDRV disclosed herein utilizes existing circuitry to incorporate the function of a low-dropout regulator (LDO), thereby reducing the required circuit area. Compared to conventional technologies, the driver portDRV disclosed herein has at least the following advantages: it eliminates the need for an additional low-dropout regulator, requires only one operational amplifier, necessitates only a single-stage drive circuit, and requires only a reference voltage Vref. Compared to conventional technologies, the driver portDRV disclosed herein can be implemented with a simpler circuit, saving power and occupying a smaller area, thereby reducing product manufacturing costs. In practical applications, this disclosure proposes that the power-saving driver portDRV has no limited uses. For example, in addition to applications in MIPI port physical layer drivers, it can also be applied to display driver circuits, etc. The scope of practical applications in this section will not be detailed here. In summary, although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. 10: MIPI physical layer driver 101: Port control circuit 103, LDO: Low dropout regulator 105, DRV1: First-stage driver circuit 107, DRV2: Second-stage driver circuit EN: Driver circuit enable signal inDAT: Driver input signal Vref_ldo: Low dropout reference voltage Vref_in: Input reference voltage Vddl: Low supply voltage (endpoint) Vddh: High supply voltage (endpoint) Gnd: Ground voltage (endpoint) Cup: Pull-up path capacitor Cdn: Pull-down path capacitor upCKT2, upCKT1, upCKT: Pull-up circuit dnCKT2, dnCKT1, dnCKT: Pull-down circuit ctlSIG_pg1, ctlSIG_ng1, ctlSIG_pg2, ctlSIG_ng2: Control signal ND out : Driver output endpoint outSIG: Driver output signal portDRV: Driver swGenCKT: Switching signal generation circuit extCTL: External controller portCtrlMDL: Port control module cfCKT: Comparator circuit compCKT: Compensation circuit DRV: Driver circuit SW_P: Pull-up path positive switching signal SWB_P: Pull-up path negative switching signal SW_N: Pull-down path positive switching signal SWB_N: Pull-down path negative switching signal cfout+: Positive comparator output terminal cfout-: Inverting comparator output terminal cfin+: Positive comparator input terminal cfin-: Inverting comparator input terminal Vref: Reference voltage ND mrr_pm PMOS current mirror bias terminal ND mrr_nm NMOS current mirror bias terminal ND Cup : Pull-up capacitor terminal ND Cdn Pull-down capacitor terminal ND NG18 Pull-down transistor gate endpoint IQ_EN: Additional current path enable signal IQ_extEN: Additional current path external enable signal Vcc: Supply voltage (terminal) ND comp_en : Compensation circuit enable terminal ND mrr_compCompensation circuit bias terminals NAND1, NAND2: reverse gate NOT1a, NOT1b, NT1c: reverse gate cfdisPM: PMOS current mirror disable transistor cfdisNM: NMOS current mirror disable transistor updisPM: pull-up path disable transistor upbpPM: pull-up path bypass transistor dnbpNM: pull-down path bypass transistor dndisNM: pull-down path disable transistor comp_disNM: compensation circuit disable transistor ND PG18 : Pull-up transistor gate terminal pathSelCKT: Path selection circuit pMRR: PMOS current mirror pmrr_pPM: PMOS current mirror positive transistor pmrr_nPM: PMOS current mirror negative transistor I pPM Comparator reference current I nPM Comparator mirror current: diffpNM; Non-inverting differential input transistor: diffnNM; Inverting differential input transistor: diffInCKT; Differential input circuit I nNM : Bias mirror current nMRR: NMOS current mirror nmrr_nNM: NMOS current mirror inverting transistor nmrr_pNM: NMOS current mirror non-inverting transistor I pNM : Bias reference current upPM,upPM[1],upPM[2],upPM[3],upPM[4]: Pull-up transistor upTG: Pull-up path transmission gate dnTG: Pull-down path transmission gate dnNM,dnNM[1],dnNM[2],dnNM[3],dnNM[4]: Pull-down transistor enTG: Drive circuit enable transmission gate Rout: Output impedance addEnCKT: Additional current enable circuit comp_refPATH: Compensation reference current path comp_curPATH[1],comp_curPATH[K]: Compensation current path add_curPATH[1],add_curPATH[K]: Additional current path curSRC: Reference current source ND pathSEL : Path selection endpoint upselTG: Pull-up path selects transmission gate dnselTG: Pull-down path selects transmission gate ND diff Differential endpoint ND Cfb :Capacitor feedback endpoint add_iqenNM:Additional current path enables transistor I add_iq , I add_iq [1],I add_iq [2],I add_iq [3],I add_iq [4]: Added current add_iqNM,add_iqNM[1],add_iqNM[2],add_iqNM[3],add_iqNM[4]: Added current path transistor comp_iqNM,comp_iqNM[1],comp_iqNM[2],comp_iqNM[3],comp_iqNM[4]: Compensation current path transistor comp_bsnNM: Compensation current source pull-down bias transistor comp_bspPM: Compensation current source pull-up bias transistor PH1: Rising transient stage PH2: High steady state stage PH3: Falling transient stage PH4: Low steady state stage t1~t10: Time point I comp_ref Compensation reference current I comp_iq ,I comp_iq [1],I comp_iq [2],I comp_iq [3],I comp_iq [4]: Compensation current Rout_ts, Rout_ts[1], Rout_ts[2], Rout_ts[3], Rout_ts[4]: Transistor path output impedance ND Rout_ts ,ND Rout_ts [1],ND Rout_ts [2],ND Rout_ts [3],ND Rout_ts [4]: Transistor path output endpoint Rout_cp: Capacitor path output impedance Figure 1 is a block diagram of a conventional MIPI port physical layer driver; Figure 2 is a block diagram of a driver portDRV according to the present disclosure; Figure 3 is a schematic diagram illustrating how to implement the switching signal generation circuit swGenCKT of the present disclosure using logic circuits; Figure 4 is a schematic diagram of the internal components and related signals of the port control module portCtrlMDL according to the present disclosure; Figure 5 is a schematic diagram of the internal components and related signals of the comparator circuit cfCKT according to the present disclosure; Figure 6 is a schematic diagram of the internal components and related signals of the drive circuit DRV according to the present disclosure; Figure 7 is a schematic diagram of the internal components and related signals of the compensation circuit compCKT according to the present disclosure; Figure 8 is a circuit diagram of the driver portDRV according to the present disclosure; Figure 9 is a schematic diagram of the circuit state of the driver portDRV according to the present disclosure when the drive circuit enable signal EN is at a low logic level L (EN=L). Figure 10 is a schematic diagram showing how the port control module portCtrlMDL, according to the present disclosure, controls the driver portDRV to change its circuit state in response to changes in the driver input signal inDAT when the driver enable signal EN is at a high logic level H (EN=H); Figure 11 is a schematic diagram showing the circuit state of the driver portDRV according to the present disclosure during the rising transient phase PH1; Figure 12 is a schematic diagram showing the circuit state of the driver portDRV according to the present disclosure during the high steady-state phase PH2; Figure 13 is a schematic diagram showing the circuit state of the driver portDRV according to the present disclosure during the falling transient phase PH3; Figure 14 is a schematic diagram showing the circuit state of the driver portDRV according to the present disclosure during the low steady-state phase PH4. Figure 15 shows the waveform of the internal endpoints of the driver portDRV according to the present disclosure, when the driver circuit enable signal EN is at a high logic level H (EN=H) and the external enable signal IQ_extEN for the additional current path is set to a low logic level L (IQ_extEN=L) to disable the additional current path add_curPATH, as the driver input signal inDAT changes. Figure 16 shows the waveform of the internal endpoints of the driver portDRV according to the present disclosure, when the driver circuit enable signal EN is at a high logic level H (EN=H) and the external enable signal IQ_extEN for the additional current path is set to a high logic level H (IQ_extEN=H) to enable the additional current path add_curPATH, as the driver input signal inDAT changes. Figure 17 shows a schematic diagram of the transistor path output impedance Rout_ts and the capacitor path output impedance Rout_cp added to the driver portDRV.Figure 18A is a schematic diagram of calculating the equivalent output impedance Rout_eq when the driver portDRV is equipped with transistor path output impedance Rout_ts and capacitor path output impedance Rout_cp, and the pull-up path is selected in the rising transient phase PH1 and the high steady-state phase PH2; Figure 18B is a schematic diagram of calculating the equivalent output impedance Rout_eq when the driver portDRV is equipped with transistor path output impedance Rout_ts and capacitor path output impedance Rout_cp, and the pull-down path is selected in the falling transient phase PH3 and the low steady-state phase PH4; Figure 19 is a schematic diagram of setting multiple parallel pull-up transistors upPM[1]~upPM[4], multiple parallel pull-down transistors dnNM[1]~dnNM[4], and multiple parallel transistor path output impedances Rout_ts[1]~Rout_ts[4] in the driver portDRV; Figure 20 is a schematic diagram showing the parallel compensation current paths comp_curPATH[1]~comp_curPATH[4] and parallel additional current paths add_curPATH[1]~add_curPATH[4] set up in response to the driver portDRV in Figure 19; and Figure 21 is a schematic diagram showing the low dropout regulator LDO formed by the driver portDRV according to the present disclosure using the comparator circuit cfCKT, the pull-up transistor upPM and the compensation circuit compCKT. portDRV: driver inDAT: Driver input signal EN: Enable signal for drive circuit portCltrMDL: Port control module cfCKT: Comparator circuit swGenCKT: Switching signal generation circuit SW_P: Pull-up path positive phase switching signal SWB_P: Pull-up path inversion switching signal SW_N: Pull-down path positive phase switching signal SWB_N: Pull-down path inversion switching signal cfin+: Input of the inverting comparator cfin-: Input of the inverting comparator cfout+: Output of the positive comparator cfout-: Output of the inverting comparator outSIG: Driver output signal Vcc: Supply voltage (terminal) Gnd: Grounding voltage (terminal) Vref: Reference voltage DRV: Drive circuit ND out :Driver output endpoint ND NG18 Pull-down transistor gate control terminal ND PG18 Pull-up transistor gate control terminal compCKT: Compensation circuit addEnCKT: Additional current enable circuit IQ_extEN: External enable signal for additional current path IQ_EN: Additional current path enable signal ND Cup Pull-up capacitor endpoint ND Cdn Pull-down capacitor endpoint ND mrr_pm PMOS current mirror bias terminal ND mrr_nm NMOS current mirror bias terminal ND comp_en Compensation circuit enable endpoint ND mrr_comp : Compensation circuit bias terminals

Claims

1. A driver includes: a switching signal generating circuit that generates a pull-up path positive phase switching signal, a pull-up path negative phase switching signal, a pull-down path positive phase switching signal, and a pull-down path negative phase switching signal based on a drive circuit enable signal and a driver input signal; a comparator circuit electrically connected to a first fixed voltage terminal and a second fixed voltage terminal, including: a positive comparator input terminal electrically connected to a driver output terminal of the driver; an negative comparator input terminal receiving a reference voltage, wherein the reference voltage is greater than the voltage of the second fixed voltage terminal and less than the voltage of the first fixed voltage terminal; a positive comparator output terminal; and an negative comparator output terminal electrically connected to a pull-up transistor gate terminal; a drive circuit including: a pull-up circuit electrically connected to the switching signal generating circuit and the comparator circuit, which selectively adjusts the voltage of the driver output terminal based on the pull-up path positive phase switching signal and the voltage of the pull-up transistor gate terminal; and... A pull-down circuit, electrically connected to the switching signal generation circuit, selectively adjusts the voltage of the driver output terminal based on the positive phase switching signal of the pull-down path and the voltage of the pull-down transistor gate terminal; and a port control module, electrically connected to the switching signal generation circuit, the comparator circuit, and the driver circuit, sets the voltage of the pull-up transistor gate terminal and the voltage of the pull-down transistor gate terminal based on the positive phase switching signal of the pull-up path, the negative phase switching signal of the pull-up path, the positive phase switching signal of the pull-down path, and the negative phase switching signal of the pull-down path. The driver as described in claim 1, wherein the pull-up circuit comprises: K pull-up transistors electrically connected to the gate terminal of the pull-up transistors and the first constant voltage terminal, wherein the driver output terminal is selectively set to the voltage of the first constant voltage terminal based on the voltage of the gate terminal of the pull-up transistors; a pull-up path transmission gate electrically connected to the switching signal generation circuit and the gate terminal of the pull-up transistors, wherein the gate is selectively turned on based on the pull-up path positive phase switching signal; and a pull-up path capacitor electrically connected to the pull-up path transmission gate, wherein the pull-down circuit comprises: K pull-down transistors electrically connected to the gate terminal of the pull-down transistors and the second constant voltage terminal, wherein the driver output terminal is selectively set to the voltage of the second constant voltage terminal based on the voltage of the gate terminal of the pull-down transistors; A pull-down path transmission gate is electrically connected to the switching signal generation circuit and the gate control terminal of the pull-down transistor, and is selectively turned on according to the positive phase switching signal of the pull-down path; and a pull-down path capacitor is electrically connected to the pull-up path capacitor and the pull-down path transmission gate, wherein the kth pull-up transistor of the K pull-up transistors is electrically connected to the kth pull-down transistor of the K pull-down transistors, where k and K are positive integers, and k is less than or equal to K. The driver as described in claim 2, wherein when the pull-up path transmission gate is turned on according to the pull-up path positive phase switching signal, the pull-down path transmission gate is turned off according to the pull-down path positive phase switching signal; and when the pull-up path transmission gate is turned off according to the pull-up path positive phase switching signal, the pull-down path transmission gate is turned on according to the pull-down path positive phase switching signal. The driver as described in claim 2, wherein the port control module includes: a reference current source electrically connected to the first constant voltage terminal, which provides a reference current; and a path selection circuit including: a pull-up path selection transmission gate electrically connected to the reference current source and the comparator circuit, which is selectively turned on according to the pull-up path positive phase switching signal, thereby allowing the reference current to flow to the comparator circuit; and a pull-down path selection transmission gate electrically connected to the reference current source and the pull-down circuit, which is selectively turned on according to the pull-down path positive phase switching signal, thereby allowing the reference current to flow to the pull-down circuit. The driver as described in claim 4, wherein when the drive circuit enable signal is equal to a first logic level, the pull-up path selector gate and the pull-down path selector gate are synchronously disconnected; and when the drive circuit enable signal is equal to a second logic level, the pull-up path selector gate and the pull-down path selector gate are alternately turned on. The driver as described in claim 4, wherein the port control module further comprises: a pull-up path disable transistor electrically connected to the first constant voltage terminal and the pull-up transistor gate terminal, which is selectively turned on according to the pull-up path positive phase switching signal, wherein when the pull-up path disable transistor is turned on, the pull-up path disable transistor sets the pull-up transistor gate terminal to the voltage of the first constant voltage terminal, thereby causing the K pull-up transistors to be turned off; and a pull-up path bypass transistor electrically connected to the first constant voltage terminal, the pull-up path transmission gate and the pull-up path capacitor, which is selectively turned on according to the pull-up path positive phase switching signal. The driver as described in claim 6, wherein when the drive circuit enable signal is equal to a first logic level, both the pull-up path disable transistor and the pull-up path bypass transistor are turned on, and the K pull-up transistors and the pull-up path transmission gate are all turned off; and when the drive circuit enable signal is equal to a second logic level, the pull-up path disable transistor and the pull-up path bypass transistor system are selectively turned on, wherein... When the enable signal of the driving circuit is equal to the second logic level, and when both the pull-up path disable transistor and the pull-up path bypass transistor are turned on, the K pull-up transistors and the pull-up path transmission gate are all turned off; and when the enable signal of the driving circuit is equal to the second logic level, and when both the pull-up path disable transistor and the pull-up path bypass transistor are turned off, the K pull-up transistors and the pull-up path transmission gate are all turned on. The driver as described in claim 4, wherein the port control module further comprises: a pull-down path disable transistor electrically connected to the second constant voltage terminal and the pull-down transistor gate terminal, which is selectively turned on according to the pull-down path inverting switching signal, wherein when the pull-down path disable transistor is turned on, the pull-down path disable transistor sets the pull-down transistor gate terminal to the voltage of the second constant voltage terminal, thereby causing the K pull-down transistors to be turned off; and a pull-down path bypass transistor electrically connected to the second constant voltage terminal, the pull-down path transmission gate and the pull-down path capacitor, which is selectively turned on according to the pull-down path inverting switching signal. The driver as described in claim 8, wherein when the drive circuit enable signal is equal to a first logic level, both the pull-down path disable transistor and the pull-down path bypass transistor are turned on, and the K pull-down transistors and the pull-down path transmission gate are all turned off; and when the drive circuit enable signal is equal to a second logic level, the pull-down path disable transistor and the pull-down path bypass transistor system are selectively turned on, wherein... When the enable signal of the driving circuit is equal to the second logic level, and when both the pull-down path disable transistor and the pull-down path bypass transistor are turned on, the K pull-down transistors and the pull-down path transmission gate are all turned off; and when the enable signal of the driving circuit is equal to the second logic level, and when both the pull-down path disable transistor and the pull-down path bypass transistor are turned off, the K pull-down transistors and the pull-down path transmission gate are all turned on. The driver as described in claim 2, wherein the driver circuit further comprises: a driver circuit enable transmission gate electrically connected to the pull-up path capacitor and the pull-down path capacitor, which is selectively turned on according to the driver circuit enable signal; a capacitor path output impedance electrically connected to the driver circuit enable transmission gate and the driver output terminal; and K transistor path output impedances, wherein a kth transistor path output impedance of the K transistor path output impedances is electrically connected to the kth pull-up transistor and the kth pull-down transistor. The driver as described in claim 10, wherein when the drive circuit enables the transmission gate to open, the pull-up circuit and the pull-down circuit stop setting the voltage at the output terminal of the driver, and the output terminal of the driver is in a floating state. The driver as described in claim 10, wherein when the drive circuit enables the transmission gate to conduct, the voltage at the output terminal of the driver changes with the input signal of the driver, wherein, When the driver input signal changes from a first logic level to a second logic level, the voltage at the driver output terminal rises from the voltage at the second constant voltage terminal to the reference voltage; when the voltage of the driver input signal remains equal to the second logic level, the voltage at the driver output terminal remains equal to the reference voltage; when the driver input signal changes from the second logic level to the first logic level, the voltage at the driver output terminal drops from the reference voltage to the voltage at the second constant voltage terminal; and when the driver input signal remains equal to the first logic level, the voltage at the driver output terminal remains equal to the voltage at the second constant voltage terminal. The driver as described in claim 2 further includes: a compensation circuit comprising: a compensation reference current path electrically connected to the port control module, the output of the positive comparator, the first constant voltage terminal, and the second constant voltage terminal, wherein a compensation reference current is selectively generated between the first constant voltage terminal and the second constant voltage terminal based on the voltage at the output of the positive comparator and the pull-up path inverting switching signal; and K compensation current paths electrically connected to the switching signal generation circuit, the port control module, the driver output terminal, and the second constant voltage terminal, wherein K compensation currents are selectively and synchronously generated between the driver output terminal and the second constant voltage terminal based on the pull-up path positive switching signal and the pull-up path inverting switching signal. The driver as described in claim 13, wherein the port control module further includes: a compensation circuit disable transistor electrically connected to the switching signal generation circuit, the compensation reference current path and the K compensation current paths, which selectively disconnects the compensation reference current path and the K compensation current paths according to the pull-up path inverted switching signal. The layer driver as described in claim 14, wherein the compensation circuit further comprises: K additional current paths electrically connected to the compensation reference current path, the K compensation current paths and the compensation circuit disable transistor, which selectively and synchronously generates the K additional currents according to the logic level of an additional current path enable signal, wherein the compensation circuit disable transistor selectively disconnects the K additional current paths according to the pull-up path inversion switching signal. The driver as described in claim 15 further includes: an additional current enable circuit electrically connected to the switching signal generation circuit and the K additional current paths, which receives the pull-up path positive phase switching signal from the switching signal generation circuit and an additional current path external enable signal from an external controller, wherein the additional current enable circuit determines the logic level of the additional current path enable signal based on the pull-up path positive phase switching signal and the additional current path external enable signal. The driver as described in claim 13, wherein the comparator circuit, the K pull-up transistors, and the compensation circuit together form a low-dropout regulator. The driver as described in claim 1, wherein the comparator circuit further comprises: a first current mirror, including: a first current mirror positive transistor electrically connected to the output of the positive comparator, the port control module, and the first constant voltage terminal; and a first current mirror inverting transistor electrically connected to the output of the inverting comparator, the port control module, and the first constant voltage terminal; a differential input circuit, including: a positive differential input transistor electrically connected to the output of the positive comparator and the input of the positive comparator; and an inverting differential input transistor electrically connected to the output of the inverting comparator and the input of the inverting comparator; and a second current mirror, including: a second current mirror positive transistor electrically connected to the port control module and the second constant voltage terminal; and a second current mirror inverting transistor electrically connected to the port control module, the positive differential input transistor, the inverting differential input transistor, and the second constant voltage terminal. The driver as described in claim 18, wherein the port control module further comprises: a first current mirror disabling transistor electrically connected to the first fixed voltage endpoint, the switching signal generation circuit, the first current mirror positive-phase transistor, and the first current mirror negative-phase transistor, wherein the first current mirror disabling transistor selectively conducts the voltage of the first fixed voltage endpoint to the output of the positive-phase comparator according to the pull-up path positive-phase switching signal, thereby disconnecting the first current mirror positive-phase transistor and the first current mirror negative-phase transistor; and a second current mirror disabling transistor electrically connected to the second fixed voltage endpoint, the switching signal generation circuit, the second current mirror positive-phase transistor, and the second current mirror negative-phase transistor, wherein the second current mirror positive-phase transistor selectively conducts the voltage of the second fixed voltage endpoint to the second current mirror positive-phase transistor and the second current mirror negative-phase transistor according to the pull-up path negative-phase switching signal, thereby disconnecting the second current mirror positive-phase transistor and the second current mirror negative-phase transistor, wherein the first current mirror disabling transistor and the second current mirror disabling transistor are synchronously turned on or off. The driver as described in request item 1, wherein, When the enable signal of the driving circuit is a first logic level, the switching signal generating circuit sets the positive phase switching signal of the pull-up path and the positive phase switching signal of the pull-down path to the first logic level, and sets the negative phase switching signal of the pull-up path and the negative phase switching signal of the pull-down path to a second logic level; and when the enable signal of the driving circuit is the second logic level, the switching signal generating circuit sets the positive phase switching signal of the pull-up path and the negative phase switching signal of the pull-down path according to the logic level of the driver input signal, and sets the negative phase switching signal of the pull-up path and the positive phase switching signal of the pull-down path according to the negative logic level of the driver input signal.

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