Signal generator and method for verifying asynchronous interface circuit

Abstract

A signal generator and a method for verifying an asynchronous interface circuit are provided, where the signal generator includes a frame modulator, a clock generator, an interface selector and a checking module. The frame modulator generates a modulated signal according to a frame control parameter, and the clock generator generates a clock signal according to a clock control parameter. The interface selector generate a receiving test signal according to an interface control parameter, the modulated signal and the clock signal, where the signal generator utilize a reference model to generate a reference signal according to the receiving test signal, and the asynchronous interface circuit generates a transmitting test signal according to the receiving test signal. In addition, the checking module generates at least one verification result according to the reference signal and the transmitting test signal.

Description

[Technical Field]

[0001] This invention relates to the verification of digital chips, and more particularly to a signal generator and method for verifying an asynchronous interface circuit (e.g., an asynchronous interface circuit for transmitting Ethernet packets). [Previous Technology]

[0002] In a communication network, Ethernet packet transmission typically involves multiple asynchronous interfaces. Compared to synchronous interfaces, asynchronous interfaces are more prone to data packet transmission errors or loss, leading to degraded communication quality or even network connection interruption. Therefore, chips with asynchronous interfaces must undergo thorough verification before mass production to ensure proper operation of the asynchronous interfaces within the chip. However, the verification methods of related technologies typically verify the entire chip, making it difficult to perform complete verification of the asynchronous interfaces within it (e.g., simulating various possible error scenarios), and lacking testing to push the performance limits of the asynchronous interfaces. Furthermore, related technologies usually only allow for complete verification of the asynchronous interfaces after chip manufacturing is complete, resulting in a lack of sufficient adjustment and correction methods when problems with the asynchronous interfaces are discovered, leading to inefficient chip design, verification, and correction processes.

[0003] Therefore, a novel verification mechanism is needed to enable specialized testing of asynchronous interfaces in the early stages of product development, thereby improving verification efficiency and shortening the chip development cycle. [Summary of the Invention]

[0004] The purpose of this invention is to provide a signal generator and method for verifying an asynchronous interface circuit (e.g., an asynchronous interface circuit for transmitting Ethernet packets) to solve the problems of the related art without or with minimal side effects.

[0005] At least one embodiment of the present invention provides a signal generator for verifying an asynchronous interface circuit, wherein the signal generator includes a frame modulator, a clock generator, an interface selector, and a verification module. The frame modulator is used to generate a modulation signal based on at least one frame control parameter, and the clock generator is used to generate a clock signal based on at least one clock control parameter. The interface selector is used to generate a receive test signal to the asynchronous interface circuit based on at least one interface control parameter, the modulation signal, and the clock signal, wherein the signal generator uses a reference model to generate a reference signal based on the receive test signal, and the asynchronous interface circuit generates a transmit test signal based on the receive test signal. Furthermore, the verification module is used to generate at least one verification result based on the reference signal and the transmit test signal.

[0006] At least one embodiment of the present invention provides a method for verifying an asynchronous interface circuit, wherein the asynchronous interface circuit is coupled to a signal generator. The method includes: generating a modulation signal using a frame modulator of the signal generator according to at least one frame control parameter; generating a clock signal using a clock generator of the signal generator according to at least one clock control parameter; generating a receive test signal to the asynchronous interface circuit using an interface selector of the signal generator according to at least one interface control parameter, the modulation signal, and the clock signal; generating a reference signal using a reference model of the signal generator according to the receive test signal; generating a transmit test signal using the asynchronous interface circuit according to the receive test signal; and generating at least one verification result using a check module of the signal generator according to the reference signal and the transmit test signal.

[0007] The signal generator and related methods provided in the embodiments of the present invention can simulate various packet reception conditions of the asynchronous interface circuit by setting different control parameters, thereby ensuring that the asynchronous interface circuit can operate properly in these situations and testing the performance limits of the asynchronous interface. Furthermore, the embodiments of the present invention do not significantly increase additional costs. Therefore, the present invention can solve the problems of related technologies without or with minimal side effects.

Implementation Method

[0008] The main function of an Ethernet switch chip is to receive and forward data frames. The Ethernet uses the IEEE 802.3 local area network standard. Figure 1 is a schematic diagram of the structure of a media access control (MAC) frame 10 of an Ethernet according to an embodiment of the present invention. The MAC frame 10 may include an inter-frame gap (IFG) DIFG, a preamble (DPREAMB), a start of frame delimiter (SDF) (DSFD), a frame payload (DPLOAD), and a checksum (DCRC). The inter-frame gap (IFG) is an idle time reserved between frames to allow the circuit to process other processes, and no valid data is transmitted during this idle time. In addition, the length of the inter-frame gap (IFG) defined in the local area network standard IEEE 802.3 must be greater than or equal to 12 bytes, and the length of the preamble (DPREAMB) must be equal to 7 bytes.

[0009] Figure 2 is a schematic diagram of an asynchronous interface circuit 20 according to one embodiment of the present invention. The asynchronous interface circuit 20 shown in Figure 2 simultaneously illustrates a first data path (as shown by data DATA0RX and DATA0TX) and a second data path (as shown by data DATA1RX and DATA1TX). Specifically, the receiving and transmitting operations of the asynchronous interface circuit 20 can be considered as two independent actions, wherein the clock signals for receiving and transmitting the asynchronous interface circuit 20 can be asynchronous and correspond to different interface types. For example, on the first data path, the asynchronous interface circuit 20 can receive data DATA0RX based on the clock signal CLK0RX and transmit data DATA0TX based on the clock signal CLK0TX, wherein the clock signals CLK0RX and CLK0TX are asynchronous. For example, on the second data path, the asynchronous interface circuit 20 can receive data DATA1RX based on the clock signal CLK1RX and transmit data DATA1TX based on the clock signal CLK1TX, where the clock signals CLK1RX and CLK1TX are asynchronous. Therefore, when the frequency of the clock signals received and transmitted by the asynchronous interface circuit 20 is inaccurate, the probability of errors will increase significantly.

[0010] Figure 3 is a schematic diagram of a MAC frame (e.g., MAC frame 10) transmitted between two devices through a physical medium according to an embodiment of the present invention. As shown in Figure 3, the transmitting end can process the MAC frame 10 to be transmitted sequentially through the application layer, presentation layer, conferencing layer, transport layer, network layer, data link layer and physical layer. In particular, the physical layer encodes / decodes the MAC frame 10 into a bit stream so that the physical medium can transmit the bit stream to the receiving end. After receiving the bit stream, the receiving end can perform corresponding processing sequentially through the physical layer, data link layer, network layer, transport layer, conferencing layer, presentation layer and application layer. It should be noted that the interface type used to transmit MAC frame 10 may include (but is not limited to) media-independent interface (MII), gigabit media-independent interface (GMII), and 10-gigabit media-independent interface (XGMII). To accommodate the communication protocols of these interface types, the lengths of the inter-frame gap (DIFG) and / or preamble (DPREAMB) in MAC frame 10 may be increased or decreased after processing by the physical layer circuitry. In particular, MAC frame 10 may pass through many module circuits during transmission in the system, and these module circuits may use different interface types. To ensure that MAC frame 10 can pass smoothly through each module circuit, asynchronous interface circuit 20 needs to have interface type conversion capabilities (e.g., GMII to XGMII, XGMII to GMII, etc.). The length of the inter-frame gap (DIFG) is an important parameter for evaluating communication quality, and smaller fluctuations in the length of the DIFG indicate better communication quality.

[0011] Figure 4 is a schematic diagram of four communication scenarios, such as 40A, 40B, 40C, and 40D, according to an embodiment of the present invention. When the system operates at full speed, the theoretical average length of the inter-frame gap (DIFG) is 12 bytes. Although the average inter-frame gap length of each of the communication scenarios 40A, 40B, 40C, and 40D shown in Figure 4 is 12 bytes, the communication quality of these scenarios is not the same. Communication scenario 40A is a standard communication scenario that conforms to the communication protocol requirements. The inter-frame gap length of communication scenario 40B fluctuates around 12 bytes, while the inter-frame gap length of communication scenario 40C fluctuates more significantly than that of communication scenario 40B. Furthermore, although the fluctuation amplitude of communication scenario 40D is the same as that of communication scenario 40C, communication scenario 40D has consecutive short inter-frame gaps (e.g., two consecutive 6-byte inter-frame gaps), which have the greatest impact on the circuit. Therefore, communication quality is best in communication scenario 40A, second best in communication scenario 40B, third best in communication scenario 40C, and worst in communication scenario 40D. Additionally, MAC frame 10 may contain some erroneous bytes. When such non-standard frames are transmitted between multiple communication devices, it cannot be guaranteed that each communication device can correctly identify and forward these non-standard frames, thus affecting communication quality.

[0012] As can be seen from the above, the MAC frame 10 received by the asynchronous interface circuit 20 may have various types of conditions. In addition to correctly forwarding the MAC frame 10, the asynchronous interface circuit 20 sometimes needs to provide functions to improve communication quality (such as adjusting the length of the MAC frame 10's inter-frame gap DIFG and / or preamble DPREAMB) to reduce the impact of the MAC frame 10 on other communication devices in the network.

[0013] Figure 5 is a schematic diagram of verifying asynchronous interface circuit 50 by means of a signal generator 500 according to an embodiment of the present invention, wherein asynchronous interface circuit 50 is coupled to signal generator 500, and asynchronous interface circuit 50 may be an example of asynchronous interface circuit 20 shown in Figure 2. As shown in Figure 5, the signal generator 500 may include a frame modulator such as a non-standard frame modulator 510, a scrambler 520, a clock generator 530, an interface selector 540, a monitor 550, a reference model 560, a monitor 570, and a check module 580 (e.g., a check circuit), wherein the scrambler 520 is coupled between the non-standard frame modulator 510 and the interface selector 540, the clock generator 530 is coupled to the interface selector 540, the monitor 550 is coupled to the interface selector 540, the reference model 560 is coupled to the monitor 550, and the check module 580 is coupled to the reference model 560 and the monitor 570. In this embodiment, the non-standard frame modulator 510 is used to modulate a standard frame F0 according to at least one frame control parameter, such as control parameter P2, to generate a modulation signal F1, and the clock generator 530 is used to generate a clock signal CLK according to at least one clock control parameter, such as control parameter P1. Additionally, the interface selector 540 is used to generate a receive test signal FRX to the asynchronous interface circuit 50 according to at least one interface control parameter, such as control parameter P3, the modulation signal F1, and the clock signal CLK. The signal generator 500 can use the reference model 560 to generate a reference signal D0 based on the receive test signal FRX, and the asynchronous interface circuit 50 can generate a transmit test signal FTX based on the receive test signal FRX. The inspection module is used to generate at least one verification result, such as a comparison result R1 and an analysis result R2, based on the reference signal D0 and the transmit test signal FTX.

[0014] In this embodiment, the scrambler 520 is used to scramble the content of the modulation signal F1 to generate a scrambled signal F2. The interface selector 540 can generate a receive test signal FRX based on the control parameter P3, the scrambled signal F2, and the clock signal CLK. Additionally, monitors 550 and 570 are used to monitor the receive test signal FRX and the transmit test signal FTX, respectively. For example, monitor 550 can generate a receive monitoring signal DREF by monitoring and sampling the receive test signal FRX, and monitor 570 can generate a transmit monitoring signal D1 by monitoring and sampling the transmit test signal FTX. Specifically, the reference model 560 is used to simulate the operation of the asynchronous interface circuit 50. The reference signal D0 output by the reference model 560 can be considered as the theoretical value of the transmit monitoring signal D1 when the asynchronous interface circuit 50 correctly forwards the receive test signal FRX into the transmit test signal FTX.

[0015] In this embodiment, the inspection module 580 may include a comparison module 581 and an analyzer 582. Specifically, the comparison module 581 (which can be considered a scoreboard) is used to check whether the reference signal D0 and the transmission test signal FTX (especially the transmission monitoring signal D1) are consistent to generate a comparison result R1. In addition, when the comparison result R1 indicates that the reference signal D0 and the transmission test signal FTX (especially the transmission monitoring signal D1) are consistent, the analyzer 582 can generate an analysis result R2 based on the multiple inter-frame gaps in the transmission test signal FTX. For example, the comparison module 581 may forward the transmission monitoring signal D1 to the analyzer 582 as a transmission monitoring signal D2 along with certain control parameters, and the analyzer 582 can generate the analysis result R2 based on the inter-frame gap information carried in the transmission monitoring signal D2 (e.g., the multiple inter-frame gaps in the transmission test signal FTX).

[0016] In some embodiments, one or more of the non-standard frame modulator 510, scrambler 520, clock generator 530, interface selector 540, monitor 550, reference model 560, monitor 570, and inspection module 580 (e.g., comparison module 581 and analyzer 582 therein) may be implemented using hardware (e.g., circuitry). In some embodiments, one or more of the non-standard frame modulator 510, scrambler 520, clock generator 530, interface selector 540, monitor 550, reference model 560, monitor 570, and inspection module 580 (e.g., comparison module 581 and analyzer 582 therein) may be implemented using firmware. In some embodiments, one or more of the non-standard frame modulator 510, scrambler 520, clock generator 530, interface selector 540, monitor 550, reference model 560, monitor 570, and inspection module 580 (e.g., comparison module 581 and analyzer 582 therein) may be implemented in software.

[0017] Since the receiving clock and transmitting clock of the asynchronous interface circuit 50 come from different clock sources (e.g., two independent quartz oscillators), various non-ideal conditions may exist in practice. In this embodiment, the control parameter P1 may include the control parameters ppm_type and Nppm, wherein the clock generator 530 can control the frequency offset mode of the generated clock signal CLK according to the control parameter ppm_type, and control the frequency offset amount of the clock signal CLK according to the control parameter Nppm. For example, when the clock generator 530 generates the clock signal CLK in the first frequency offset mode according to the control parameter ppm_type, the frequency offset amount of the clock signal CLK may be a typical frequency offset amount in the range of 200 parts per million (ppm). As another example, when the clock generator 530 generates the clock signal CLK in the second frequency offset mode according to the control parameter ppm_type, the frequency offset amount of the clock signal CLK may be a random value (e.g., Nppm) in the range of 200 ppm. Specifically, setting the clock generator 530 to the first frequency offset mode allows for rapid verification of the operation of the asynchronous interface circuit 50 under typical frequency offset, while setting the clock generator 530 to the second frequency offset mode better reflects the actual operation of a quartz oscillator. Specifically, when the standard frequency of the clock signal CLK is FREQ0 and the frequency offset of the clock signal CLK is Nppm, the offset frequency FREQ1 of the clock signal CLK can be calculated using formula (1) as follows: Formula (1):

[0018] In addition, control parameter P2 may include control parameters cfg_ifg_min, cfg_ifg_max, cfg_ifg_avg, cfg_ifg_tx_min, cfg_preamble_size, cfg_pkt_len_min, cfg_pkt_len_max, cfg_pkt_len_avg, NCRC, symbol_err, symbol_err_point, check_ifg_min, check_ifg_max, check_ifg_avg, check_ifg_offset, cfg_var_ifg_min, and cfg_var_ifg_max. The control parameter cfg_ifg_min may represent the minimum inter-frame gap length of the transmitted data packet (e.g., modulation signal F1 or receive test signal FRX generated based on modulation signal F1), and the control parameter cfg_ifg_max may represent the minimum inter-frame gap length of the transmitted data packet. The parameters are: maximum interframe gap length of the data packet; average interframe gap length of the transmitted data packet; minimum interframe gap length of the forwarded data packet (e.g., reference signal D0 or transmission monitoring signal D1); preamble size of the transmitted data packet; minimum packet length of the transmitted data packet; maximum packet length of the transmitted data packet; average packet length of the transmitted data packet; NCRC checksum of the transmitted data packet; symbol_err indicating whether the transmitted data packet has been inserted with symbol errors such as the aforementioned error byte; and symbol_err_point indicating the position of the inserted symbol error in the transmitted data packet. In addition, the control parameters check_ifg_min, check_ifg_max, check_ifg_avg, check_ifg_offset, cfg_var_ifg_min, and cfg_var_ifg_max can be transmitted to the inspection module 580 through the internal signal path of the signal generator 500 (e.g., through the reference model 560) for comparison modules 581 and 582 to compare and analyze.

[0019] Additionally, the interface selector 540 can determine the communication protocol (e.g., a communication protocol conforming to MII, GMII, or XGMII) for receiving the test signal FRX based on the control parameter P3, so as to transmit the data packets in the scrambled signal F2 transmitted based on the clock signal CLK to the asynchronous interface circuit 50 using the specified communication protocol. In particular, MII, GMII, and XGMII have different bit widths and are used in communication scenarios at different speeds, so different frequency errors can be corresponded to different interface types and different frequency offsets.

[0020] In this embodiment, the signal generator 500 can generate various Ethernet packets (e.g., MAC frame 10) according to the settings of control parameters P1, P2, and P3 to verify the asynchronous interface circuit 50's processing of different Ethernet packets. The signal generator 500 can establish a verification platform and execute each step based on the Universal Verification Methodology (UVM). First, the signal generator 500 can define control parameters P1 and P2 according to the characteristics of the Ethernet packet to be tested to modify the standard frame F0 into the required test packet. As shown in Figure 6, the MAC frame 60 has an inter-frame gap length between cfg_ifg_min and cfg_ifg_max, a total length of the preamble and start-of-frame character of the MAC frame 60 of 8 bytes, and the length of each packet of the MAC frame 60 (e.g., packet A and packet B) between cfg_pkt_len_min and cfg_pkt_len_max. Next, the signal generator 500 can select the required interface type in the interface selector 540 via control parameter P3 to transmit the test packet to the asynchronous interface circuit 50 using the specified communication protocol, and transmit the test packet to the reference model 560 via the monitor 550. The comparison module 581 in the inspection module 580 can perform a byte-by-byte comparison between the packet output by the asynchronous interface circuit 50 and the packet processed by the reference model to check whether the asynchronous interface circuit 50 can correctly forward the packet content. For example, the packet inspection items may include: checking whether the preamble (e.g., the preamble DPREAMB shown in Figure 1) remains unchanged; checking whether the content of each byte of the packet remains unchanged (e.g., the frame payload DPLOAD shown in Figure 1); the packet length (e.g., the length of MAC frame 10 shown in Figure 1) remains unchanged; the checksum (e.g., the checksum DCRC shown in Figure 1) remains unchanged; if there is a symbol error, the position of the symbol error remains unchanged; and the packet is not lost or out of order. When any of the above checks indicates that any characteristic of the packet has changed, the comparison result R1 generated by the comparison module 581 can indicate that the packet content has not been forwarded correctly. When each of the above checks indicates that none of the packet characteristics have changed, the comparison result R1 generated by the comparison module 581 can indicate that the packet content has been forwarded correctly, and the analyzer 582 can further record the length of the inter-frame gap of each packet (e.g., the length of the inter-frame gap DIFG shown in Figure 1) and perform analysis accordingly to generate the analysis result R2.

[0021] In some embodiments, the analyzer 582 may perform a first analysis operation, such as checking whether each of the plurality of inter-frame gaps, such as N inter-frame gaps IFG1, IFG2, ... and IFGN, in the transmission test signal FTX (e.g., transmission monitoring signal D1) matches the corresponding inter-frame gap in the reference signal D0, to generate a first analysis sub-result in the analysis result R2, wherein when any inter-frame gap IFGn (n is a positive integer in the interval [1, N]) in the transmission test signal FTX (e.g., transmission monitoring signal D1) does not match the corresponding inter-frame gap in the reference signal D0, the analyzer 582 may issue an error reminder through the first analysis sub-result.

[0022] In some embodiments, the analyzer 582 may perform a second analysis operation, such as checking whether the average values ​​of the inter-frame gaps IFG1, IFG2, ..., and IFGN conform to the theoretical values ​​determined by control parameter P2 (e.g., control parameters cfg_ifg_avg and / or cfg_pkt_len_avg) and control parameter P1 (e.g., control parameter Nppm), to generate a second analysis sub-result of analysis result R2. Specifically, when MAC frame 60 is forwarded through the synchronization interface circuit, the average values ​​of its inter-frame gaps IFG1, IFG2, ..., and IFGN are theoretically equal to the control parameter cfg_ifg_avg. When MAC frame 60 is forwarded through the asynchronous interface circuit (e.g., asynchronous interface circuit 50), the average values ​​of its inter-frame gaps IFG1, IFG2, ..., and IFGN will theoretically be close. Therefore, when the average values ​​of the inter-frame gaps IFG1, IFG2, ..., and IFGN deviate from the above theoretical values ​​(e.g., the difference is greater than a predetermined value), the analyzer 582 may issue an error warning through the second analysis sub-result.

[0023] In some embodiments, the analyzer 582 may perform a third analysis operation, such as checking whether each of the frame gaps IFG1, IFG2, ... and IFGN is not less than a minimum frame gap length determined by the control parameter P2 (e.g., the control parameter check_ifg_min), to generate a third analysis sub-result of the analysis result R2. When the length of any frame gap IFGn of the frame gaps IFG1, IFG2, ... and IFGN is less than check_ifg_min, the analyzer 582 may issue an error warning through the third analysis sub-result.

[0024] In some embodiments, the analyzer 582 may perform a fourth analysis operation, such as checking whether the inter-frame gaps IFG1, IFG2, ..., and IFGN contain multiple consecutive offset inter-frame gaps, to generate a fourth analysis sub-result of the analysis result R2, wherein the length of each of the multiple consecutive offset inter-frame gaps falls within an offset interval determined by the control parameter P2. For example, the offset interval may be defined as the interval between check_ifg_min and (check_ifg_min + check_ifg_offset), and when the length of the multiple consecutive inter-frame gaps contained in the inter-frame gaps IFG1, IFG2, ..., and IFGN falls within the interval between check_ifg_min and (check_ifg_min + check_ifg_offset), the analyzer 582 may issue an error warning through the fourth analysis sub-result.

[0025] In some embodiments, the analyzer 582 may perform a fifth analysis operation, such as calculating the variance S2 of the inter-frame gaps IFG1, IFG2, ... and IFGN to produce a fifth analysis sub-result of the analysis result R2, wherein a larger variance S2 indicates a greater fluctuation in the length of the inter-frame gaps IFG1, IFG2, ... and IFGN, i.e., a worse communication quality. The method for calculating the variance S2 of the inter-frame gaps IFG1, IFG2, ... and IFGN is shown in the following formulas (2), (3) and (4). Formula (2): Formula (3): Formula (4):

[0026] Formula (2) calculates the deviation value of the inter-frame gap of the nth frame (analyzer 582 allows the inter-frame gap IFGn to offset between cfg_var_ifg_min and cfg_var_ifg_max), formula (3) calculates the average deviation value of inter-frame gaps IFG1, IFG2, ... and IFGN, and formula (4) calculates the variation S2 of inter-frame gaps IFG1, IFG2, ... and IFGN. Based on the above packet configuration and the corresponding comparison / analysis mechanism, signal generator 500 can test the performance of asynchronous interface circuit 50 when receiving packets with various characteristics.

[0027] In one embodiment, the signal generator 500 can perform a standard frame Ethernet packet pass-through synchronization interface test on the asynchronous interface circuit 50. Specifically, the signal generator 500 can construct a clock synchronization scenario based on control parameter P1, and construct standard Ethernet packets (e.g., Ethernet packets with 12-byte inter-frame gaps and packet lengths falling between 64 bytes and 1518 bytes) based on control parameter P2. The comparison module 581 can determine whether the Ethernet packets output by the reference model 560 and the Ethernet packets output by the asynchronous interface circuit 50 are consistent, in order to check whether the Ethernet packets can be correctly forwarded by the asynchronous interface circuit 50. After the check by the comparison module 581, the analyzer 582 can perform the above-mentioned first analysis operation to check the length of each inter-frame gap.

[0028] In one embodiment, the signal generator 500 can perform standard frame Ethernet packet passing asynchronous interface testing on the asynchronous interface circuit 50. Specifically, the signal generator 500 can construct a clock asynchronous scenario based on control parameter P1, and construct standard Ethernet packets (e.g., Ethernet packets with a frame gap of 12 bytes and a packet length falling between 64 bytes and 1518 bytes) based on control parameter P2. The comparison module 581 can determine whether the Ethernet packets output by the reference model 560 and the Ethernet packets output by the asynchronous interface circuit 50 are consistent, in order to check whether the Ethernet packets can be correctly forwarded by the asynchronous interface circuit 50. After passing the check by the comparison module 581, the analyzer 582 can perform the frame gap related checks of the above-mentioned second analysis operation, third analysis operation, fourth analysis operation, and fifth analysis operation.

[0029] In one embodiment, the signal generator 500 can test the interface conversion of standard frame Ethernet packets through the asynchronous interface circuit 50. Specifically, the signal generator 500 can construct a clock asynchronous scenario based on control parameter P1, and construct standard Ethernet packets (e.g., Ethernet packets with a frame gap of 12 bytes and a packet length falling between 64 bytes and 1518 bytes) based on control parameter P2. Additionally, the signal generator 500 can transmit Ethernet packets to the asynchronous interface circuit 50 using a first type interface (e.g., GMII) and receive Ethernet packets from the asynchronous interface circuit 50 using a second type interface (e.g., XGMII) based on control parameter P3 to check the interface type conversion function of the asynchronous interface circuit 50. In particular, the comparison module 581 can determine whether the content and characteristics of the Ethernet packets have changed due to the interface type conversion of the asynchronous interface circuit 50. After the comparison module 581 performs the checks, the analyzer 582 can perform the frame gap checks of the second, third, fourth and fifth analysis operations described above.

[0030] In communication networks, after Ethernet packets pass through various asynchronous interfaces, it is difficult to maintain the inter-frame gap within them at the standard length (e.g., 12 bytes). If the inter-frame gap is too long, it will affect the transmission rate, while if the inter-frame gap is too short, there is a risk of data collision and loss. Furthermore, when the frequency of the quartz oscillator is inaccurate, variations in the length of the transmitted packets can also affect the asynchronous interface. (For example, when the frequency offset is too large and the packet length is too long, the asynchronous interface cannot compensate in time during the inter-frame interval, leading to empty or full buffer space and errors.) Additionally, due to limitations in the transmission system design, one or more frames may inevitably be corrupted during transmission (e.g., bit errors occur), causing the receiving end to receive erroneous data. For example, Figure 7 is a schematic diagram of an encoding error in the physical layer of GMII according to an embodiment of the present invention, where the clock signal RX_CLK can be an example of the clock signal CLK shown in Figure 5, the data signal RXD can be an example of the Ethernet packet in the receive test signal FRX shown in Figure 5, and the control signal RX_DV has a high logic level (e.g., logic value "1"). The interval can represent the period when the data signal RXD is valid, and the interval where the error indication signal RX_ER has a high logic level can represent the location of the symbol error in the data signal RXD. Specifically, when an error occurs in the encoding of the physical layer, the media access control layer can pull the error indication signal RX_ER to a high logic level during data reception to indicate the location of the symbol error in the data signal RXD. Through the configuration of control parameters P1, P2, and P3, the signal generator 500 can generate non-standard frames for various situations (e.g., the inter-frame gap is not equal to 12 bytes, the packet length does not fall within the range of 64 bytes and 1518 bytes, or there is a symbol error) to test whether the packet forwarding of the asynchronous interface circuit 50 is normal, and use the analyzer 582 to determine the communication quality of the asynchronous interface circuit 50 forwarding non-standard frames.

[0031] In one embodiment, the signal generator 500 can test the asynchronous interface circuit 50 for non-standard frame Ethernet packets passing through the asynchronous interface. Specifically, the signal generator 500 can construct a clock asynchronous scenario based on control parameter P1, and construct the characteristics of the Ethernet packets (e.g., inter-frame gap length, packet length, etc.) based on control parameter P2. The comparison module 581 can determine whether the Ethernet packets output by the reference model 560 and the Ethernet packets output by the asynchronous interface circuit 50 are consistent, in order to check whether the Ethernet packets can be correctly forwarded by the asynchronous interface circuit 50 (e.g., checking whether the packet content has changed, checking whether the packet has been lost). After the check by the comparison module 581, the analyzer 582 can perform the inter-frame gap related checks of the above-mentioned second analysis operation, third analysis operation, fourth analysis operation, and fifth analysis operation. After passing the above checks, the control parameters symbol_err and symbol_err_point can be further configured (e.g., by pulling the control parameter symbol_err to a logic value "1" to enable the insertion of symbol errors), so that the signal generator 500 can further generate Ethernet packets with symbol errors at specific positions based on the control parameters symbol_err and symbol_err_point. The comparison module 581 can determine whether the Ethernet packets output by the reference model 560 and the Ethernet packets output by the asynchronous interface circuit 50 are consistent, in order to check whether the Ethernet packets can be correctly forwarded by the asynchronous interface circuit 50 (e.g., checking whether the packet content has changed or whether the position of the symbol error has changed).

[0032] Furthermore, non-standard frames are more prone to errors when passing through different interface types. For example, in the case of GMII to XGMII conversion, the position of the start-of-frame symbol DSFD needs to be adjusted, and the length of the inter-frame gap DIFG will change, causing the frequency offset of the clock signal CLK to have a serious impact on the inter-frame gap DIFG. Therefore, it is necessary to ensure that the asynchronous interface circuit 50 does not change the content of the MAC frame 10 (e.g., the length of the MAC frame 10, the checksum DCRC of the MAC frame 10, whether additional errors are generated, whether the position of the symbol error is changed, etc.) when performing interface type conversion.

[0033] In one embodiment, the signal generator 500 can test the interface conversion of non-standard frame Ethernet packets through the asynchronous interface circuit 50. Specifically, the signal generator 500 can construct a clock asynchronous scenario based on control parameter P1, and enable the interface type conversion function (e.g., GMII to XGMII) based on control parameter P3. In addition, the signal generator 500 can construct the characteristics of the Ethernet packets (e.g., inter-frame length, packet length, etc.) based on control parameter P2. The comparison module 581 can determine whether the content and characteristics of the Ethernet packets have changed when forwarded through the asynchronous interface circuit 50, and check whether the Ethernet packets are lost. After passing the above checks, the control parameters symbol_err and symbol_err_point can be further set (e.g., the control parameter symbol_err can be pulled to the logic value "1" to enable the insertion of symbol errors), so that the signal generator 500 can further generate Ethernet packets with symbol errors at specific positions based on the control parameters symbol_err and symbol_err_point. The comparison module 581 can check whether the Ethernet packets can be correctly forwarded by the asynchronous interface circuit 50, and in particular, it can check whether Ethernet packets with symbol errors can be correctly forwarded (e.g., checking whether the packet content has changed or whether the position of the symbol error has changed). After passing the check of the comparison module 581, the analyzer 582 can perform the inter-frame checks of the second, third, fourth, and fifth analysis operations described above.

[0034] In addition, the minimum frame gap of Ethernet is to ensure the stability and performance of data transmission. When the frame gap is too small, collisions may occur between MAC frames, resulting in data loss. For example, in the asynchronous first-in first-out (FIFO) register in the asynchronous interface 50, when the read rate and write rate are inconsistent, data overflow or data underflow may occur.

[0035] Figure 8 is a schematic diagram of a data overflow in an asynchronous FIFO register 80 due to the write rate being greater than the read rate, according to an embodiment of the present invention. The read pointer is marked on the left and the write pointer is marked on the right to indicate that the write rate is greater than the read rate. As shown in Figure 8, data0, data1, data2, data3, data4, ..., data22 and data23 are written to the addresses addr0, addr1, addr2, addr3, addr4, ..., addr22, addr23 of the asynchronous FIFO register 80, respectively. The new data0, data1, data2 and data3 (labeled as "data0(new)", "data1(new)", "data2(new)" and "data3(new)" in Figure 8 for ease of understanding) have been written to the asynchronous FIFO register 80 and the new data4 is about to be written, but the old data4 has not yet been read, resulting in data overflow (e.g., the old data4 is lost). Specifically, the following formula (5) can be used to determine whether data overflow will occur: Formula (5):

[0036] When the result of formula (5) is greater than or equal to 0, it indicates that data overflow will not occur; when the result of formula (5) is less than 0, it indicates that data overflow will occur. Additionally, the following formula (6) can calculate the time when data overflow occurs in different types of Ethernet packets when the write rate is greater than the read rate (overflowcnt1, indicating that data overflow occurs in the overflowcnt1th packet): Formula (6):

[0037] Where Ndeep represents the depth parameter of the asynchronous FIFO register (e.g., asynchronous FIFO register 80), and when the width of the asynchronous FIFO register (e.g., asynchronous FIFO register 80) is M, it means that this asynchronous register can store at most Ndeep M bits of data. Additionally, WL represents the water level parameter of the asynchronous FIFO register (e.g., asynchronous FIFO register 80), where the read operation of this asynchronous FIFO register is performed only after WL clock cycles following the writing of the Ethernet packet. Based on calculations using formulas (5) and (6), it can be seen that when the average length of an Ethernet packet (cfg_pkt_len_avg) is 64 bytes, the average length of an inter-frame gap (cfg_ifg_avg) is 5 bytes, the water level parameter WL is 3, the depth parameter Ndeep is 24, and the target length of the inter-frame gap to be compensated (cfg_ifg_tx_min) is 5 bytes, theoretically, data overflow will occur in the 1420th Ethernet packet with a frequency offset of 200 ppm. Furthermore, when the average length of an inter-frame gap (cfg_ifg_avg) is 6 bytes and other conditions remain unchanged, theoretically, data overflow will not occur.

[0038] In one embodiment, the signal generator 500 can verify the limit value of the inter-frame gap based on the case where writing is faster than reading. Specifically, the signal generator 500 can construct a case where writing is faster than reading based on the control parameter P1, and construct the characteristics of the Ethernet packet (e.g., inter-frame gap length, packet length, etc., especially setting the inter-frame gap length to cfg_ifg_min) based on the control parameter P2. The comparison module 581 can determine whether the condition of the Ethernet packet output by the asynchronous interface circuit 50 (e.g., whether data overflow occurs, and when data overflow occurs) matches the theoretical value provided by the reference model 560 (e.g., the theoretical value calculated by formulas (5) and (6)). In addition, after adjusting the control parameter cfg_ifg_min, the signal generator 500 can again construct the characteristics of the Ethernet packet based on the control parameter P2 (especially changing the length of the inter-frame gap), and use the comparison module 581 to determine the condition of the Ethernet packet output by the asynchronous interface circuit 50 after the change in the length of the inter-frame gap. Through the above operation, the signal generator 500 can obtain the limit value of the inter-frame gap when writing is faster than reading. For example, when the average length of the Ethernet packet (i.e., cfg_pkt_len_avg) is 64 bytes, the water level parameter WL is 3, the depth parameter Ndeep is 24, and the target length of the inter-frame gap to be compensated (i.e., cfg_ifg_tx_min) is 5 bytes, if the length of the inter-frame gap (e.g., cfg_ifg_avg or cfg_ifg_min) is greater than or equal to 6 bytes, data overflow will not occur. Furthermore, although the Ethernet packet at the moment of data overflow is faulty, the reception of subsequent Ethernet packets will not be affected, and the signal generator 500 can use the comparison module 581 to perform relevant checks.

[0039] Figure 9 is a schematic diagram of data underflow occurring in an asynchronous FIFO register 80 due to the write rate being lower than the read rate, according to an embodiment of the present invention. The read pointer is marked on the right and the write pointer is marked on the left to indicate that the write rate is lower than the read rate. As shown in Figure 8, data0, data1, data2, data3 and data4 are written to the addresses addr0, addr1, addr2, addr3 and addr4 of the asynchronous FIFO register 90, respectively. Since the data after data4 has not been written but data4 has been read, if reading continues, invalid data will be read and data underflow will occur. The following formula (7) can calculate the time underflowcnt when data underflow occurs in different types of Ethernet packets when the write rate is lower than the read rate (indicating that data underflow occurs in the underflowcnt-th packet): Formula (7):

[0040] It should be noted that when the write rate is lower than the read rate, if the frame gap is shortened to a length less than the target length of the frame gap to be compensated (i.e., cfg_ifg_tx_min), after the accumulation of Ethernet packets, the difference between the read pointer and the write pointer will exceed the depth of the asynchronous FIFO register, which will also cause data overflow. The following formula (8) can be used to determine whether data overflow will occur: Formula (8):

[0041] When the result of formula (8) is greater than or equal to 0, it indicates that data overflow will not occur; when the result of formula (8) is less than 0, it indicates that data overflow will occur. Additionally, the following formula (9) can calculate the time when data overflow occurs in different types of Ethernet packets when the write rate is lower than the read rate (overflowcnt2, indicating that data overflow occurs in the overflowcnt2th packet): Formula (9):

[0042] Based on the calculations of formulas (8) and (9), it can be seen that when the average length of the Ethernet packet (i.e., cfg_pkt_len_avg) is 64 bytes, the average length of the inter-frame gap (i.e., cfg_ifg_avg) is 4 bytes, the water level parameter WL is 3, the depth parameter Ndeep is 24, and the target length of the inter-frame gap to be compensated (i.e., cfg_ifg_tx_min) is 5 bytes, theoretically, data overflow will occur in the 22nd Ethernet packet when the frequency offset is 200 ppm. In addition, when the average length of the inter-frame gap (i.e., cfg_ifg_avg) is 5 bytes and other conditions remain unchanged, theoretically, data overflow will not occur.

[0043] In one embodiment, the signal generator 500 can verify the limit value of the inter-frame gap based on the case where writing is slower than reading. Specifically, the signal generator 500 can construct a case where writing is slower than reading based on the control parameter P1, and construct the characteristics of the Ethernet packet (e.g., inter-frame gap length, packet length, etc., especially setting the inter-frame gap length to cfg_ifg_min) based on the control parameter P2. The comparison module 581 can determine whether the condition of the Ethernet packet output by the asynchronous interface circuit 50 (e.g., whether data overflow or underflow occurs, and the time when data overflow or underflow occurs) matches the theoretical value provided by the reference model 560 (e.g., the theoretical value calculated by formula (8) and formula (9)). Furthermore, after adjusting the control parameter cfg_ifg_min, the signal generator 500 can reconstruct the characteristics of the Ethernet packet based on the control parameter P2 (especially by changing the inter-frame gap length), and use the comparison module 581 to determine the state of the Ethernet packet output by the asynchronous interface circuit 50 after the change in the inter-frame gap length. Through the above operation, the signal generator 500 can obtain the limit value of the inter-frame gap when writing is slower than reading. In addition, although the Ethernet packet at the moment of data overflow or underflow has errors, the reception of subsequent Ethernet packets should not be affected, and the signal generator 500 can use the comparison module 581 to perform relevant checks.

[0044] In Ethernet, when the packet length is less than 64 bytes, the packet can be called a fragmented packet, and when the packet length is greater than 1518 bytes, the packet can be called an oversized packet. Both fragmented packets and oversized packets are abnormal Ethernet packets and can cause significant damage to asynchronous interfaces. The signal generator 500 can use the scrambler 520 to change the packet length (for example, change the packet length in the modulation signal F1) to generate fragmented packets with a length less than 64 bytes and oversized packets with a length greater than 1518 bytes in the scrambled signal F2. When the asynchronous interface circuit 50 receives these scrambled packets (such as fragmented packets and oversized packets), a reset function can be triggered. After the asynchronous interface circuit 50 is reset, the signal generator 500 can send normal packets (such as packets with a length between 64 bytes and 1518 bytes) to the asynchronous interface circuit 50 to check whether the asynchronous interface circuit 50 can recover on its own and receive / forward these normal packets normally after being hit by a large number of scrambled packets.

[0045] In addition, the signal generator 500 can continuously generate scrambled packets with an inter-frame gap length less than cfg_ifg_min using the scrambler 520. After the asynchronous interface circuit 50 receives these scrambled packets and triggers the retry function, the signal generator 500 can transmit normal packets (e.g., packets with an inter-frame gap length greater than cfg_ifg_min) to the asynchronous interface circuit 50 to check whether the asynchronous interface circuit 50 can recover on its own and receive / forward these normal packets normally after being hit by a large number of scrambled packets.

[0046] In addition, the signal generator 500 can use the scrambler 520 to continuously generate scrambled packets with a preamble length less than the minimum length specified by the IEEE 802.3 standard (e.g., 7 bytes). After the asynchronous interface circuit 50 receives these scrambled packets and triggers the retry function, the signal generator 500 can send normal packets (e.g., packets with a preamble length conforming to the IEEE 802.3 standard) to the asynchronous interface circuit 50 to check whether the asynchronous interface circuit 50 can recover on its own and receive / forward these normal packets normally after being hit by a large number of scrambled packets.

[0047] In addition, the signal generator 500 may randomly insert the aforementioned scrambled packets (such as fragmented packets, excessively long packets, scrambled packets with too short an inter-frame gap, scrambled packets with too short a preamble length, etc.) during the transmission of normal packets that have not been scrambled by the scrambler 520 to the asynchronous interface circuit 50, in order to check whether the asynchronous interface circuit 50 can correctly process a small number of scrambled packets (for example, to check whether the asynchronous interface circuit 50 will be disturbed by scrambled packets to the point that it cannot work properly).

[0048] Figure 10 is a schematic diagram of the workflow of a method for verifying an asynchronous interface circuit (e.g., the asynchronous interface circuit 50 shown in Figure 5) according to an embodiment of the present invention, wherein the asynchronous interface circuit is coupled to a signal generator (e.g., the signal generator 500 shown in Figure 5). It should be noted that the workflow shown in Figure 10 is for illustrative purposes only and is not intended to limit the invention. For example, one or more steps may be added, deleted, or modified in the workflow shown in Figure 10. Furthermore, these steps do not necessarily have to be performed in the exact order shown in Figure 10 if the same result can be obtained.

[0049] In step S110, the signal generator may use a frame modulator (e.g., the non-standard frame bar modulator 510 shown in Figure 5) to generate a modulation signal based on at least one frame control parameter.

[0050] In step S120, the signal generator may use a clock generator (e.g., clock generator 530 shown in Figure 5) within it to generate a clock signal according to at least one clock control parameter.

[0051] In step S130, the signal generator may use an interface selector (e.g., interface selector 540 shown in Figure 5) to generate a receive test signal to the asynchronous interface circuit based on at least one interface control parameter, the modulation signal and the clock signal.

[0052] In step S140, the signal generator may use a reference model (e.g., reference model 560 shown in Figure 5) to generate a reference signal based on the received test signal.

[0053] In step S150, the signal generator can use the asynchronous interface circuit to generate a transmission test signal based on the received test signal.

[0054] In step S160, the signal generator may use an inspection module (e.g., inspection module 580 shown in Figure 5) to generate at least one verification result based on the reference signal and the transmission test signal.

[0055] In summary, the signal generator 500 and related methods provided in the embodiments of the present invention can generate Ethernet packets under various conditions to check whether the asynchronous interface circuit 50 can properly forward these Ethernet packets under these conditions and further analyze its communication quality. Furthermore, by repeatedly adjusting the settings of the signal generator 500 (e.g., the settings of control parameters P1, P2, and / or P3), test packets under various extreme conditions can be transmitted to the asynchronous interface circuit 50 to test the performance limits of the asynchronous interface circuit 50. Therefore, compared to related technologies, the embodiments of the present invention can more comprehensively verify the performance of the asynchronous interface circuit 50. The above description is only a preferred embodiment of the present invention, and all equivalent variations and modifications made within the scope of the claims of the present invention should be included in the scope of the present invention. [Simplified Explanation of the Diagram]

[0056] Figure 1 is a schematic diagram of the structure of a media access control frame for an Ethernet network according to an embodiment of the present invention. Figure 2 is a schematic diagram of an asynchronous interface circuit according to an embodiment of the present invention. Figure 3 is a schematic diagram of media access control frames transmitted between two devices through a physical medium according to an embodiment of the present invention. Figure 4 is a schematic diagram of four communication scenarios according to an embodiment of the present invention. Figure 5 is a schematic diagram of verifying an asynchronous interface circuit using a signal generator according to an embodiment of the present invention. Figure 6 is a schematic diagram of a media access control frame generated by a signal generator according to control parameters according to an embodiment of the present invention. Figure 7 is a schematic diagram of an error occurring in the encoding of the physical layer according to an embodiment of the present invention. Figure 8 is a schematic diagram of data overflow occurring because the write rate is greater than the read rate according to an embodiment of the present invention. Figure 9 is a schematic diagram of data underflow occurring because the write rate is lower than the read rate according to an embodiment of the present invention. Figure 10 is a schematic diagram of the workflow of a method for verifying an asynchronous interface circuit according to an embodiment of the present invention.

Claims

1. A signal generator for verifying an asynchronous interface circuit, comprising: a frame modulator for generating a modulation signal based on at least one frame control parameter; a clock generator for generating a clock signal based on at least one clock control parameter; an interface selector for generating a receive test signal to the asynchronous interface circuit based on at least one interface control parameter, the modulation signal, and the clock signal, wherein the signal generator generates a reference signal based on the receive test signal using a reference model, and the asynchronous interface circuit generates a transmit test signal based on the receive test signal; and a verification module for generating at least one verification result based on the reference signal and the transmit test signal.

2. The signal generator as described in claim 1, wherein the inspection module comprises: a comparison module for checking whether the reference signal is consistent with the transmitted test signal to generate a comparison result among the at least one verification result.

3. The signal generator as described in claim 2, wherein the inspection module further comprises: an analyzer, wherein when the comparison result indicates that the reference signal matches the transmission test signal, the analyzer generates an analysis result among the at least one verification result based on a plurality of frame gaps in the transmission test signal.

4. The signal generator as described in claim 3, wherein the analyzer checks whether each of the plurality of inter-frame gaps in the transmission test signal matches a corresponding inter-frame gap in the reference signal to generate the analysis result.

5. The signal generator as described in claim 3, wherein the analyzer checks whether an average value of the plurality of inter-frame gaps conforms to a theoretical value determined based on the at least one frame control parameter and the at least one clock control parameter, to generate the analysis result.

6. The signal generator as described in claim 3, wherein the analyzer checks whether each of the plurality of inter-frame gaps is not less than a minimum inter-frame gap length determined by the control parameter of the at least one frame.

7. The signal generator as described in claim 3, wherein the analyzer examines whether the plurality of frame gaps contain a plurality of consecutive offset frame gaps to generate the analysis result, and the length of each of the plurality of consecutive offset frame gaps falls within an offset range determined by the control parameter of the at least one frame.

8. The signal generator as described in claim 3, wherein the analyzer calculates a variance of the plurality of inter-frame gaps to produce the analysis result.

9. The signal generator as described in claim 1, further comprising: a scrambler coupled between the frame modulator and the interface selector, for scrambling the content of the modulated signal to generate a scrambled signal; wherein the interface selector generates the receive test signal based on the at least one interface control parameter, the scrambled signal, and the clock signal.

10. A method for verifying an asynchronous interface circuit, wherein the asynchronous interface circuit is coupled to a signal generator, and the method comprising: generating a modulation signal using a frame modulator of the signal generator according to at least one frame control parameter; generating a clock signal using a clock generator of the signal generator according to at least one clock control parameter; generating a receive test signal to the asynchronous interface circuit using an interface selector of the signal generator according to the at least one interface control parameter, the modulation signal, and the clock signal; generating a reference signal using a reference model of the signal generator according to the receive test signal; generating a transmit test signal using the asynchronous interface circuit according to the receive test signal; and generating at least one verification result using a check module of the signal generator according to the reference signal and the transmit test signal.

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