Circuit board assembly

Abstract

A circuit board assembly includes an insulating material, a processor die, at least one memory die, a magnetic material and plural conductive layers. The insulating material has a top surface and a bottom surface. The processor die is disposed inside the insulating material. The memory die is disposed above the processor die along a vertical direction. The magnetic material is disposed in the insulating material, in which the magnetic material has a first portion and a second portion stacked on the first portion along the vertical direction, and the magnetic material is disposed around the processor die and the memory die. The conductive layers are disposed on the top and bottom surfaces of the insulating material and in the insulating material, in which the conductive layers are electrically connected to the processor die and the memory die.

Description

Technical Field

[0001] This disclosure relates to a circuit board assembly. Prior Technology

[0002] With the rapid development of electronic products, circuit boards, which serve as component supports and carriers of electrical signals, should gradually become miniaturized, lightweight, have high circuit density, and be multifunctional. Therefore, there are higher requirements for the space utilization of circuit boards. Summary of the Invention

[0003] This disclosure provides a circuit board assembly in some embodiments. This circuit board can be manufactured using a coreless process to create a three-dimensional stacked structure of a Graphics Processing Unit (GPU) and High Bandwidth Memory (HBM). This design utilizes magnetic materials to encapsulate and embed the GPU and HBM within the circuit board. This reduces the thickness of the circuit board and improves its space utilization while effectively preventing signal interference. Furthermore, compared to prior art, this design eliminates the reliability risks associated with direct interconnection between the interposer and the circuit board via laser vias.

[0004] This disclosure provides a circuit board assembly including an insulating material, a processor die, at least one memory die, a magnetic material, and multiple conductive layers. The insulating material has an upper surface and a lower surface. The processor die is disposed within the insulating material. The memory die is disposed vertically above the processor die. The magnetic material is disposed within the insulating material, wherein the magnetic material has a first portion and a second portion stacked vertically on the first portion, and the magnetic material is disposed around the processor die and the memory die. Conductive layers are disposed on the upper surface, the lower surface, and within the insulating material, wherein the conductive layers are electrically connected to the memory die and the processor die. Simple Explanation of the Diagram

[0005] Figure 1 is a schematic diagram of a circuit board assembly according to a partial embodiment of this disclosure. Figures 2A and 2B are flowcharts of a method for manufacturing a circuit board assembly according to a partial embodiment of this disclosure. Figures 3A to 3T are cross-sectional views of a circuit board assembly according to an embodiment of the present disclosure at various stages of the manufacturing process. Implementation

[0006] The embodiments disclosed herein are discussed in detail below. However, it should be understood that the embodiments provide many applicable concepts that can be implemented in a wide variety of specific contexts. The discussed and disclosed embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The terms "first," "second," etc., used herein do not specifically refer to any order or sequence, but are merely used to distinguish components or operations described using the same technical terms.

[0007] Additionally, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and similar terms are used herein to describe the relationship between one element or feature and another illustrated in the figures. Besides the orientation depicted in the figures, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein shall be interpreted accordingly. As used herein, “approximately,” “about,” “closely,” or “substantially” generally refer to within 20%, 10%, or 5% of a given value or range. The numerical quantities given herein are approximate, meaning that unless explicitly specified, the terms “approximately,” “about,” “closely,” or “substantially” may be speculative.

[0008] Please refer to Figure 1. Figure 1 is a schematic diagram of a circuit board assembly 100 according to a partial embodiment of this disclosure. In this embodiment, the circuit board assembly 100 may include an insulating material 110, a magnetic material 120, a conductive layer 130, a processor die 140, metal pillars 150, and a memory die 160.

[0009] In some embodiments, the insulating material 110 may be formed of organic or inorganic insulating materials to provide the mechanical support required for the circuit board assembly 100 or electrical isolation between the various conductive paths, thereby preventing short circuits and maintaining signal integrity. For example, in some embodiments, the insulating material 110 may be formed of polypropylene (PP), ajinomoto build-film (ABF), similar materials, or combinations thereof.

[0010] In some embodiments, the magnetic material 120 may be a ferromagnetic material, a ferromagnetic material, an alloy thereof, or a combination thereof. For example, in some embodiments, the magnetic material 120 is a ferromagnetic material and may be formed from materials such as iron (Fe), iron-cobalt (FeCo), cobalt-iron-boron (CoFeB), iron-boron (FeB), iron-platinum (FePt), iron-palladium (FePd), nickel-iron (NiFe), or similar materials or combinations thereof. Alternatively, the magnetic material 120 may be a ferromagnetic material and may include ceramic materials such as iron oxide.

[0011] Furthermore, portions 122 and 124 of the magnetic material 120 directly contact and surround the processor die 140 and the memory die 160, respectively. In this way, the magnetic material 120 can separate the memory die 160 from the processor die 140, and also separate the conductive layer 130 from the memory die 160. Thus, the magnetic material 120 can encapsulate and embed the processor die 140 and the memory die 160 into the circuit board assembly 100 to prevent signal interference.

[0012] In some embodiments, the conductive layer 130 may include copper, tin, silver, nickel, similar conductive materials, or combinations thereof. The conductive layer 130 may be disposed on the upper surface 110A, the lower surface 110B, and within the insulating material 110. For example, in this embodiment, the conductive layer 130 may include a plurality of lines 132 and 134. Lines 132 may be disposed on the upper surface 110A, the lower surface 110B, a portion 122 of the magnetic material 120, and within the insulating material 110, wherein lines 132 are parallel to the upper surface 110A and the lower surface 110B of the insulating material 110 in a horizontal direction (direction X). Lines 134 may be disposed within the insulating material 110, wherein lines 134 intersect with lines 132 in a vertical direction (direction Y) and are electrically connected to lines 132.

[0013] In some embodiments, the processor die 140 may be used to manufacture a graphics processing unit (GPU). A portion 122 of the magnetic material 120 may be disposed around the processor die 140, and the processor die 140 may be disposed inside the insulating material 110. A plurality of bumps 180 are provided on the surface 140A of the processor die 140 away from the memory die 160, and the processor die 140 may be electrically connected to the lines 132 of the conductive layer 130 via the bumps 180.

[0014] In some embodiments, metal pillars 150 are disposed on the surface 160C of memory die 160 near processor die 140. The metal pillars 150 connect a conductive layer 130 (e.g., a protrusion 132P of line 132 in conductive layer 130) located above processor die 140 to one of the memory die 160, and are electrically connected to the conductive layer 130. Specifically, the metal pillars 150 may be conductive paste, and may use materials including copper paste, solder paste, silver paste, similar materials, or combinations thereof. However, it should be noted that the metal pillars 150 may be made of any suitable material, and are not limited thereto. The length of the metal pillars 150 may be varied according to functional requirements. For example, in this embodiment, the length of the metal pillars 150 is the same as the protrusion 132P of line 132 in conductive layer 130.

[0015] In some embodiments, the memory chip 160 may be a high-bandwidth memory (HBM). A portion 124 of the magnetic material 120 may be designed to surround the memory chip 160, and the memory chip 160 may partially overlap the metal pillar 150 and the processor chip 140 in the vertical direction (direction Y). Here, the memory chip 160 can be electrically connected to the lines 132 of the conductive layer 130 via the metal pillar 150. Furthermore, the number of memory chips 160 can be varied according to functional requirements. For example, in this embodiment, four memory chips 160 are used.

[0016] In some embodiments, the silicon through-hole 170 may be located within the memory die 160, wherein the silicon through-hole 170 extends along the upper surface 160A of one of the memory dies 160 away from the metal pillar 150 to the lower surface 160B of the other memory die 160 away from the metal pillar 150. For example, in this embodiment, the silicon through-hole 170 penetrates through memory dies 162, 164, and 166, and extends along the upper surface 160A of memory die 162 to the lower surface 160B of memory die 166. Thus, each layer of the memory die 160 can be electrically connected via the silicon through-hole 170. In this embodiment, the silicon through-hole 170 may include microbumps 172 and conductive material 174, wherein the silicon through-hole 170 may include the same material as the conductive layer 130. In other embodiments, the silicon through-hole 170 may be made of a different material than the conductive layer 130, and the conductive material 174 may include substances such as copper, polycrystalline silicon, and tungsten.

[0017] Furthermore, the magnetic material 120 can be designed to surround the processor die 140 and the memory die 160 in a stacked configuration. For example, in this embodiment, the magnetic material 120 can be disposed in the insulating material 110, and the magnetic material 120 can also fill the gaps SP1 between the lines 132 of the conductive layer 130 disposed on the processor die 140. The magnetic material 120 has a portion 122 and a portion 124 stacked on the portion 122 in a vertical direction (e.g., direction Y), wherein the portion 124 extends in a horizontal direction (e.g., direction X) and protrudes from the side 122A of the portion 122, and the thickness TH2 of the portion 124 is greater than the thickness TH1 of the portion 122. In other words, the volume of the portion 124 is larger than that of the portion 122.

[0018] Figures 2A and 2B are flowcharts of a method 200 for manufacturing a circuit board assembly 100 according to a partial embodiment of the present disclosure. Figures 3A to 3T are cross-sectional views of a circuit board assembly 100 according to an embodiment of the present disclosure at various stages of the manufacturing process. Method 200 includes steps S210 to S410. It should be understood that additional steps may be added before, during, and after steps S210 to S410, and for another partial embodiment of the method, some of the steps mentioned below may be replaced or omitted. The order of steps / procedures may be changed.

[0019] First, please refer to Figures 1 and 3A. Method 200 begins at step S210. A processor die 140 is disposed on the metal layer 906 of the support structure 900. For example, in this embodiment, the support structure 900 may include a core layer 902, a dielectric layer 904, a metal layer 906, and a metal layer 908. The dielectric layer 904 is disposed on the core layer 902. The metal layers 906 and 908 are respectively disposed on opposite surfaces of the dielectric layer 904. The processor die 140 may be formed on the metal layer 906 by die bonding, or similar or combined processes.

[0020] Next, please refer to Figure 3B. Method 200 proceeds to step S220. An insulating material 800 is formed on the support structure 900. For example, in this embodiment, the insulating material 800 may include PP, ABF, similar materials, or combinations thereof. The insulating material 800 may be formed on the metal layer 906 by lamination, similar or combined processes, and separated from the processor die 140 to form a gap space GS, wherein the gap space GS is located between the insulating material 800 and the processor die 140.

[0021] Next, please refer to Figure 3C. Method 200 proceeds to step S230. A portion 122 of the magnetic material 120 is formed between the insulating materials 800. For example, in this embodiment, a portion 122 of the magnetic material 120 may fill the gap space GS between the insulating material 800 and the processor die 140, wherein the portion 122 directly contacts and surrounds the processor die 140.

[0022] Next, please refer to Figure 3D. Method 200 proceeds to step S240. Line 132A is formed on portion 122 of the insulating material 800 and the magnetic material 120. For example, in this embodiment, a conductive material can be formed on portion 122 of the insulating material 800 and the magnetic material 120 through sputtering, electroplating, or similar or combined processes. Next, a photosensitive film is formed on this conductive material by a lamination process. Next, this photosensitive film is exposed. Next, an etching process is performed on the conductive material and the photosensitive film to form line 132A.

[0023] Next, please refer to Figure 3E. Method 200 proceeds to step S250. A photoresist layer 700 is formed on the portion 122 of the line 132A, the insulating material 800, and the magnetic material 120. For example, in this embodiment, the photoresist layer 700 is formed on the portion 122 of the line 132A, the insulating material 800, and the magnetic material 120 by a lamination process. Next, the photoresist layer 700 is exposed. Next, the photoresist layer 700 is subjected to a development process to pattern the photoresist layer 700 and expose a portion of the line 132A.

[0024] Next, please refer to Figure 3F. Method 200 proceeds to step S260. A protrusion 132P of the line 132A is formed. For example, in this embodiment, an electroplating process is performed on the line 132A exposed by the photoresist layer 700 to form the protrusion 132P of the line 132A. Next, the photoresist layer 700 can be removed by chemical stripping.

[0025] Next, method 200 proceeds to step S270. A polymer film 600 is formed on line 132A. For example, in this embodiment, the polymer film 600 may include a polyimide (PI) film. The polymer film 600 may be formed on line 132A having a protrusion 132P by lamination, similar or combined processes, wherein the polymer film 600 surrounds the protrusion 132P. Thereby, in a subsequent process, memory chips 160 (see subsequent FIG3O) may be formed on the protrusion 132P of line 132A.

[0026] Next, please refer to Figure 3G. Method 200 proceeds to step S280. An augmentation layer 500 is formed on the insulating material 800, the circuit 132A, and the polymer film 600. For example, in this embodiment, the augmentation layer 500 may include insulating materials 502 and 504, a metal layer 506, and circuits 134A and 132B. Insulating materials 502 and 504 may include the same material as insulating material 800. In detail, insulating material 502 may be formed on insulating material 800, circuit 132A, and polymer film 600 by lamination, or similar or combined processes. Next, a conductive material may be formed on insulating material 502 by sputtering, electroplating, or similar or combined processes.

[0027] Next, a laser process is performed on the insulating material 502 and the conductive material to form multiple blind vias. Then, another conductive material is deposited in these blind vias by electroplating, or similar or combined processes, to form circuit 134A. Next, a patterning process is performed on the conductive material on the insulating material 502 to form circuit 132B, wherein circuit 134A electrically connects circuits 132A and 132B. Next, an insulating material 504 is formed on the insulating material 502 and circuit 132B by lamination, or similar or combined processes. Next, a metal layer 506 is formed on the insulating material 504 by sputtering, electroplating, or similar or combined processes to form an addendum layer 500.

[0028] Next, please refer to Figure 3H. Method 200 proceeds to step S290. The support structure 900 is removed to form structure S1. For example, in this embodiment, the core layer 902, dielectric layer 904, and metal layer 908 of the support structure 900 can be removed by a process of board separation, or a similar or combined process to form structure S1.

[0029] Next, please refer to Figure 3I. Method 200 proceeds to step S300. A plurality of blind vias V1 are formed in structure S1. For example, in this embodiment, the blind vias V1 can be formed in structure S1 by laser, or similar or combined processes, wherein the blind vias V1 penetrate metal layers 906, 506, insulating materials 800 and 504, and expose portions of the circuits 132A and 132B.

[0030] Next, please refer to Figure 3J. Method 200 proceeds to step S310. A conductive material is filled into the blind via V1 to form the circuit 134B. For example, in this embodiment, the conductive material is formed in the blind via V1 by sputtering, electroplating, or similar or combined processes. Next, a planarization process is performed on the conductive material to make it flush with the metal layers 506 and 906 to form the circuit 134B.

[0031] Next, please refer to Figure 3K. Method 200 proceeds to step S320. Metal layer 506 (see Figure 3J) and metal layer 906 (see Figure 3J) are patterned to form line 132C. For example, in this embodiment, a photosensitive film can be formed on metal layer 506 and metal layer 906 by a lamination process. Next, this photosensitive film is exposed. Next, metal layer 506, metal layer 906, and the photosensitive film are etched to form line 132C, wherein line 134B connects line 132C and 132B / 132A.

[0032] Next, please refer to Figures 2B and 3L. Method 200 proceeds to step S330. An addendum layer 400 is formed on structure S1 to form structure S2. For example, in this embodiment, the addendum layer 400 may include an insulating material 402 and a metal layer 404, wherein the insulating material 402 may include the same material as the insulating material 800, and the metal layer 404 may include the same material as the conductive layer 130. The addendum layer 400 may be formed on the addendum layer 500, the insulating material 800, and the circuit 132C of structure S1 by the same process as the addendum layer 500, wherein the circuit 134C of the addendum layer 400 connects the circuit 132C of the addendum layer 500 and the circuit 132D of the addendum layer 400.

[0033] Next, please refer to Figures 2B and 3M. Method 200 proceeds to step S340. A cavity CV is formed in structure S2. For example, in this embodiment, structure S2 may be subjected to laser, drilling, or similar or combined opening processes to form the cavity CV in structure S2, wherein the cavity CV exposes one surface of the polymer film 600 and the protrusion 132P of the line 132A.

[0034] Next, please refer to Figures 2B and 3N. Method 200 proceeds to step S350. The polymer film 600 is removed. For example, in this embodiment, the polymer film 600 can be removed by plasma, or a similar or combined process, to expose the line 132A and the protrusion 132P of the line 132A.

[0035] Next, please refer to Figures 2B and 3O. Method 200 proceeds to step S360. A memory die 160 is disposed in the cavity CV. For example, in this embodiment, the memory die 160 may be disposed in the cavity CV and located on the protrusion 132P of line 132A, wherein a metal pillar 150 is located between the memory die 160 and the protrusion 132P. Thus, the memory die 160 can be connected to the protrusion 132P via the metal pillar 150.

[0036] Next, please refer to Figures 2B and 3P. Method 200 proceeds to step S370. A portion 124 of the magnetic material 120 is formed in the cavity CV. For example, in this embodiment, the portion 124 of the magnetic material 120 fills the cavity CV and directly contacts and surrounds the memory chip 160.

[0037] Next, please refer to Figures 2B and 3Q. Method 200 proceeds to step S380. An addendum layer 300 is formed on structure S2 to form structure S3. For example, in this embodiment, the addendum layer 300 includes an insulating material 302 and a metal layer 304, wherein the insulating material 302 may include the same material as the insulating material 800, and the metal layer 304 may include the same material as the conductive layer 130. The insulating material 302 may be formed on the circuit 132D and the portion 124 of the magnetic material 120 by lamination, similar or combined processes. Next, the metal layer 304 may be formed on the insulating material 302 by sputtering, electroplating, similar or combined processes.

[0038] Next, please refer to Figures 2B and 3R. Method 200 proceeds to step S390. A plurality of blind vias V2 are formed in structure S3. For example, in this embodiment, the blind vias V2 may be formed in structure S3 by laser, or similar or combined processes, wherein the blind vias V2 penetrate layers 300 and 400 and expose portions of the lines 132C and 132D.

[0039] Next, please refer to Figures 2B and 3S. Method 200 proceeds to step S400. A conductive material is formed in the blind via V2 to form the circuit 134D. For example, in this embodiment, the conductive material can be formed in the blind via V2 by sputtering, electroplating, or similar or combined processes. Next, a planarization process is performed on the conductive material to form the circuit 134D.

[0040] Next, please refer to Figures 2B and 3T. Method 200 proceeds to step S410. The metal layers 304 (see Figure 3Q) and 404 (see Figure 3L) are patterned. For example, in this embodiment, a photosensitive film can be formed on the metal layers 304 and 404 by a lamination process. Next, the photosensitive film is exposed. Then, the metal layers 304 and 404 and the photosensitive film are etched to form line 132E, thereby obtaining the circuit board assembly 100, wherein line 134D connects lines 132D and 132E. Furthermore, lines 132A to 132E can be collectively referred to as line 132 (see Figure 1), and lines 134A to 134D can be collectively referred to as line 134 (see Figure 1). The insulating materials 800, 502, 504, 402, and 302 can be collectively referred to as insulating material 110.

[0041] This disclosure provides a circuit board assembly in some embodiments. This circuit board can be manufactured using a coreless process to create a three-dimensional stacked structure of a Graphics Processing Unit (GPU) and High Bandwidth Memory (HBM). This design encapsulates and embeds the GPU and HBM within the circuit board using magnetic materials. This reduces the thickness of the circuit board and improves its space utilization while effectively preventing signal interference. Furthermore, compared to prior art, this design eliminates the reliability risks associated with direct interconnection between the interposer and the circuit board via laser vias.

[0042] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the various aspects of this application. Those skilled in the art should understand that they can readily use this application as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this application, and various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this application.

[0043] 100: Circuit board assembly 110, 800, 502, 504, 402, 302: Insulating materials 120: Magnetic materials 122A: Side 122, 124: Partial 130: Conductive layer 132, 132A, 132B, 132C, 132D, 132E, 134, 134A, 134B, 134C, 134D: Lines 132P: Protruding part 140: Processor die 150: Metal Column 160, 162, 164, 166: Memory chips 110A, 110B, 140A, 160A, 160B, 160C: Surface 170: Silicon perforation 172: Microbumps 174: Conductive Materials 180: Bump 200: Method S210, S220, S230, S240, S250, S250, S260, S270, S280, S290, S300, S310, S320, S330, S340, S350, S360, S370, S380, S390, S400, S410: Steps 300, 400, 500: Additional floors 600: Polymer membrane 700: Photoresist layer 900: Supporting structure 902: Core Layer 904: Dielectric layer 908, 906, 506, 404, 304: Metallic layer V1, V2: Blind holes TH1, TH2: Thickness GS: Gap Space SP1: Gap CV: Cavity S1, S2, S3: Structure X, Y, Z: Direction

Claims

1. A circuit board assembly, comprising: An insulating material having an upper surface and a lower surface; a processor die disposed within the insulating material; At least one memory die is disposed above the processor die in a vertical direction; a magnetic material is disposed in the insulating material, wherein the magnetic material has a first portion and a second portion stacked on the first portion in the vertical direction, the magnetic material is disposed around the processor die and the at least one memory die, wherein the magnetic material separates the at least one memory die from the processor die; a plurality of conductive layers are disposed on the upper surface, the lower surface and in the insulating material, wherein the plurality of conductive layers are electrically connected to the at least one memory die and the processor die; And a plurality of metal pillars disposed in the second portion of the magnetic material, wherein the plurality of metal pillars connect one of the at least one memory chip to the plurality of conductive layers located above the processor chip, and the plurality of metal pillars are electrically connected to the plurality of conductive layers.

2. The circuit board assembly as claimed in claim 1, wherein the magnetic material fills a void between the plurality of conductive layers disposed on the processor die.

3. The circuit board assembly as claimed in claim 1, wherein the second portion of the magnetic material extends in a horizontal direction and protrudes beyond the side of the first portion of the magnetic material.

4. The circuit board assembly as claimed in claim 1, wherein the magnetic material is in direct contact with the at least one memory die and the processor die.

5. The circuit board assembly as claimed in claim 1, wherein the magnetic material separates the plurality of conductive layers from the at least one memory die.

6. The circuit board assembly as claimed in claim 1, wherein a plurality of bumps are provided on a surface of the processor die away from the at least one memory die, and the processor die is electrically connected to the plurality of conductive layers through the plurality of bumps.

7. The circuit board assembly as claimed in claim 1, wherein the plurality of conductive layers includes a first line parallel to the upper surface of the insulating material.

8. The circuit board assembly as claimed in claim 7, wherein the plurality of conductive layers includes a second line that intersects with the first line and is electrically connected to the first line.

9. The circuit board assembly as described in claim 1, further comprising: A silicon through-hole is located in the at least one memory die, wherein the silicon through-hole extends along an upper surface of one of the at least one memory die away from the plurality of metal pillars to a lower surface of the other of the at least one memory die away from the plurality of metal pillars, and each layer of the at least one memory die is electrically connected through the silicon through-hole.

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