Circuit layout method

Abstract

A circuit layout method, implemented via a computing device, is applicable to a circuit board image including an unrouted printed circuit board to be routed and a reference circuit board image including a reference printed circuit board for reference routing. The printed circuit board to be routed includes a plurality of wiring pair connection groups for interconnecting with each other by wires. Each wiring pair connection group includes a start connection point and an end connection point corresponding to the start connection point. The computing device includes a processing module that, for the printed circuit board to be routed, obtains a current adjustment state corresponding to the current layout state based on a current layout state corresponding to the wiring pair connection groups, thereby obtaining a target printed circuit board for completing circuit routing.

Claims

1. A circuit layout method, implemented via a computing device, is applicable to a circuit board image including an unrouted printed circuit board to be routed and a reference circuit board image including a reference printed circuit board for reference routing, the unrouted printed circuit board including a plurality of wiring pair connection groups for interconnection by wires, each wiring pair connection group including a start connection point and an end connection point corresponding to the start connection point, the computing device including a processing module, the circuit layout method comprising the following steps for the unrouted printed circuit board: (A) for each wiring pair connection group, the processing module obtaining a current wire in the unrouted printed circuit board for extension from the start connection point to the corresponding end connection point according to a random sampling algorithm; (B) the processing module updating the unrouted printed circuit board according to the current wires; (C) the processing module obtaining an error rate indicating the presence of errors in the unrouted wiring pair connection groups; (D) the processing module using the unrouted printed circuit board as a current printed circuit board. (E) The processing module obtains a pairing connection group to be corrected from the uncorrected pairing connection groups to be corrected in the current printed circuit board; (F) The processing module obtains a current layout adjustment action related to the pairing connection group to be corrected based on the error ratio, the circuit board image containing the current printed circuit board, and the reference circuit board image; and (G) The processing module obtains a next conductor related to the current conductor after adjusting the current conductor based on the current layout adjustment action corresponding to the pairing connection group to be corrected; (H) The processing module updates the current printed circuit board to the printed circuit board to be routed based on the next conductor, and uses the next conductor as the current conductor of the corresponding pairing connection group to be corrected; (I) The processing module determines whether the pairing connection group to be corrected corresponds to the erroneous conductor; (J) The processing module determines whether there is at least one uncorrected pairing connection group to be corrected in the pairing connection group to be waited for wiring. (K) When the processing module determines that there is no at least one uncorrected wiring pairing connection group, the processing module determines whether the similarity threshold between the circuit board image of the printed circuit board to be wired and the reference circuit board image exceeds; (L) When the processing module determines that the similarity threshold between the circuit board image of the printed circuit board to be wired and the reference circuit board image exceeds, the processing module uses the printed circuit board to be wired as a target printed circuit board; (a) The processing module determines whether there is at least one defective wiring pairing connection group in the target printed circuit board, wherein, (a) The electromagnetic interference of each defective pairing connection group is greater than an electromagnetic interference threshold; (b) When the processing module determines that the at least one defective pairing connection group exists, the processing module treats the target printed circuit board as a printed circuit board to be adjusted; (c) The processing module obtains a pairing connection group to be adjusted from the at least one defective pairing connection group that has not been adjusted; (d) The processing module obtains a current interference adjustment action related to the pairing connection group to be adjusted based on the printed circuit board to be adjusted; (e) The processing module obtains another conductor based on the current conductor corresponding to the pairing connection group to be adjusted using the current interference adjustment action; (f) The processing module updates the printed circuit board to be adjusted to the target printed circuit board based on the other conductor, and uses the other conductor as the current conductor of the corresponding pairing connection group to be adjusted; (g) The processing module determines whether there is at least one unadjusted defective pairing connection group among the defective pairing connection groups; and (h) When the processing module determines that there is at least one unadjusted defective pairing connection group, it returns to step (c).

2. The circuit layout method as described in claim 1, wherein the computing device further includes a storage module signal-connected to the processing module, and stores a circuit layout model for generating an input adjustment action and an output layout feedback based on an input circuit board state, wherein, Step (F) further includes the following sub-steps: (F-1) The processing module obtains an image similarity degree based on the circuit board image containing the current printed circuit board and the reference circuit board image to describe the layout similarity between the current printed circuit board and the reference circuit board image; (F-2) The processing module obtains a current layout state based on the error ratio and the image similarity degree; and (F-3) The processing module obtains the current layout adjustment action and a current layout feedback corresponding to the current layout adjustment action from multiple adjustment actions corresponding to the current layout state using the circuit layout model, wherein the output feedback corresponding to the current layout adjustment action is the largest among the output feedback of the adjustment actions.

3. The circuit layout method as described in claim 2, wherein, Before sub-step (F-2), there is a sub-step (F-4) in which the processing module obtains a wire distance indicating the distance between the current wire and the reference wire segment based on the current wire corresponding to the wiring pairing connection point in the circuit board image containing the current printed circuit board and the reference wire corresponding to the wiring pairing connection point in the reference printed circuit board image; and wherein, in sub-step (F-2), the processing module obtains the current layout state based on the wire distance in addition to the error ratio and the image similarity.

4. The circuit layout method as described in claim 3, wherein, Before sub-step (F-2), the following sub-steps are also included: (F-5) The processing module initializes a density count for each pixel of the current printed circuit board; (F-6) The processing module selects a center pixel from the pixels in the circuit board image containing the current printed circuit board whose pixel density has not been determined; (F-7) The processing module determines whether there is at least one object pixel in the region mask based on an object recognition threshold, which includes a plurality of neighboring pixels centered at the center pixel position and having a radius of a density radius, wherein the at least one object pixel indicates that the pixel value at the corresponding position is greater than the object recognition threshold; (F-8) When the processing module determines that there is at least one object pixel in the region mask, the processing module determines whether the number of the at least one object pixel exceeds a density threshold; (F-9) When the processing module determines that the number of the at least one object pixel exceeds the density threshold, for each object pixel, the processing module increments the density count corresponding to the object pixel by one; (F-10) The processing module determines whether there is at least one pixel in the circuit board image whose wiring density has not been determined; (F-11) When the processing module determines that there is at least one pixel whose pixel density has not been determined, it returns to sub-step (F-6); (F-12) When the processing module determines that there is no pixel whose pixel density has not been determined, the processing module obtains a wiring density mark based on the density count of all pixels; and wherein, in sub-step (F-2), in addition to the error ratio, the image similarity and the wire distance, the processing module also obtains the current layout state based on the wiring density.

5. The circuit layout method as described in claim 4, wherein, In sub-step (F-3), each adjustment action is one of the following: a node correction action for adding, modifying or moving nodes of the current conductor of the pairing connection group to be corrected; a rewiring action for rearranging the current conductor of the pairing connection group to be corrected; and a conductor adjustment action for adjusting the length or width of the current conductor of the pairing connection group to be corrected.

6. The circuit layout method as described in claim 5, further comprising the following sub-step in step (C): (C-1) The processing module determines whether there is at least one erroneous wire among the current wires corresponding to the waiting wiring pairing connection group, wherein, (C-2) When the processing module determines that at least one erroneous wire exists in the wires corresponding to the waiting wiring pairing connection group, the processing module obtains the error ratio based on the waiting wiring pairing connection group with the erroneous wire and all waiting wiring pairing connection groups; and (C-3) When the processing module determines that at least one erroneous wire does not exist in the wires corresponding to the waiting wiring pairing connection group, the processing module sets the error ratio to zero.

7. The circuit layout method as described in claim 1, after step (I), further includes the following steps: (M) when the processing module determines that the pairing connection group to be corrected corresponds to the erroneous wire, the processing module updates the error ratio; and (N) when the processing module determines that there is at least one uncorrected pairing connection group to be corrected, return to step (D).

8. The circuit layout method as described in claim 7, after step (K), further includes the following steps: (O) when the processing module determines that the circuit board image and the reference circuit board image of the printed circuit board to be wired do not exceed the similarity threshold, the corrected waiting wiring pairing connection group is reclassified as an uncorrected waiting wiring pairing connection group, and the process returns to step (C).

9. The circuit layout method as described in claim 8, further comprising the following steps after step (F): (P) the processing module obtains a historical layout record based on the current layout state and its corresponding current layout adjustment action, the layout state of the printed circuit board to be routed, and the current layout feedback; (Q) the processing module obtains at least one sampled layout record from the historical layout records; and (R) the processing module updates the circuit layout model based on the at least one sampled layout record.

10. The circuit layout method as described in claim 1, wherein the storage module further stores an electromagnetic interference correction model for generating an output interference adjustment action and an output interference correction feedback based on an input electromagnetic interference state, wherein, Step (d) further includes the following sub-steps: (d-1) The processing module obtains a current electromagnetic interference matrix indicating the electromagnetic interference level of the panel of the printed circuit board to be adjusted based on the printed circuit board to be adjusted, wherein each element of the current electromagnetic interference matrix indicates the electromagnetic interference value at the corresponding location; (d-2) The processing module obtains a current electromagnetic interference state based on the current electromagnetic interference matrix; and (d-3) The processing module obtains the current interference adjustment action and a current interference correction feedback corresponding to the current interference adjustment action from multiple interference adjustment actions corresponding to the current electromagnetic interference state using the electromagnetic interference correction model, wherein the output interference correction feedback corresponding to the current interference adjustment action is the largest among the output interference correction feedbacks of the interference adjustment actions.

11. The circuit layout method as described in claim 10, further comprising the following sub-steps before sub-step (d-2): (d-4) the processing module initializes an interference density count for each element of the current electromagnetic interference matrix; (d-5) the processing module selects a center element from the elements in the current electromagnetic interference matrix containing the printed circuit board to be adjusted that have not been determined for interference density; (d-6) the processing module determines, using an interference identification threshold, whether the interference region mask contains at least one interfering element based on an interference region mask comprising a plurality of neighboring elements centered at the position of the center element and having a radius equal to an interference density radius, wherein, The at least one interfering element indicates that the electromagnetic interference value at the corresponding location is greater than the interference identification threshold; (d-7) When the processing module determines that the at least one interfering element exists in the interference area mask, the processing module determines whether the number of the at least one interfering element exceeds an interference density threshold; (d-8) When the processing module determines that the number of the at least one interfering element exceeds the interference density threshold, for each interfering element, the processing module increments the interference density count corresponding to the interfering element by one; (d-9) The processing module determines whether there is at least one element in the current electromagnetic interference matrix whose interference density has not been determined; (d-10) When the processing module determines that there is at least one element whose interference density has not been determined, return to sub-step (d-5). (d-11) When the processing module determines that there is no element with an undetermined interference density, the processing module obtains a wiring interference density mark related to the wiring density of the current electromagnetic interference matrix based on the corresponding interference density count of all elements; and wherein, in sub-step (d-2), the processing module obtains the current electromagnetic interference state based on the wiring interference density mark in addition to the current electromagnetic interference matrix.

12. The circuit layout method as described in claim 11, wherein, In sub-step (d-3), each interference adjustment action is one of an adjustment interference wire action for modifying the length of the current wire of the pairing connection group to be adjusted and a reset interference wire action for rearranging the current wire of the pairing connection group to be adjusted.

13. The circuit layout method as described in claim 12, further comprising the following steps after step (d): (i) the processing module obtains a historical interference correction record based on the current electromagnetic interference state and its corresponding current interference adjustment action, the electromagnetic interference state of the target printed circuit board and the current interference correction feedback; (j) the processing module obtains at least one sampled interference correction record from the historical interference correction records; and (k) the processing module updates the electromagnetic interference correction model based on the at least one sampled interference correction record.

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