Memory integrated circuit and manufacturing method thereof
Patent Information
- Authority / Receiving Office
- TW · TW
- Patent Type
- Applications
- Current Assignee / Owner
- WINBOND ELECTRONICS CORP
- Filing Date
- 2025-01-20
- Publication Date
- 2026-08-01
AI Technical Summary
Lithography limitations during DRAM cell miniaturization lead to alignment issues and potential leakage current or increased parasitic capacitance due to close spacing between insulating structures and word lines, necessitating improved lithography verification mechanisms.
A memory volumetric circuit design with memory arrays and test structures on a semiconductor wafer, where insulating structures in the test structures have a larger pitch than in the memory arrays, allowing for accurate verification of positional relationships using self-aligned dual or reverse patterning techniques.
Ensures accurate verification of positional relationships between insulating structures and word lines, preventing obscuration and enabling reliable pattern verification, thus addressing alignment issues and potential leakage current.
Smart Images
Figure TWG2TA001069623_001 
Figure TWG2TA001069623_002 
Figure TWG2TA001069623_003
Abstract
Description
[Technical Field]
[0001] This disclosure relates to an integrated circuit and a method for manufacturing the same, and more particularly to a memory integrated circuit and a method for manufacturing the same. [Previous Technology]
[0002] As a semiconductor memory, dynamic random access memory (DRAM) is often used as the main memory in memory systems due to its advantages such as high storage density and fast operation speed. To further increase storage density, DRAM cells are continuously miniaturized. However, the limitations of lithography processes cause many side effects during DRAM cell miniaturization, such as alignment problems between patterns. While further improving lithography technology, it is also necessary to design verification mechanisms to ensure the reliability of DRAM. [Summary of the Invention]
[0003] One aspect of this disclosure provides a memory volumetric circuit, comprising: a plurality of memory arrays located in a plurality of wafer regions of a semiconductor wafer; and a plurality of test structures located in a dicing region of the semiconductor wafer, wherein the plurality of memory arrays and the plurality of test structures each include a plurality of word lines extending in the same direction and a plurality of insulating structures, wherein the plurality of insulating structures in each memory array are configured to define a plurality of capacitive contact structures, the plurality of insulating structures in each memory array are arranged with a first pitch, and the plurality of insulating structures in each test structure are arranged with a second pitch greater than the first pitch.
[0004] Another aspect of this disclosure provides a memory volumetric circuit, comprising: a plurality of functional pattern arrays located in a plurality of wafer regions of a semiconductor wafer; and a plurality of test structures located in a dicing region of the semiconductor wafer, wherein the plurality of functional pattern arrays and the plurality of test structures respectively include a plurality of first patterns and a plurality of second patterns extending in the same direction, wherein the plurality of second patterns in each functional pattern array are configured to define the positions of a plurality of third patterns, the plurality of second patterns in each functional pattern array are arranged with a first pitch, and the plurality of second patterns in each test structure are arranged with a second pitch greater than the first pitch.
[0005] Another aspect of this disclosure provides a method for manufacturing a memory volumetric circuit, comprising: forming a plurality of memory arrays in a plurality of wafer regions of a semiconductor wafer; and forming a plurality of test structures in a dicing region of the semiconductor wafer, wherein the plurality of memory arrays and the plurality of test structures respectively include a plurality of word lines extending in the same direction and a plurality of insulating structures, wherein the plurality of insulating structures in each memory array are configured to define a plurality of capacitive contact structures, the plurality of insulating structures in each memory array are arranged with a first pitch, and the plurality of insulating structures in each test structure are arranged with a second pitch greater than the first pitch.
Implementation Method
[0006] The memory volume circuit disclosed herein will be described below using DRAM integrated circuits as an example. Nevertheless, after understanding the lithography verification mechanism disclosed herein, it should be understood that this lithography verification mechanism can also be applied to other memory volume circuits or any integrated circuit with periodic patterns.
[0007] A DRAM integrated circuit includes multiple memory cells arranged in an array, each including a transistor and a storage capacitor coupled to the transistor. In terms of process sequence, the transistor can be formed in the semiconductor wafer first, followed by the storage capacitor. Furthermore, after the transistor is formed but before the storage capacitor is formed, various components, including bit line contact structures and bit line-capacitor contact structures, can be formed on the semiconductor wafer.
[0008] In the intermediate stage illustrated in FIG1A, access transistors 100 have been formed in a semiconductor substrate. Specifically, each access transistor 100 is defined at the intersection of an active region 102 and a word line WL. The word line WL serves as the gate of the access transistor 100, while the portions of the active region 102 located on both sides of the word line WL serve as the drain and source of the access transistor.
[0009] Each active region 102 is shared by two access transistors 100. In these embodiments, each active region 102 is interleaved across two word lines WL. The two access transistors 100 are defined with the portion of their active regions 102 located between the two word lines WL as a shared drain / source.
[0010] The character lines WL extend along direction D1 and are arranged along direction D2, which is perpendicular to direction D1. On the other hand, the active areas 102 may extend along direction D3, which intersects with directions D1 and D2, and are arranged in an array. The active areas 102 in each row are arranged along direction D1, while the active areas 102 in each column are arranged along direction D2. In some embodiments, each column active area 102 is displaced in direction D2 relative to two adjacent columns of active areas 102, and each row active area 102 is displaced in direction D1 relative to two adjacent rows of active areas 102.
[0011] In addition to the access transistor 100, bit lines BL and bit line contact structures 104 are formed on the semiconductor substrate in the intermediate stage shown in FIG. 1A. One drain / source of each access transistor 100 is connected to a bit line BL through a bit line contact structure 104. The extension direction of the bit line BL may be perpendicular to the extension direction of the word line WL. In an example where the word line WL extends along direction D1, the bit line BL may extend along direction D2. In an embodiment where each active region 102 is shared by two access transistors 100, the bit line BL may be connected to the portion of the active region 102 that serves as a common drain / source through the bit line contact structure 104.
[0012] In addition to connecting one of their drain / source terminals to the bit line BL, each access transistor 100 also connects its other drain / source terminal to the storage capacitor to be formed subsequently. In an embodiment where each active region 102 is interleaved across two word lines WL and shared by two access transistors 100, each active region 102 uses its middle portion located between the two interleaved word lines WL as the common drain / source terminal of the two access transistors 100 and connects to a bit line BL, while its end portions on both sides are connected to the storage capacitor to be formed subsequently. As shown in FIG1A, the end portions of the active regions 102 are each located between the two word lines WL.
[0013] Next, according to some embodiments, an insulating structure will be formed between the character lines WL, which defines a capacitor contact structure for connecting the end portion of the active region 102 to the storage capacitor.
[0014] Referring to Figure 1B, an insulating structure 106 is formed between character lines WL and defines the location of the subsequently formed capacitive contact structure. In some embodiments, the location of the capacitive contact structure is defined using self-aligned double patterning (SADP) technology. In these embodiments, after forming the insulating structure 106, a filler material is formed around the insulating structure 106, and then the insulating structure 106 is removed to expose the opening defined by the insulating structure 106. The opening is used to accommodate the capacitive contact structure.
[0015] Referring to FIG2A, a first insulating material layer 202 is first formed on the substrate structure 200, and a core pattern 204 is formed on the first insulating material layer 202. Although not specifically illustrated, the substrate structure 200 includes at least the structure shown in FIG1A. The first insulating material layer 202 completely covers the substrate structure 200 and will be patterned into the insulating structure 106 shown in FIG1B in subsequent steps. The core pattern 204 is used to form an etch mask for patterning the first insulating material layer 202. In some embodiments, a liner 206 is pre-formed on the first insulating material layer 202 before forming the core pattern 204.
[0016] In the step shown in FIG2B, a shell layer 208 conformally covering the structure shown in FIG2A is formed. Specifically, the first lateral extension 208a of the shell layer 208 covers the top surface of the core pattern 204, while the longitudinal extension 208b of the shell layer 208 covers the sidewalls of the core pattern 204. In addition, the second lateral extension 208c of the shell layer 208 extends laterally between the core patterns 204.
[0017] In the steps shown in FIG2C, an isotropic etching process is performed to remove the first lateral extension 208a and the second lateral extension 208c of the shell 208, and to remove the core pattern 204. As a result, the longitudinal extension 208b of the shell 208 originally on both sides of each core pattern 204 is left, which is also called a mask 210. In this way, each core pattern 204 is converted into two masks 210, and the pattern pitch is halved.
[0018] In the steps shown in FIG2D, the portion of the first insulating material layer 202 not covered by the mask 210 is removed by an etching process, and then the mask 210 is removed. As a result, the remaining portion of the first insulating material layer 202 forms the insulating structure 106 as illustrated with FIG1B.
[0019] In the steps shown in FIG. 2E, a second insulating material layer 212 is formed comprehensively. The second insulating material layer 212 fills the space around the insulating structure 106 and can be formed to a height higher than the top of the insulating structure 106. Furthermore, the material of the second insulating material layer 212 is selected to have a sufficient etch selectivity relative to the insulating structure 106. As an example, if the material of the insulating structure 106 (i.e., the material of the first insulating material layer 202) is silicon oxide, the material of the second insulating material layer 212 can be silicon nitride.
[0020] In the step shown in FIG2F, the second insulating material layer 212 is planarized until the insulating structure 106 is exposed. Subsequently, the insulating structure 106 is removed, and an opening T is formed in the second insulating material layer 212. In subsequent steps, a capacitive contact structure (not shown) is formed in the opening T.
[0021] As can be seen from the above method, a mask 210 with double the quantity and halved pitch is defined by the core pattern 204, and the outline of the insulating structure 106 is defined by the mask 210. Furthermore, an opening T in the second insulating material layer 212 is defined by removing the insulating structure 106, which determines the position of the capacitor contact structure. Therefore, the pattern of the capacitor contact structure is defined by the insulating structure 106, and the pattern of the insulating structure 106 is influenced by the core pattern 204.
[0022] As a result of continuous miniaturization, the spacing between the insulating structure 106 and the word line WL becomes very short (as shown in Figure 1B). In certain cases, the insulating structure 106 may even overlap the word line WL. This may cause the capacitive contact structure to be inadequately spaced from the word line WL, potentially leading to leakage current or increased parasitic capacitance between the two.
[0023] To verify the above-mentioned problem, in addition to forming the structure shown in FIG. 1B in the wafer region of the semiconductor substrate, a test structure is also formed in the dicing region of the semiconductor substrate. The test structure in the dicing region is the same as the array structure in the wafer region, but the test structure includes fewer repeating units and differs in the design of the insulating structure. By observing the relative positional relationship between the insulating structure 106 and the word line WL in the test structure, the relative positional relationship between the insulating structure 106 and the word line WL in the wafer region can be accurately determined.
[0024] As shown in FIG3A, the semiconductor wafer 300 includes an array of wafer regions 302 and dicing channels 304 extending between the wafer regions 302. The array structure shown in FIG1B is disposed in the wafer regions 302, while the test structure 306 is disposed in the dicing channel 304. The test structure 306 is similar to the array structure in the wafer regions 302, and also includes active regions 102, word lines WL, bit line contact structures 104, bit lines BL, and insulating structures 106. However, compared to the array structure in the wafer regions 302, the test structure 306 includes fewer repeating units, and differs in the pitch of the insulating structure 106.
[0025] Specifically, the insulating structure 106 in the wafer region 302 has a pitch P1, while the insulating structure 106 in the test structure 306 of the dicing region 304 has a pitch P2 greater than the pitch P1. In some embodiments, the pitch P2 is approximately twice the pitch P1. In these embodiments, the insulating structure 106 and word lines WL are alternately arranged in the wafer region 302, while the insulating structures 106 in the test structure 306 of the dicing region 304 are spaced apart between the word lines WL. Specifically, in the test structure 306 of the dicing region 304, an insulating structure 106 is placed every two word lines WL in the direction D2. This results in two word lines WL being placed between adjacent insulating structures 106 in the test structure 306. In contrast, an insulating structure 106 is placed every other word line WL in the wafer region 302, resulting in only a single word line WL between adjacent insulating structures 106.
[0026] Since the insulating structures 106 are spaced apart between the character lines WL in the test structure 306 of the cut channel area 304, even when the spacing between the insulating structure 106 and the adjacent character line WL is quite short or even partially overlaps, at least a partial outline of the character line WL can still be observed. In this way, it is still possible to verify whether the two maintain an appropriate distance by observing the outline of each insulating structure 106 and the partial outline of the adjacent character line WL. For example, when the opposite sides of the insulating structure 106a are quite close to the near edges N1 and N2 of the character lines WL1 and WL2, it is not easy to observe the spacing between the opposite sides of the insulating structure 106a and the near edges N1 and N2 of the character lines WL1 and WL2. Even so, the relative positional relationship between the insulating structure 106a and the word lines WL1 and WL2 can still be identified by the relationship between the opposite sides of the insulating structure 106a and the far edges F1 and F2 of the word lines WL1 and WL2, since no insulating structure 106 is provided at the far edges F1 and F2 of the word lines WL1 and WL2. Accordingly, the relative positional relationship between the insulating structure 106 and the word lines WL in the chip area 302 can be accurately identified by observing the insulating structure 106 and the word lines WL in the test structure 306.
[0027] In embodiments where the insulating structure 106 is defined using a self-aligned dual patterning technique (described with reference to Figures 2A to 2F), the design shown in Figure 3A can be achieved by having the core pattern 204 in the wafer region 302 and the core pattern 204 in the test structure 306 of the dicing region 304 have different widths and pitches. Specifically, in these embodiments, the width W204 of the core pattern 204 in the test structure 306 is approximately twice the width W204 of the core pattern 204 in the wafer region 302, and the pitch P204 of the core pattern 204 in the test structure 306 is approximately twice the pitch P204 of the core pattern 204 in the wafer region 302.
[0028] In the embodiment where self-aligned dual patterning is used to define both the character line WL and the insulating structure 106, the center line of the core pattern 204 within the test structure 306 used to define the insulating structure 106 is substantially aligned with the center line of the core pattern (not shown) used to define the character line WL. In contrast, the center line of the core pattern 204 within the wafer region 302 used to define the insulating structure 106 is offset relative to the center line of the core pattern (not shown) used to define the character line WL.
[0029] Referring to Figure 3B, when the pitch of the character line WL fluctuates, the pitch of the character line WL alternates. As a result, the character lines WL on both sides of each insulating structure 106 may move toward the insulating structure 106 between them, and partially overlap with the insulating structure 106 between them. Even so, each character line WL has at least one other side that does not overlap with any insulating structure 106. This means that the relative positional relationship between the insulating structure 106 and the character line WL in the chip area 302 can be verified by observing the relationship between the outline of each insulating structure 106 in the test structure 306 and the outline of the unshielded side of the adjacent character line WL. Since the pitch of the insulating structure 106 in the test structure 306 is increased, even if a severe character line WL pitch fluctuation occurs, the character line WL can be prevented from being completely obscured, and the exposed portion of the character line WL can be used for pattern verification.
[0030] In the embodiments described above, a self-aligned dual patterning technique is used to define the capacitive contact structure. In other embodiments, a self-aligned reverse patterning technique is used to define the capacitive contact structure.
[0031] The self-aligned reverse patterning process is similar to the self-aligned dual patterning process in the first half, and also includes the steps described with reference to Figures 2A and 2B. After forming the shell 208, as shown in Figure 4A, the second lateral extension 208c of the shell 208 is removed, leaving the first lateral extension 208a and the longitudinal extension 208b, and a dielectric layer 500 is formed to fully cover the resulting structure. In some embodiments, the first lateral extension 208a of the shell 208 may also be removed before forming the dielectric layer 500, leaving only the longitudinal extension 208b of the shell 208. In order to selectively remove the retained portions of the shell 208 in subsequent steps, the material of the shell 208 should have a sufficient etch selectivity relative to the materials of the dielectric layer 500 and the core pattern 204.
[0032] At the stage shown in FIG4B, the top of the dielectric layer 500 is first removed to expose the remaining portion of the shell layer 208. Then, the remaining portion of the shell layer 208 is selectively removed, leaving only the core pattern 204 and the remaining portion of the dielectric layer 500. Next, an etching operation is performed using the core pattern 204 and the remaining portion of the dielectric layer 500 as a mask. As a result, the portion of the first insulating material layer 202 (and the substrate 206) not covered by the mask is removed, and an opening T is formed in the first insulating material layer 202.
[0033] At the stage shown in FIG. 4C, a second insulating material layer 502 is formed on the current structure. Specifically, the second insulating material layer 502 fills the opening T in the first insulating material layer 202 and extends further on the top surface of the first insulating material layer 202. In order to selectively remove the first insulating material layer 202 in subsequent steps, the material of the second insulating material layer 502 has sufficient etch selectivity relative to the material of the first insulating material layer 202.
[0034] At the stage shown in FIG4D, the top of the second insulating material layer 502 can be removed until the first insulating material layer 202 is exposed. As a result, the portion of the second insulating material layer 502 that fills the opening T in the first insulating material layer 202 is left. Next, the first insulating material layer 202 can be selectively removed, leaving the remaining portion of the second insulating material layer 502, which is also referred to as the insulating structure 504.
[0035] Subsequently, a capacitive contact structure (not shown) is formed between the insulating structures 504. As can be seen from the above method, the longitudinal extension 208b of the shell layer 208 is defined by the core pattern 204, which further defines the opening T in the first insulating material layer 202. The opening T determines the position of the insulating structure 504, and the gap between the insulating structures 504 determines the position of the capacitive contact structure.
[0036] The embodiment in FIG5 is similar to that in FIG3A, except that in the embodiment shown in FIG5, the position of the capacitor contact structure is defined by the gap between the insulating structures 504. As shown in FIG5, in the wafer region 302, the insulating structures 504 overlap the word lines WL and are arranged periodically with a pitch P1. On the other hand, in the test structure 606 of the dicing track 304, the insulating structures 504 are located between adjacent word lines WL and are arranged periodically with a pitch P2 greater than the pitch P1. In some embodiments, the pitch P2 is approximately twice the pitch P1. In these embodiments, the insulating structures 504 in the test structure 606 are spaced apart between the word lines WL. Furthermore, an insulating structure 504 is provided on one side of each word line WL in the test structure 606, while no insulating structure 504 is provided on the other side, so at least one side is not blocked by any insulating structure 504.
[0037] In embodiments where the insulating structure 504 is defined using a self-aligned reverse patterning technique (described with reference to Figures 4A to 4D), the design shown in Figure 5 can be achieved by having the core pattern 204 in the wafer region 302 and the core pattern 204 in the test structure 606 of the dicing region 304 have different widths and pitches. Specifically, in these embodiments, the width W204 of the core pattern 204 in the test structure 606 is approximately twice the width W204 of the core pattern 204 in the wafer region 302, and the pitch P204 of the core pattern 204 in the test structure 306 is approximately twice the pitch P204 of the core pattern 204 in the wafer region 302.
[0038] In the embodiment where self-aligned dual patterning technology is used to define both the character line WL and the insulating structure 504, the center line of the core pattern 204 used to define the insulating structure 504 within the test structure 606 is substantially aligned with the center line of the core pattern (not shown) used to define the character line WL. On the other hand, the center line of the core pattern 204 used to define the insulating structure 504 within the wafer region 302 is also substantially aligned with the center line of the core pattern (not shown) used to define the character line WL.
[0039] In summary, this disclosure provides a memory volumetric circuit and a method for manufacturing the same. The memory volumetric circuit includes a memory array formed in a wafer region of a semiconductor wafer, and a test structure formed in a dicing region of the semiconductor wafer. The test structure is similar to the memory array in the wafer region and is used to verify the pattern configuration of the memory array in the wafer region. Both the memory array in the wafer region and the test structure in the dicing region include multiple word lines and multiple insulating structures for defining capacitor contact structures. The word lines and insulating structures extend in the same direction. In the wafer region, the word lines and insulating structures are arranged alternately. On the other hand, in the test structure of the dicing region, insulating structures are spaced apart between the word lines. This ensures that at least one side of each word line in the test structure is not covered by any insulating structure. Even if the insulating structures are quite close to or partially overlap the word lines, at least one side of each word line will not be shielded by any insulating structure. In this way, the relative positional relationship between the insulating structure and the word lines within the test structure can still be observed, and this can be used to determine the relative positional relationship between the word lines and the insulating structure within the wafer area. Based on this, the relative positional relationship between the word lines and the capacitor contact structure within the wafer area can be accurately verified. Alternatively, in the test structure of the diced area, the insulating structure overlaps the word lines at intervals. This ensures that the word lines on both sides of the insulating structure are not obscured, allowing for the identification of the relative positional relationship between the word lines and the insulating structure.
[0040] As described above, the lithography verification mechanism provided in this disclosed embodiment can also be applied to the manufacture of other memory volumetric circuits or any integrated circuit with periodic patterns. Specifically, the array structure in the wafer region can be replaced with other functional pattern arrays different from DRAM arrays, and test structures are formed in the dicing channels accordingly according to the method described herein. As an example, the functional pattern array and the test structure respectively include multiple first patterns similar to word lines and multiple second patterns similar to the above-described insulating structure. The second patterns are configured to define the position of a third pattern similar to a capacitor contact structure. Furthermore, the second patterns in the functional pattern array are arranged with a first pitch, and the second patterns in the test structure are arranged with a second pitch greater than the first pitch. In some embodiments, a second pattern is placed every two first patterns in each test structure. In some embodiments, the first patterns and second patterns are arranged alternately in each functional pattern array. In some embodiments, at least one side of each first pattern in each test structure is not adjacent to or overlaps with any second pattern. In some embodiments, the first patterns in each functional pattern array overlap with a second pattern. [Simplified Explanation of the Diagram]
[0041] Figures 1A and 1B are schematic plan views of an intermediate structure of a memory volumetric circuit during the manufacturing process according to some embodiments of the present disclosure. Figures 2A to 2F are schematic cross-sectional views of a series of intermediate structures during a self-aligned double patterning process for forming a capacitor contact structure according to some embodiments of the present disclosure. Figure 3A is a schematic cross-sectional view of an intermediate structure during the stage of forming a first insulating structure for defining the capacitor contact structure according to some embodiments of the present disclosure. Figure 3B is a schematic plan view of the test structure shown in Figure 3A in the case of pitch walking of the character lines. Figures 4A to 4D are schematic cross-sectional views of a series of intermediate structures during a self-aligned reverse patterning process for forming a capacitor contact structure according to some embodiments of the present disclosure. Figure 5 is a schematic cross-sectional view of an intermediate structure during the stage of forming a second insulating structure for defining the capacitor contact structure according to some embodiments of the present disclosure.
Claims
1. A memory volumetric circuit, comprising: Multiple memory arrays located in multiple wafer regions of a semiconductor wafer; The semiconductor wafer includes multiple test structures located in the dicing area of the semiconductor wafer. The multiple memory arrays and the multiple test structures each include multiple word lines extending in the same direction and multiple insulating structures. In each memory array, the multiple insulating structures are configured to define multiple capacitive contact structures. The multiple insulating structures in each memory array are arranged with a first pitch, and the multiple insulating structures in each test structure are arranged with a second pitch greater than the first pitch.
2. The memory volume circuit as claimed in claim 1, wherein one of the plurality of insulating structures is placed every other one of the plurality of word lines in each test structure.
3. The memory volume circuit as claimed in claim 1, wherein the plurality of word lines and the plurality of insulating structures are arranged alternately in each memory array.
4. The memory volume circuit as claimed in claim 2, wherein in each test structure, at least one side of each character line is not adjacent to any of the plurality of insulating structures.
5. The memory volume circuit as claimed in claim 2, wherein in each memory array, the plurality of word lines overlap one of the plurality of insulating structures.
6. The memory volume circuit as claimed in claim 1, wherein the second pitch is approximately twice the first pitch.
7. The memory volume circuit as claimed in claim 1, wherein the positions of the plurality of insulating structures in each memory array define the positions of the plurality of capacitive contact structures.
8. The memory volume circuit as claimed in claim 1, wherein the gaps between the plurality of insulating structures in each memory array define the positions of the plurality of capacitor contact structures.
9. A memory volumetric circuit, comprising: Multiple functional pattern arrays located in multiple wafer regions of a semiconductor wafer; The semiconductor wafer includes multiple test structures located in the dicing zone of the semiconductor wafer, wherein the multiple functional pattern arrays and the multiple test structures each include multiple first patterns and multiple second patterns extending in the same direction, the multiple second patterns in each functional pattern array are configured to define the positions of multiple third patterns, the multiple second patterns in each functional pattern array are arranged with a first pitch, and the multiple second patterns in each test structure are arranged with a second pitch greater than the first pitch.
10. The memory volume circuit as claimed in claim 9, wherein one of the plurality of second patterns is placed in each test structure every other pair of the plurality of first patterns.
11. The memory volume circuit as claimed in claim 9, wherein the plurality of first patterns and the plurality of second patterns are alternately arranged in each functional pattern array.
12. The memory volume circuit as claimed in claim 10, wherein in each test structure, at least one side of each first pattern is not adjacent to any of the plurality of second patterns.
13. The memory volume circuit as claimed in claim 10, wherein in each functional pattern array, the plurality of first patterns overlap one of the plurality of second patterns.
14. A method for manufacturing a memory volumetric circuit, comprising: Multiple memory arrays are formed in multiple wafer regions of a semiconductor wafer; And a plurality of test structures are formed in the dicing area of the semiconductor wafer, wherein the plurality of memory arrays and the plurality of test structures respectively include a plurality of word lines extending in the same direction and a plurality of insulating structures. In each memory array, the plurality of insulating structures are configured to define a plurality of capacitive contact structures. The plurality of insulating structures in each memory array are arranged with a first pitch, and the plurality of insulating structures in each test structure are arranged with a second pitch greater than the first pitch.
15. A method of manufacturing a memory volumetric circuit as claimed in claim 14, wherein forming the plurality of insulating structures in each of the memory arrays or test structures comprises: A first insulating material layer is formed on the substrate structure; Multiple core patterns are formed on the first insulating material layer; A shell is formed that conformally covers the plurality of core patterns and the first insulating material layer; Remove the lateral extension of the shell while retaining the longitudinal extension of the shell covering the sidewalls of the plurality of core patterns; Remove the aforementioned multiple core patterns; The first insulating material layer is etched using the longitudinally extended portion of the shell as a mask, thereby patterning the first insulating material layer into the plurality of insulating structures; And remove the longitudinally extended portion of the shell.
16. A method of manufacturing a memory volumetric circuit as claimed in claim 15, wherein the width of each core pattern in each test structure is approximately twice the width of each core pattern in each memory array, and the pitch of the plurality of core patterns in each test structure is approximately twice the pitch of the plurality of core patterns in each memory array.
17. A method of manufacturing a memory volumetric circuit as claimed in claim 14, wherein forming the plurality of insulating structures in each memory array or each test structure comprises: An insulating material layer is formed on the substrate structure; Multiple core patterns are formed on the insulating material layer; A shell is formed that conformally covers the multiple core patterns; A dielectric layer is formed that fully covers the shell layer and the insulating material layer; Remove the shell layer; The insulating material layer is etched using the multiple core patterns and the dielectric layer as a mask to form multiple openings in the insulating material layer; And filling the plurality of openings with the plurality of insulating structures.
18. A method of manufacturing a memory volume circuit as claimed in claim 17, wherein the width of each core pattern in each test structure is approximately twice the width of each core pattern in each memory array, and the pitch of the plurality of core patterns in each test structure is approximately twice the pitch of the plurality of core patterns in each memory array.