Semiconductor device and formation method thereof

Abstract

A semiconductor device and a formation method thereof are provided. The semiconductor device includes a substrate, a contact pad, a first conductive layer, a dielectric layer, a second conductive layer, a first contact, and isolation element. The substrate includes a memory cell array area and a peripheral area adjacent to the memory cell array area. The contact pad is disposed on the substrate. The first conductive layer is disposed on the contact pad and in the memory cell array area. The dielectric layer is disposed on the first conductive layer and in the memory cell array area and the peripheral area. The second conductive layer is disposed on the dielectric layer and in the memory cell array area and the peripheral area. The first contact is disposed in the peripheral area and is electrically connected to the contact pad in the peripheral area. The isolation element is disposed in the peripheral area and disposed between the second conductive layer and the first contact.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and methods of forming the same, and more particularly to semiconductor devices including isolation elements and methods of forming the same. Prior Technology

[0002] As semiconductor devices miniaturize, the size of memory also continues to shrink to increase density and improve performance. However, this shrinking size can lead to short circuits between the resulting components, degrading the electrical performance of the memory. Summary of the Invention

[0003] In one embodiment, a semiconductor device is provided. The semiconductor device includes a substrate, contact pads, a first conductive layer, a dielectric layer, a second conductive layer, a first contact, and an isolator. The substrate includes a memory array region and a peripheral region adjacent to the memory array region. The contact pads are disposed on the substrate. The first conductive layer is disposed on the contact pads and in the memory array region. The dielectric layer is disposed on the first conductive layer and in the memory array region and the peripheral region. The second conductive layer is disposed on the dielectric layer and in the memory array region and the peripheral region. The first contact is disposed in the peripheral region and electrically connected to the contact pads in the peripheral region. The isolator is disposed in the peripheral region and between the second conductive layer and the first contact.

[0004] In one embodiment, a method for forming a semiconductor device is provided. The method includes providing a substrate, the substrate including a memory array region and a peripheral region adjacent to the memory array region. A contact pad is formed on the substrate. A first conductive layer is formed on the contact pad. A dielectric layer is formed on the first conductive layer. A second conductive layer is formed on the dielectric layer. A first opening is formed in the peripheral region to expose a side surface of the second conductive layer. An isolator is formed on the side surface of the second conductive layer. A first contact is formed in the first opening and on the isolator to electrically connect the first contact to the contact pad in the peripheral region. Simple Explanation of the Diagram

[0005] Figures 1 through 8 show cross-sectional schematic diagrams of a semiconductor device according to an embodiment of the present disclosure at various stages of the fabrication method. Figures 9 through 12 show cross-sectional schematic diagrams of a semiconductor device according to another embodiment of the present disclosure at various stages of the formation method. Implementation

[0006] The following examples are described in detail with reference to the accompanying drawings, but the provided examples are not intended to limit the scope of the invention. For ease of understanding, the same components will be designated with the same symbols in the following description.

[0007] Figures 1 through 8 show cross-sectional schematic diagrams of various stages of a semiconductor device formation method according to some embodiments of the present disclosure. Referring to Figure 1, a substrate 10 is provided. The substrate 10 may include a memory array region CA and a peripheral region PA, and the peripheral region PA may be adjacent to the memory array region CA. The substrate 10 may be a wafer such as a silicon wafer, an insulating layer-covered semiconductor substrate, or a bulk semiconductor substrate. The substrate 10 may be a multilayer substrate or a gradient substrate. The substrate 10 may include elemental semiconductors, including silicon and germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP; and similar combinations thereof, but the present disclosure is not limited thereto. The substrate 10 may be a doped or undoped semiconductor substrate. For example, the substrate 10 may include silicon.

[0008] As shown in Figure 1, a contact pad 12 may be provided on the substrate 10. The contact pad 12 may include a conductive material. The conductive material may include amorphous silicon; polycrystalline silicon; polycrystalline silicon germanium; metals such as tungsten, copper, silver, gold, cobalt, and titanium; metal nitrides such as tungsten nitride and titanium nitride; conductive metal oxides; the like or combinations thereof, but this disclosure is not limited thereto. The contact pad 12 may be formed by performing deposition processes such as chemical vapor deposition (CVD), physical vapor deposition, similar processes or combinations thereof; and removal processes such as etching processes, similar processes or combinations thereof. The etching process may include dry etching and wet etching. Dry etching may include plasma etching, plasmaless gas etching, sputtering etching, ion polishing, reactive ion etching or similar processes, but this disclosure is not limited thereto. Wet etching may include using an acidic solution, an alkaline solution, or a solvent to remove at least a portion of the structure to be removed. Contact pad 12 can serve as a landing pad that is electrically connected to the storage node contact.

[0009] As shown in Figure 1, an insulating layer 14 can be formed on the contact pad 12. The insulating layer 14 can cover the contact pad 12 in the peripheral region PA and can expose the contact pad 12 in the memory array region CA. Therefore, the position of the contact pad 12 for electrical connection with other components can be adjusted by controlling the pattern of the insulating layer 14. The insulating layer 14 can be a single layer or a multilayer structure. The insulating layer 14 may include nitrides such as silicon nitride, oxides such as silicon oxide and germanium silicon oxide, oxynitrides such as silicon oxynitride, and combinations thereof, but this disclosure is not limited thereto. For example, the insulating layer 14 may include silicon nitride. The insulating layer 14 can be formed by performing a deposition process such as CVD.

[0010] As shown in Figure 1, a capacitor structure CS can be formed on the contact pad 12. In one embodiment, a conductive layer 20 can be formed on the contact pad 12 in the memory array region CA to electrically connect the conductive layer 20 to the contact pad 12 in the memory array region CA. The conductive layer 20 can be disposed in the memory array region CA and not in the peripheral region PA. The material and formation method of the conductive layer 20 can be the same as or different from the material and formation method of the contact pad 12. The conductive layer 20 may include a conductive material. For example, the conductive layer 20 may include titanium nitride.

[0011] As shown in Figure 1, a dielectric layer 22 can be compliantly formed on the conductive layer 20. The dielectric layer 22 can be disposed in the memory array region CA and the peripheral region PA. The material and formation method of the dielectric layer 22 can be the same as or different from the material and formation method of the insulating layer 14. The dielectric layer 22 may include a high dielectric constant dielectric material. The high dielectric constant dielectric material may include metal oxides, metal nitrides, metal silicides, transition metal oxides, transition metal nitrides, transition metal silicides, metal oxynitrides, metal aluminates, their analogs, or combinations thereof.

[0012] As shown in Figure 1, a conductive layer 24 can be formed on the dielectric layer 22 in a blanket manner. The conductive layer 24 can be disposed in the memory array region CA and the peripheral region PA. The material and formation method of the conductive layer 24 can be the same as or different from the material and formation method of the conductive layer 20. The conductive layer 24 may include a conductive material. For example, the conductive layer 24 may include polycrystalline silicon germanium. The conductive layer 20 can serve as the lower electrode, the conductive layer 24 can serve as the upper electrode or the cell plate, and the dielectric layer 22 is disposed between the conductive layer 20 and the conductive layer 24. Therefore, the conductive layer 20, the dielectric layer 22, and the conductive layer 24 can together serve as the capacitor structure CS.

[0013] As shown in Figure 1, a planarization layer 30 can be formed on the capacitor structure CS in a blanket manner. Specifically, the planarization layer 30 can be formed on the conductive layer 24 in a blanket manner. The planarization layer 30 can be disposed in the memory array region CA and the peripheral region PA. The material and formation method of the planarization layer 30 can be the same as or different from the material and formation method of the insulating layer 14. The planarization layer 30 can be a single-layer or multi-layer structure. For example, the planarization layer 30 may include silicon oxide.

[0014] Referring to Figure 2, a mask layer 32 can be formed on the planarization layer 30, and a photoresist layer 34 can be formed on the mask layer 32. The mask layer 32 may include a carbon-based mask. The photoresist layer 34 may include a positive photoresist or a negative photoresist. The opening 35 in the photoresist layer 34 may correspond to the subsequently formed opening 36 (as shown in Figure 3 below).

[0015] Referring to Figure 3, an opening 36 is formed in the peripheral region PA by performing a first removal process. Specifically, the opening 36 can penetrate the planarization layer 30, the conductive layer 24, the dielectric layer 22, and the insulating layer 14, but does not penetrate the contact pad 12. The opening 36 can expose the side surface 30S of the planarization layer 30, the side surface 24S of the conductive layer 24, the side surface 22S of the dielectric layer 22, the side surface 14S of the insulating layer 14, and the top surface of the contact pad 12 in the peripheral region PA. The first removal process may include an etching process.

[0016] Please refer to Figure 4 to remove the mask layer 32 and the photoresist layer 34 to expose the top surface of the planarization layer 30. The photoresist layer 34 can be removed by a removal process such as an ashing process, and the mask layer 32 can be removed by a removal process such as an etching process.

[0017] Referring to Figure 5, an insulating element 40 is formed in the opening 36 to cover the conductive layer 24 exposed by the opening 36. The insulating element 40 can be formed by a deposition process or an oxidation process. The insulating element 40 may include oxides such as silicon oxide and germanium silicon oxide, nitrides such as silicon nitride, oxynitrides such as silicon oxynitride, and similar combinations thereof, but this disclosure is not limited thereto.

[0018] In one embodiment, the material of the spacer 40 can be compliantly formed on the top surface of the planarization layer 30 and in the opening 36. For example, the material of the spacer 40 can be formed by a deposition process such as an ALD process. Then, a removal process can be used to remove part of the material of the spacer 40 to expose the top surface of the planarization layer 30 and the top surface of the contact pad 12. The spacer 40 can be formed on the side surfaces 30S of the planarization layer 30, the side surfaces 24S of the conductive layer 24, the side surfaces 22S of the dielectric layer 22, and the side surfaces 14S of the insulating layer 14 exposed in the opening 36. In other words, the spacer 40 can be formed on the sidewalls 36W of the opening 36 and can substantially completely cover the sidewalls 36W of the opening 36. The spacer 40 can contact the contact pad 12 in the peripheral region PA.

[0019] Referring to Figure 6, a first contact 50 is formed in the opening 36 and on the contact pad 12 to electrically connect the first contact 50 to the contact pad 12 in the peripheral region PA. The first contact 50 may be disposed in the peripheral region PA and not in the memory array region CA. In one embodiment, a liner 52 is formed in the opening 36 and on the contact pad 12, and conductive pillars 54 are formed on the liner 52. The materials and formation methods of the liner 52 and conductive pillars 54 may be the same as or different from those of the conductive layer 20. Next, a planarization process such as chemical mechanical polishing (CMP) is performed to remove portions of the liner 52 and portions of the conductive pillars 54 to expose the top surface of the planarization layer 30, thereby forming the first contact 50. For example, the liner 52 may include titanium nitride, and the conductive pillars 54 may include tungsten.

[0020] As shown in Figure 6, the isolator 40 surrounds the first contact 50 and electrically isolates the first contact 50 from the conductive layer 24 and other components. Specifically, the isolator 40 is disposed at least between the conductive layer 24 and the first contact 50. The isolator 40 may be located between the conductive layer 24 and the substrate 52. Accordingly, the isolator 40 prevents short circuits between the conductive layer 24 and the first contact 50.

[0021] Referring to Figure 7, a second removal process is performed to form an opening 66 in the memory array region CA, thereby exposing the top surface of the conductive layer 24 of the memory array region CA. In one embodiment, the second removal process can be performed by forming a mask layer 62 on the planarization layer 30 and a photoresist layer 64 on the mask layer 62. Specifically, the opening 66 can penetrate the planarization layer 30 of the memory array region CA but does not penetrate the conductive layer 24.

[0022] As shown in Figures 3 and 7, in one embodiment, the second removal process for forming opening 66 and the first removal process for forming opening 36 are performed in different processes. The first removal process is performed before the formation of the first contact 50, and the second removal process is performed after the formation of the first contact 50. Specifically, since the first removal process causes opening 36 to penetrate the conductive layer 24 in the peripheral region PA, and the second removal process causes opening 66 to not penetrate the conductive layer 24 in the memory array region CA, the alignment requirements of the first removal process are greater than those of the second removal process. Furthermore, since the first removal process must further penetrate the conductive layer 24 and the dielectric layer 22 and insulating layer 14 beneath the conductive layer 24 to expose the contact pad 12, if the first removal process and the second removal process are performed simultaneously, the conductive layer 24 and the material beneath it in the memory array region CA may be over-etched. Therefore, according to this disclosure, when the first removal process and the second removal process are performed in different process channels, the etching parameters (such as etching depth and etching time) of the first removal process and the second removal process can be easily and independently controlled, the process margin of the etching process can be improved, and / or the capacitor structure CS in the memory array region CA can be avoided.

[0023] Referring to Figure 8, a second contact 70 is formed in the opening 66 to electrically connect the second contact 70 to the capacitor structure CS in the memory array region CA, thereby obtaining the semiconductor device 1. The second contact 70 may be disposed in the memory array region CA and not in the peripheral region PA. In one embodiment, a substrate 72 is formed in the opening 66, and conductive pillars 74 are formed on the substrate 72. The materials and formation methods of the substrate 72 and conductive pillars 74 may be the same as or different from those of the conductive layer 20. Next, a planarization process such as CMP is performed to remove a portion of the substrate 72 and a portion of the conductive pillars 74 to expose the top surface of the planarization layer 30, thereby forming the second contact 70. For example, the substrate 72 may include titanium nitride, and the conductive pillars 74 may include tungsten.

[0024] Figures 9 through 12 show cross-sectional schematic diagrams of a semiconductor device according to another embodiment of the present disclosure at various stages of the fabrication method. Figure 9 can be continued from the process of Figure 4 of the previous embodiment. This embodiment is largely similar to the previous embodiment, with the main difference being that the insulating member 42 in this embodiment only covers the side surface 24S of the conductive layer 24 exposed by the opening 36, and does not cover the side surface 30S of the planarization layer 30, the side surface 22S of the dielectric layer 22, and the side surface 14S of the insulating layer 14.

[0025] Referring to Figure 9, an isolation element 42 can be formed in the opening 36 by an oxidation process to cover the conductive layer 24 exposed in the opening 36. Specifically, the isolation element 42 can be formed on the side surface 24S of the conductive layer 24 exposed in the opening 36, and the isolation element 42 is not formed on the side surface 30S of the planarization layer 30, the side surface 22S of the dielectric layer 22, and the side surface 14S of the insulating layer 14. As shown in Figure 9, the oxidation process completely oxidizes the conductive layer 24 exposed in the opening 36 into the isolation element 42, so that the remaining conductive layer 24 is electrically isolated from the first contact 50 subsequently formed in the opening 36.

[0026] As shown in Figure 9, in one embodiment, the oxidation process may include a thermal oxidation process, an in-situ steam generation (ISSG) process, a similar process, or a combination thereof, but this disclosure is not limited thereto. In embodiments using an oxidation process, the spacer 42 may be an oxide formed by the oxidation process. For example, since the oxidation process is performed on the conductive layer 24 comprising polycrystalline silicon germanium, the spacer 42 may be silicon germanium oxide, but this disclosure is not limited thereto. In one embodiment, the spacer 42 may include an oxide of the material of the conductive layer 24. In another embodiment, the spacer 42 may be used in combination with the spacer 40.

[0027] Please refer to Figure 10, which is similar to Figure 6. A first contact 50 can be formed in the opening 36, and the first contact 50 can be electrically connected to the contact pad 12 in the peripheral area PA.

[0028] As shown in Figure 10, the isolator 42 surrounds the first contact 50 and electrically isolates the first contact 50 from the conductive layer 24. Specifically, the isolator 42 is disposed between the conductive layer 24 and the first contact 50. The isolator 42 may be located between the conductive layer 24 and the substrate 52. Accordingly, the isolator 42 prevents short circuits between the conductive layer 24 and the first contact 50.

[0029] Please refer to Figure 11. Similar to Figure 7, an opening 66 can be formed in the memory array region CA to expose the top surface of the capacitor structure CS.

[0030] Referring to Figure 12, similar to Figure 8, a second contact 70 can be formed in the opening 66 so that the second contact 70 is electrically connected to the capacitor structure CS in the memory array region CA, and a semiconductor device 2 is obtained.

[0031] It is worth mentioning that, generally, the conductive layer 24 in the peripheral PA region is completely removed to avoid a short circuit between the conductive layer 24 and the first contact 50. However, if a removal process is performed to completely remove the conductive layer in the peripheral PA region, insufficient etching may still cause a short circuit due to the residual portion of the conductive layer in the peripheral PA region, or excessive etching may cause damage to other components. In contrast, according to the embodiments disclosed herein, after forming the conductive layer 24 and the planarization layer 30, the opening 36, the first contact 50, and the separator 40 / 42 disposed between the conductive layer 24 and the first contact 50 in the peripheral PA region are directly formed in the peripheral PA region. The present disclosure does not perform an additional removal process to completely remove the conductive layer 24 in the peripheral PA region.

[0032] Therefore, by forming an isolation element between the conductive layer in the peripheral region and the first contact, this disclosure avoids short circuits between the first contact and the conductive layer without completely removing the conductive layer in the peripheral region. Furthermore, the isolation element ensures sufficient insulation and improves process margin. Additionally, since the second opening and the first opening are formed in different processes, etching parameters can be easily and independently controlled, improving the process margin of the etching process and / or preventing damage to the capacitor structure in the memory array region. Accordingly, the formation method disclosed herein achieves the effects of avoiding short circuits, providing sufficient insulation, improving electrical performance, and / or improving reliability.

[0033] The above outlines several embodiments to enable those skilled in the art to better understand the viewpoints of the embodiments disclosed herein. Those skilled in the art should understand that equivalent processes and structures do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and replacements without departing from the spirit and scope of this disclosure.

[0034] 1,2: Semiconductor devices 10:Substrate 12: Contact pad 14: Insulation layer 14S, 22S, 24S, 30S: Side surface 20,24: Conductive layer 22: Dielectric layer 30: Planarization layer 30B: Bottom surface 32,62: Masking layer 34,64: Photoresist layer 35, 36, 66: Opening 36W: Sidewall 40, 42: Isolation components 50: First contact object 52,72: Lining 54, 74: Conductive pillars 70: Second contact object CA: Memory Array Area CS: Capacitor Structure PA: Surrounding Area

Claims

1. A semiconductor device, comprising: A substrate includes a memory array region and a peripheral region adjacent to the memory array region; A contact pad is disposed on the substrate; a first conductive layer is disposed on the contact pad and in the memory array region; a dielectric layer is disposed on the first conductive layer and in the memory array region and the peripheral region; a second conductive layer is disposed on the dielectric layer and in the memory array region and the peripheral region; a first contact is disposed in the peripheral region and electrically connected to the contact pad in the peripheral region; and an isolator is disposed in the peripheral region and between the second conductive layer and the first contact, wherein the isolator is disposed on one side surface of the second conductive layer in the peripheral region.

2. The semiconductor device as claimed in claim 1, wherein the isolator is disposed on one side surface of the dielectric layer in the peripheral region.

3. The semiconductor device as claimed in claim 1, wherein the isolator surrounds the first contact.

4. The semiconductor device as claimed in claim 1, wherein the isolator comprises an oxide of the material of the second conductive layer.

5. A method for forming a semiconductor device, comprising: A substrate is provided, the substrate including a memory array region and a peripheral region adjacent to the memory array region; A contact pad is formed on the substrate; a first conductive layer is formed on the contact pad; a dielectric layer is formed on the first conductive layer; a second conductive layer is formed on the dielectric layer; a first opening is formed in the peripheral area to expose one side surface of the second conductive layer. An isolator is formed on the side surface of the second conductive layer; and a first contact is formed in the first opening and on the isolator, so that the first contact is electrically connected to the contact pad in the peripheral area.

6. The forming method as described in claim 5, wherein forming the spacer on the side surface of the second conductive layer comprises: The material of the spacer is conformally formed in the first opening; And remove the material of the insulating element to expose the contact pad.

7. The method of forming as described in claim 6, further comprising: forming a planarization layer on the second conductive layer; wherein, The first opening is formed to penetrate the planarization layer and expose one side surface of the planarization layer, and the insulating member is formed on the side surface of the second conductive layer and the side surface of the planarization layer.

8. The method of forming as claimed in claim 5, wherein the insulating member is formed on the side surface of the second conductive layer by performing an oxidation process on the side surface of the second conductive layer.

9. The method of forming as described in claim 8, further comprising: forming a planarization layer on the second conductive layer; wherein, The first opening is formed to penetrate the planarization layer and expose one side surface of the planarization layer, and the spacer is formed therein, with the spacer exposing the side surface of the planarization layer.

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